2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
30 #include <asm/system.h>
31 #include <mach/hardware.h>
38 #ifndef CONFIG_ARCH_OMAP1
39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
46 #define OMAP_DMA_ACTIVE 0x01
47 #define OMAP_DMA_CCR_EN (1 << 7)
48 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
50 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
52 static int enable_1510_mode;
60 void (*callback)(int lch, u16 ch_status, void *data);
63 #ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
75 struct dma_link_info {
77 int no_of_lchs_linked;
88 static struct dma_link_info *dma_linked_lch;
90 #ifndef CONFIG_ARCH_OMAP1
92 /* Chain handling macros */
93 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
99 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109 #define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
124 static int dma_lch_count;
125 static int dma_chan_count;
126 static int omap_dma_reserve_channels;
128 static spinlock_t dma_chan_lock;
129 static struct omap_dma_lch *dma_chan;
130 static void __iomem *omap_dma_base;
132 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
133 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
134 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
135 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
136 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
137 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
140 static inline void disable_lnk(int lch);
141 static void omap_disable_channel_irq(int lch);
142 static inline void omap_enable_channel_irq(int lch);
144 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
147 #define dma_read(reg) \
150 if (cpu_class_is_omap1()) \
151 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
153 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 #define dma_write(val, reg) \
159 if (cpu_class_is_omap1()) \
160 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
162 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
165 #ifdef CONFIG_ARCH_OMAP15XX
166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
167 int omap_dma_in_1510_mode(void)
169 return enable_1510_mode;
172 #define omap_dma_in_1510_mode() 0
175 #ifdef CONFIG_ARCH_OMAP1
176 static inline int get_gdma_dev(int req)
178 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
179 int shift = ((req - 1) % 5) * 6;
181 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
184 static inline void set_gdma_dev(int req, int dev)
186 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
187 int shift = ((req - 1) % 5) * 6;
191 l &= ~(0x3f << shift);
192 l |= (dev - 1) << shift;
196 #define set_gdma_dev(req, dev) do {} while (0)
200 static void clear_lch_regs(int lch)
203 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
205 for (i = 0; i < 0x2c; i += 2)
206 __raw_writew(0, lch_base + i);
209 void omap_set_dma_priority(int lch, int dst_port, int priority)
214 if (cpu_class_is_omap1()) {
216 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
217 reg = OMAP_TC_OCPT1_PRIOR;
219 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
220 reg = OMAP_TC_OCPT2_PRIOR;
222 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
223 reg = OMAP_TC_EMIFF_PRIOR;
225 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
226 reg = OMAP_TC_EMIFS_PRIOR;
234 l |= (priority & 0xf) << 8;
238 if (cpu_class_is_omap2()) {
241 ccr = dma_read(CCR(lch));
246 dma_write(ccr, CCR(lch));
249 EXPORT_SYMBOL(omap_set_dma_priority);
251 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
252 int frame_count, int sync_mode,
253 int dma_trigger, int src_or_dst_synch)
257 l = dma_read(CSDP(lch));
260 dma_write(l, CSDP(lch));
262 if (cpu_class_is_omap1()) {
265 ccr = dma_read(CCR(lch));
267 if (sync_mode == OMAP_DMA_SYNC_FRAME)
269 dma_write(ccr, CCR(lch));
271 ccr = dma_read(CCR2(lch));
273 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
275 dma_write(ccr, CCR2(lch));
278 if (cpu_class_is_omap2() && dma_trigger) {
281 val = dma_read(CCR(lch));
283 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
284 val &= ~((3 << 19) | 0x1f);
285 val |= (dma_trigger & ~0x1f) << 14;
286 val |= dma_trigger & 0x1f;
288 if (sync_mode & OMAP_DMA_SYNC_FRAME)
293 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
298 if (src_or_dst_synch)
299 val |= 1 << 24; /* source synch */
301 val &= ~(1 << 24); /* dest synch */
303 dma_write(val, CCR(lch));
306 dma_write(elem_count, CEN(lch));
307 dma_write(frame_count, CFN(lch));
309 EXPORT_SYMBOL(omap_set_dma_transfer_params);
311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
315 BUG_ON(omap_dma_in_1510_mode());
317 if (cpu_class_is_omap2()) {
322 w = dma_read(CCR2(lch));
326 case OMAP_DMA_CONSTANT_FILL:
329 case OMAP_DMA_TRANSPARENT_COPY:
332 case OMAP_DMA_COLOR_DIS:
337 dma_write(w, CCR2(lch));
339 w = dma_read(LCH_CTRL(lch));
341 /* Default is channel type 2D */
343 dma_write((u16)color, COLOR_L(lch));
344 dma_write((u16)(color >> 16), COLOR_U(lch));
345 w |= 1; /* Channel type G */
347 dma_write(w, LCH_CTRL(lch));
349 EXPORT_SYMBOL(omap_set_dma_color_mode);
351 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
353 if (cpu_class_is_omap2()) {
356 csdp = dma_read(CSDP(lch));
357 csdp &= ~(0x3 << 16);
358 csdp |= (mode << 16);
359 dma_write(csdp, CSDP(lch));
362 EXPORT_SYMBOL(omap_set_dma_write_mode);
364 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
366 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 l = dma_read(LCH_CTRL(lch));
372 dma_write(l, LCH_CTRL(lch));
375 EXPORT_SYMBOL(omap_set_dma_channel_mode);
377 /* Note that src_port is only for omap1 */
378 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
379 unsigned long src_start,
380 int src_ei, int src_fi)
384 if (cpu_class_is_omap1()) {
387 w = dma_read(CSDP(lch));
390 dma_write(w, CSDP(lch));
393 l = dma_read(CCR(lch));
395 l |= src_amode << 12;
396 dma_write(l, CCR(lch));
398 if (cpu_class_is_omap1()) {
399 dma_write(src_start >> 16, CSSA_U(lch));
400 dma_write((u16)src_start, CSSA_L(lch));
403 if (cpu_class_is_omap2())
404 dma_write(src_start, CSSA(lch));
406 dma_write(src_ei, CSEI(lch));
407 dma_write(src_fi, CSFI(lch));
409 EXPORT_SYMBOL(omap_set_dma_src_params);
411 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
413 omap_set_dma_transfer_params(lch, params->data_type,
414 params->elem_count, params->frame_count,
415 params->sync_mode, params->trigger,
416 params->src_or_dst_synch);
417 omap_set_dma_src_params(lch, params->src_port,
418 params->src_amode, params->src_start,
419 params->src_ei, params->src_fi);
421 omap_set_dma_dest_params(lch, params->dst_port,
422 params->dst_amode, params->dst_start,
423 params->dst_ei, params->dst_fi);
424 if (params->read_prio || params->write_prio)
425 omap_dma_set_prio_lch(lch, params->read_prio,
428 EXPORT_SYMBOL(omap_set_dma_params);
430 void omap_set_dma_src_index(int lch, int eidx, int fidx)
432 if (cpu_class_is_omap2())
435 dma_write(eidx, CSEI(lch));
436 dma_write(fidx, CSFI(lch));
438 EXPORT_SYMBOL(omap_set_dma_src_index);
440 void omap_set_dma_src_data_pack(int lch, int enable)
444 l = dma_read(CSDP(lch));
448 dma_write(l, CSDP(lch));
450 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
452 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
454 unsigned int burst = 0;
457 l = dma_read(CSDP(lch));
460 switch (burst_mode) {
461 case OMAP_DMA_DATA_BURST_DIS:
463 case OMAP_DMA_DATA_BURST_4:
464 if (cpu_class_is_omap2())
469 case OMAP_DMA_DATA_BURST_8:
470 if (cpu_class_is_omap2()) {
474 /* not supported by current hardware on OMAP1
478 case OMAP_DMA_DATA_BURST_16:
479 if (cpu_class_is_omap2()) {
483 /* OMAP1 don't support burst 16
491 dma_write(l, CSDP(lch));
493 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
495 /* Note that dest_port is only for OMAP1 */
496 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
497 unsigned long dest_start,
498 int dst_ei, int dst_fi)
502 if (cpu_class_is_omap1()) {
503 l = dma_read(CSDP(lch));
506 dma_write(l, CSDP(lch));
509 l = dma_read(CCR(lch));
511 l |= dest_amode << 14;
512 dma_write(l, CCR(lch));
514 if (cpu_class_is_omap1()) {
515 dma_write(dest_start >> 16, CDSA_U(lch));
516 dma_write(dest_start, CDSA_L(lch));
519 if (cpu_class_is_omap2())
520 dma_write(dest_start, CDSA(lch));
522 dma_write(dst_ei, CDEI(lch));
523 dma_write(dst_fi, CDFI(lch));
525 EXPORT_SYMBOL(omap_set_dma_dest_params);
527 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
529 if (cpu_class_is_omap2())
532 dma_write(eidx, CDEI(lch));
533 dma_write(fidx, CDFI(lch));
535 EXPORT_SYMBOL(omap_set_dma_dest_index);
537 void omap_set_dma_dest_data_pack(int lch, int enable)
541 l = dma_read(CSDP(lch));
545 dma_write(l, CSDP(lch));
547 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
549 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
551 unsigned int burst = 0;
554 l = dma_read(CSDP(lch));
557 switch (burst_mode) {
558 case OMAP_DMA_DATA_BURST_DIS:
560 case OMAP_DMA_DATA_BURST_4:
561 if (cpu_class_is_omap2())
566 case OMAP_DMA_DATA_BURST_8:
567 if (cpu_class_is_omap2())
572 case OMAP_DMA_DATA_BURST_16:
573 if (cpu_class_is_omap2()) {
577 /* OMAP1 don't support burst 16
581 printk(KERN_ERR "Invalid DMA burst mode\n");
586 dma_write(l, CSDP(lch));
588 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
590 static inline void omap_enable_channel_irq(int lch)
595 if (cpu_class_is_omap1())
596 status = dma_read(CSR(lch));
597 else if (cpu_class_is_omap2())
598 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
600 /* Enable some nice interrupts. */
601 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
604 static void omap_disable_channel_irq(int lch)
606 if (cpu_class_is_omap2())
607 dma_write(0, CICR(lch));
610 void omap_enable_dma_irq(int lch, u16 bits)
612 dma_chan[lch].enabled_irqs |= bits;
614 EXPORT_SYMBOL(omap_enable_dma_irq);
616 void omap_disable_dma_irq(int lch, u16 bits)
618 dma_chan[lch].enabled_irqs &= ~bits;
620 EXPORT_SYMBOL(omap_disable_dma_irq);
622 static inline void enable_lnk(int lch)
626 l = dma_read(CLNK_CTRL(lch));
628 if (cpu_class_is_omap1())
631 /* Set the ENABLE_LNK bits */
632 if (dma_chan[lch].next_lch != -1)
633 l = dma_chan[lch].next_lch | (1 << 15);
635 #ifndef CONFIG_ARCH_OMAP1
636 if (cpu_class_is_omap2())
637 if (dma_chan[lch].next_linked_ch != -1)
638 l = dma_chan[lch].next_linked_ch | (1 << 15);
641 dma_write(l, CLNK_CTRL(lch));
644 static inline void disable_lnk(int lch)
648 l = dma_read(CLNK_CTRL(lch));
650 /* Disable interrupts */
651 if (cpu_class_is_omap1()) {
652 dma_write(0, CICR(lch));
653 /* Set the STOP_LNK bit */
657 if (cpu_class_is_omap2()) {
658 omap_disable_channel_irq(lch);
659 /* Clear the ENABLE_LNK bit */
663 dma_write(l, CLNK_CTRL(lch));
664 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
667 static inline void omap2_enable_irq_lch(int lch)
671 if (!cpu_class_is_omap2())
674 val = dma_read(IRQENABLE_L0);
676 dma_write(val, IRQENABLE_L0);
679 int omap_request_dma(int dev_id, const char *dev_name,
680 void (*callback)(int lch, u16 ch_status, void *data),
681 void *data, int *dma_ch_out)
683 int ch, free_ch = -1;
685 struct omap_dma_lch *chan;
687 spin_lock_irqsave(&dma_chan_lock, flags);
688 for (ch = 0; ch < dma_chan_count; ch++) {
689 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
696 spin_unlock_irqrestore(&dma_chan_lock, flags);
699 chan = dma_chan + free_ch;
700 chan->dev_id = dev_id;
702 if (cpu_class_is_omap1())
703 clear_lch_regs(free_ch);
705 if (cpu_class_is_omap2())
706 omap_clear_dma(free_ch);
708 spin_unlock_irqrestore(&dma_chan_lock, flags);
710 chan->dev_name = dev_name;
711 chan->callback = callback;
715 #ifndef CONFIG_ARCH_OMAP1
716 if (cpu_class_is_omap2()) {
718 chan->next_linked_ch = -1;
722 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
724 if (cpu_class_is_omap1())
725 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
726 else if (cpu_class_is_omap2())
727 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
728 OMAP2_DMA_TRANS_ERR_IRQ;
730 if (cpu_is_omap16xx()) {
731 /* If the sync device is set, configure it dynamically. */
733 set_gdma_dev(free_ch + 1, dev_id);
734 dev_id = free_ch + 1;
737 * Disable the 1510 compatibility mode and set the sync device
740 dma_write(dev_id | (1 << 10), CCR(free_ch));
741 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
742 dma_write(dev_id, CCR(free_ch));
745 if (cpu_class_is_omap2()) {
746 omap2_enable_irq_lch(free_ch);
747 omap_enable_channel_irq(free_ch);
748 /* Clear the CSR register and IRQ status register */
749 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
750 dma_write(1 << free_ch, IRQSTATUS_L0);
753 *dma_ch_out = free_ch;
757 EXPORT_SYMBOL(omap_request_dma);
759 void omap_free_dma(int lch)
763 spin_lock_irqsave(&dma_chan_lock, flags);
764 if (dma_chan[lch].dev_id == -1) {
765 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
767 spin_unlock_irqrestore(&dma_chan_lock, flags);
771 dma_chan[lch].dev_id = -1;
772 dma_chan[lch].next_lch = -1;
773 dma_chan[lch].callback = NULL;
774 spin_unlock_irqrestore(&dma_chan_lock, flags);
776 if (cpu_class_is_omap1()) {
777 /* Disable all DMA interrupts for the channel. */
778 dma_write(0, CICR(lch));
779 /* Make sure the DMA transfer is stopped. */
780 dma_write(0, CCR(lch));
783 if (cpu_class_is_omap2()) {
785 /* Disable interrupts */
786 val = dma_read(IRQENABLE_L0);
788 dma_write(val, IRQENABLE_L0);
790 /* Clear the CSR register and IRQ status register */
791 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
792 dma_write(1 << lch, IRQSTATUS_L0);
794 /* Disable all DMA interrupts for the channel. */
795 dma_write(0, CICR(lch));
797 /* Make sure the DMA transfer is stopped. */
798 dma_write(0, CCR(lch));
802 EXPORT_SYMBOL(omap_free_dma);
805 * @brief omap_dma_set_global_params : Set global priority settings for dma
808 * @param max_fifo_depth
809 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
810 * DMA_THREAD_RESERVE_ONET
811 * DMA_THREAD_RESERVE_TWOT
812 * DMA_THREAD_RESERVE_THREET
815 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
819 if (!cpu_class_is_omap2()) {
820 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
827 reg = (arb_rate & 0xff) << 16;
828 reg |= (0xff & max_fifo_depth);
832 EXPORT_SYMBOL(omap_dma_set_global_params);
835 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
838 * @param read_prio - Read priority
839 * @param write_prio - Write priority
840 * Both of the above can be set with one of the following values :
841 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
844 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
845 unsigned char write_prio)
849 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
850 printk(KERN_ERR "Invalid channel id\n");
853 l = dma_read(CCR(lch));
854 l &= ~((1 << 6) | (1 << 26));
855 if (cpu_is_omap2430() || cpu_is_omap34xx())
856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
858 l |= ((read_prio & 0x1) << 6);
860 dma_write(l, CCR(lch));
864 EXPORT_SYMBOL(omap_dma_set_prio_lch);
867 * Clears any DMA state so the DMA engine is ready to restart with new buffers
868 * through omap_start_dma(). Any buffers in flight are discarded.
870 void omap_clear_dma(int lch)
874 local_irq_save(flags);
876 if (cpu_class_is_omap1()) {
879 l = dma_read(CCR(lch));
880 l &= ~OMAP_DMA_CCR_EN;
881 dma_write(l, CCR(lch));
883 /* Clear pending interrupts */
884 l = dma_read(CSR(lch));
887 if (cpu_class_is_omap2()) {
889 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
890 for (i = 0; i < 0x44; i += 4)
891 __raw_writel(0, lch_base + i);
894 local_irq_restore(flags);
896 EXPORT_SYMBOL(omap_clear_dma);
898 void omap_start_dma(int lch)
902 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
903 int next_lch, cur_lch;
904 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
906 dma_chan_link_map[lch] = 1;
907 /* Set the link register of the first channel */
910 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
911 cur_lch = dma_chan[lch].next_lch;
913 next_lch = dma_chan[cur_lch].next_lch;
915 /* The loop case: we've been here already */
916 if (dma_chan_link_map[cur_lch])
918 /* Mark the current channel */
919 dma_chan_link_map[cur_lch] = 1;
922 omap_enable_channel_irq(cur_lch);
925 } while (next_lch != -1);
926 } else if (cpu_class_is_omap2()) {
927 /* Errata: Need to write lch even if not using chaining */
928 dma_write(lch, CLNK_CTRL(lch));
931 omap_enable_channel_irq(lch);
933 l = dma_read(CCR(lch));
936 * Errata: On ES2.0 BUFFERING disable must be set.
937 * This will always fail on ES1.0
939 if (cpu_is_omap24xx())
940 l |= OMAP_DMA_CCR_EN;
942 l |= OMAP_DMA_CCR_EN;
943 dma_write(l, CCR(lch));
945 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
947 EXPORT_SYMBOL(omap_start_dma);
949 void omap_stop_dma(int lch)
953 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
954 int next_lch, cur_lch = lch;
955 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
957 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
959 /* The loop case: we've been here already */
960 if (dma_chan_link_map[cur_lch])
962 /* Mark the current channel */
963 dma_chan_link_map[cur_lch] = 1;
965 disable_lnk(cur_lch);
967 next_lch = dma_chan[cur_lch].next_lch;
969 } while (next_lch != -1);
974 /* Disable all interrupts on the channel */
975 if (cpu_class_is_omap1())
976 dma_write(0, CICR(lch));
978 l = dma_read(CCR(lch));
979 l &= ~OMAP_DMA_CCR_EN;
980 dma_write(l, CCR(lch));
982 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
984 EXPORT_SYMBOL(omap_stop_dma);
987 * Allows changing the DMA callback function or data. This may be needed if
988 * the driver shares a single DMA channel for multiple dma triggers.
990 int omap_set_dma_callback(int lch,
991 void (*callback)(int lch, u16 ch_status, void *data),
999 spin_lock_irqsave(&dma_chan_lock, flags);
1000 if (dma_chan[lch].dev_id == -1) {
1001 printk(KERN_ERR "DMA callback for not set for free channel\n");
1002 spin_unlock_irqrestore(&dma_chan_lock, flags);
1005 dma_chan[lch].callback = callback;
1006 dma_chan[lch].data = data;
1007 spin_unlock_irqrestore(&dma_chan_lock, flags);
1011 EXPORT_SYMBOL(omap_set_dma_callback);
1014 * Returns current physical source address for the given DMA channel.
1015 * If the channel is running the caller must disable interrupts prior calling
1016 * this function and process the returned value before re-enabling interrupt to
1017 * prevent races with the interrupt handler. Note that in continuous mode there
1018 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1019 * in incorrect return value.
1021 dma_addr_t omap_get_dma_src_pos(int lch)
1023 dma_addr_t offset = 0;
1025 if (cpu_is_omap15xx())
1026 offset = dma_read(CPC(lch));
1028 offset = dma_read(CSAC(lch));
1031 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1032 * read before the DMA controller finished disabling the channel.
1034 if (!cpu_is_omap15xx() && offset == 0)
1035 offset = dma_read(CSAC(lch));
1037 if (cpu_class_is_omap1())
1038 offset |= (dma_read(CSSA_U(lch)) << 16);
1042 EXPORT_SYMBOL(omap_get_dma_src_pos);
1045 * Returns current physical destination address for the given DMA channel.
1046 * If the channel is running the caller must disable interrupts prior calling
1047 * this function and process the returned value before re-enabling interrupt to
1048 * prevent races with the interrupt handler. Note that in continuous mode there
1049 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1050 * in incorrect return value.
1052 dma_addr_t omap_get_dma_dst_pos(int lch)
1054 dma_addr_t offset = 0;
1056 if (cpu_is_omap15xx())
1057 offset = dma_read(CPC(lch));
1059 offset = dma_read(CDAC(lch));
1062 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1063 * read before the DMA controller finished disabling the channel.
1065 if (!cpu_is_omap15xx() && offset == 0)
1066 offset = dma_read(CDAC(lch));
1068 if (cpu_class_is_omap1())
1069 offset |= (dma_read(CDSA_U(lch)) << 16);
1073 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1075 int omap_get_dma_active_status(int lch)
1077 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1079 EXPORT_SYMBOL(omap_get_dma_active_status);
1081 int omap_dma_running(void)
1085 /* Check if LCD DMA is running */
1086 if (cpu_is_omap16xx())
1087 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1090 for (lch = 0; lch < dma_chan_count; lch++)
1091 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1098 * lch_queue DMA will start right after lch_head one is finished.
1099 * For this DMA link to start, you still need to start (see omap_start_dma)
1100 * the first one. That will fire up the entire queue.
1102 void omap_dma_link_lch(int lch_head, int lch_queue)
1104 if (omap_dma_in_1510_mode()) {
1105 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1110 if ((dma_chan[lch_head].dev_id == -1) ||
1111 (dma_chan[lch_queue].dev_id == -1)) {
1112 printk(KERN_ERR "omap_dma: trying to link "
1113 "non requested channels\n");
1117 dma_chan[lch_head].next_lch = lch_queue;
1119 EXPORT_SYMBOL(omap_dma_link_lch);
1122 * Once the DMA queue is stopped, we can destroy it.
1124 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1126 if (omap_dma_in_1510_mode()) {
1127 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1132 if (dma_chan[lch_head].next_lch != lch_queue ||
1133 dma_chan[lch_head].next_lch == -1) {
1134 printk(KERN_ERR "omap_dma: trying to unlink "
1135 "non linked channels\n");
1139 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1140 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1141 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1142 "before unlinking\n");
1146 dma_chan[lch_head].next_lch = -1;
1148 EXPORT_SYMBOL(omap_dma_unlink_lch);
1150 /*----------------------------------------------------------------------------*/
1152 #ifndef CONFIG_ARCH_OMAP1
1153 /* Create chain of DMA channesls */
1154 static void create_dma_lch_chain(int lch_head, int lch_queue)
1158 /* Check if this is the first link in chain */
1159 if (dma_chan[lch_head].next_linked_ch == -1) {
1160 dma_chan[lch_head].next_linked_ch = lch_queue;
1161 dma_chan[lch_head].prev_linked_ch = lch_queue;
1162 dma_chan[lch_queue].next_linked_ch = lch_head;
1163 dma_chan[lch_queue].prev_linked_ch = lch_head;
1166 /* a link exists, link the new channel in circular chain */
1168 dma_chan[lch_queue].next_linked_ch =
1169 dma_chan[lch_head].next_linked_ch;
1170 dma_chan[lch_queue].prev_linked_ch = lch_head;
1171 dma_chan[lch_head].next_linked_ch = lch_queue;
1172 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1176 l = dma_read(CLNK_CTRL(lch_head));
1179 dma_write(l, CLNK_CTRL(lch_head));
1181 l = dma_read(CLNK_CTRL(lch_queue));
1183 l |= (dma_chan[lch_queue].next_linked_ch);
1184 dma_write(l, CLNK_CTRL(lch_queue));
1188 * @brief omap_request_dma_chain : Request a chain of DMA channels
1190 * @param dev_id - Device id using the dma channel
1191 * @param dev_name - Device name
1192 * @param callback - Call back function
1194 * @no_of_chans - Number of channels requested
1195 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1196 * OMAP_DMA_DYNAMIC_CHAIN
1197 * @params - Channel parameters
1199 * @return - Succes : 0
1200 * Failure: -EINVAL/-ENOMEM
1202 int omap_request_dma_chain(int dev_id, const char *dev_name,
1203 void (*callback) (int chain_id, u16 ch_status,
1205 int *chain_id, int no_of_chans, int chain_mode,
1206 struct omap_dma_channel_params params)
1211 /* Is the chain mode valid ? */
1212 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1213 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1214 printk(KERN_ERR "Invalid chain mode requested\n");
1218 if (unlikely((no_of_chans < 1
1219 || no_of_chans > dma_lch_count))) {
1220 printk(KERN_ERR "Invalid Number of channels requested\n");
1224 /* Allocate a queue to maintain the status of the channels
1226 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1227 if (channels == NULL) {
1228 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1232 /* request and reserve DMA channels for the chain */
1233 for (i = 0; i < no_of_chans; i++) {
1234 err = omap_request_dma(dev_id, dev_name,
1235 callback, NULL, &channels[i]);
1238 for (j = 0; j < i; j++)
1239 omap_free_dma(channels[j]);
1241 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1244 dma_chan[channels[i]].prev_linked_ch = -1;
1245 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1248 * Allowing client drivers to set common parameters now,
1249 * so that later only relevant (src_start, dest_start
1250 * and element count) can be set
1252 omap_set_dma_params(channels[i], ¶ms);
1255 *chain_id = channels[0];
1256 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1257 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1258 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1259 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1261 for (i = 0; i < no_of_chans; i++)
1262 dma_chan[channels[i]].chain_id = *chain_id;
1264 /* Reset the Queue pointers */
1265 OMAP_DMA_CHAIN_QINIT(*chain_id);
1267 /* Set up the chain */
1268 if (no_of_chans == 1)
1269 create_dma_lch_chain(channels[0], channels[0]);
1271 for (i = 0; i < (no_of_chans - 1); i++)
1272 create_dma_lch_chain(channels[i], channels[i + 1]);
1277 EXPORT_SYMBOL(omap_request_dma_chain);
1280 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1281 * params after setting it. Dont do this while dma is running!!
1283 * @param chain_id - Chained logical channel id.
1286 * @return - Success : 0
1289 int omap_modify_dma_chain_params(int chain_id,
1290 struct omap_dma_channel_params params)
1295 /* Check for input params */
1296 if (unlikely((chain_id < 0
1297 || chain_id >= dma_lch_count))) {
1298 printk(KERN_ERR "Invalid chain id\n");
1302 /* Check if the chain exists */
1303 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1304 printk(KERN_ERR "Chain doesn't exists\n");
1307 channels = dma_linked_lch[chain_id].linked_dmach_q;
1309 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1311 * Allowing client drivers to set common parameters now,
1312 * so that later only relevant (src_start, dest_start
1313 * and element count) can be set
1315 omap_set_dma_params(channels[i], ¶ms);
1320 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1323 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1327 * @return - Success : 0
1330 int omap_free_dma_chain(int chain_id)
1335 /* Check for input params */
1336 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1337 printk(KERN_ERR "Invalid chain id\n");
1341 /* Check if the chain exists */
1342 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1343 printk(KERN_ERR "Chain doesn't exists\n");
1347 channels = dma_linked_lch[chain_id].linked_dmach_q;
1348 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1349 dma_chan[channels[i]].next_linked_ch = -1;
1350 dma_chan[channels[i]].prev_linked_ch = -1;
1351 dma_chan[channels[i]].chain_id = -1;
1352 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1353 omap_free_dma(channels[i]);
1358 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1359 dma_linked_lch[chain_id].chain_mode = -1;
1360 dma_linked_lch[chain_id].chain_state = -1;
1364 EXPORT_SYMBOL(omap_free_dma_chain);
1367 * @brief omap_dma_chain_status - Check if the chain is in
1368 * active / inactive state.
1371 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1374 int omap_dma_chain_status(int chain_id)
1376 /* Check for input params */
1377 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1378 printk(KERN_ERR "Invalid chain id\n");
1382 /* Check if the chain exists */
1383 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1384 printk(KERN_ERR "Chain doesn't exists\n");
1387 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1388 dma_linked_lch[chain_id].q_count);
1390 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1391 return OMAP_DMA_CHAIN_INACTIVE;
1393 return OMAP_DMA_CHAIN_ACTIVE;
1395 EXPORT_SYMBOL(omap_dma_chain_status);
1398 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1399 * set the params and start the transfer.
1402 * @param src_start - buffer start address
1403 * @param dest_start - Dest address
1405 * @param frame_count
1406 * @param callbk_data - channel callback parameter data.
1408 * @return - Success : 0
1409 * Failure: -EINVAL/-EBUSY
1411 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1412 int elem_count, int frame_count, void *callbk_data)
1419 * if buffer size is less than 1 then there is
1420 * no use of starting the chain
1422 if (elem_count < 1) {
1423 printk(KERN_ERR "Invalid buffer size\n");
1427 /* Check for input params */
1428 if (unlikely((chain_id < 0
1429 || chain_id >= dma_lch_count))) {
1430 printk(KERN_ERR "Invalid chain id\n");
1434 /* Check if the chain exists */
1435 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1436 printk(KERN_ERR "Chain doesn't exist\n");
1440 /* Check if all the channels in chain are in use */
1441 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1444 /* Frame count may be negative in case of indexed transfers */
1445 channels = dma_linked_lch[chain_id].linked_dmach_q;
1447 /* Get a free channel */
1448 lch = channels[dma_linked_lch[chain_id].q_tail];
1450 /* Store the callback data */
1451 dma_chan[lch].data = callbk_data;
1453 /* Increment the q_tail */
1454 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1456 /* Set the params to the free channel */
1458 dma_write(src_start, CSSA(lch));
1459 if (dest_start != 0)
1460 dma_write(dest_start, CDSA(lch));
1462 /* Write the buffer size */
1463 dma_write(elem_count, CEN(lch));
1464 dma_write(frame_count, CFN(lch));
1467 * If the chain is dynamically linked,
1468 * then we may have to start the chain if its not active
1470 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1473 * In Dynamic chain, if the chain is not started,
1476 if (dma_linked_lch[chain_id].chain_state ==
1477 DMA_CHAIN_NOTSTARTED) {
1478 /* Enable the link in previous channel */
1479 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1481 enable_lnk(dma_chan[lch].prev_linked_ch);
1482 dma_chan[lch].state = DMA_CH_QUEUED;
1486 * Chain is already started, make sure its active,
1487 * if not then start the chain
1492 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1494 enable_lnk(dma_chan[lch].prev_linked_ch);
1495 dma_chan[lch].state = DMA_CH_QUEUED;
1497 if (0 == ((1 << 7) & dma_read(
1498 CCR(dma_chan[lch].prev_linked_ch)))) {
1499 disable_lnk(dma_chan[lch].
1501 pr_debug("\n prev ch is stopped\n");
1506 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1508 enable_lnk(dma_chan[lch].prev_linked_ch);
1509 dma_chan[lch].state = DMA_CH_QUEUED;
1512 omap_enable_channel_irq(lch);
1514 l = dma_read(CCR(lch));
1516 if ((0 == (l & (1 << 24))))
1520 if (start_dma == 1) {
1521 if (0 == (l & (1 << 7))) {
1523 dma_chan[lch].state = DMA_CH_STARTED;
1524 pr_debug("starting %d\n", lch);
1525 dma_write(l, CCR(lch));
1529 if (0 == (l & (1 << 7)))
1530 dma_write(l, CCR(lch));
1532 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1538 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1541 * @brief omap_start_dma_chain_transfers - Start the chain
1545 * @return - Success : 0
1546 * Failure : -EINVAL/-EBUSY
1548 int omap_start_dma_chain_transfers(int chain_id)
1553 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1554 printk(KERN_ERR "Invalid chain id\n");
1558 channels = dma_linked_lch[chain_id].linked_dmach_q;
1560 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1561 printk(KERN_ERR "Chain is already started\n");
1565 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1566 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1568 enable_lnk(channels[i]);
1569 omap_enable_channel_irq(channels[i]);
1572 omap_enable_channel_irq(channels[0]);
1575 l = dma_read(CCR(channels[0]));
1577 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1578 dma_chan[channels[0]].state = DMA_CH_STARTED;
1580 if ((0 == (l & (1 << 24))))
1584 dma_write(l, CCR(channels[0]));
1586 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1590 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1593 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1597 * @return - Success : 0
1600 int omap_stop_dma_chain_transfers(int chain_id)
1606 /* Check for input params */
1607 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1608 printk(KERN_ERR "Invalid chain id\n");
1612 /* Check if the chain exists */
1613 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1614 printk(KERN_ERR "Chain doesn't exists\n");
1617 channels = dma_linked_lch[chain_id].linked_dmach_q;
1621 * Special programming model needed to disable DMA before end of block
1623 sys_cf = dma_read(OCP_SYSCONFIG);
1625 /* Middle mode reg set no Standby */
1626 l &= ~((1 << 12)|(1 << 13));
1627 dma_write(l, OCP_SYSCONFIG);
1629 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1631 /* Stop the Channel transmission */
1632 l = dma_read(CCR(channels[i]));
1634 dma_write(l, CCR(channels[i]));
1636 /* Disable the link in all the channels */
1637 disable_lnk(channels[i]);
1638 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1641 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1643 /* Reset the Queue pointers */
1644 OMAP_DMA_CHAIN_QINIT(chain_id);
1646 /* Errata - put in the old value */
1647 dma_write(sys_cf, OCP_SYSCONFIG);
1651 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1653 /* Get the index of the ongoing DMA in chain */
1655 * @brief omap_get_dma_chain_index - Get the element and frame index
1656 * of the ongoing DMA in chain
1659 * @param ei - Element index
1660 * @param fi - Frame index
1662 * @return - Success : 0
1665 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1670 /* Check for input params */
1671 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1672 printk(KERN_ERR "Invalid chain id\n");
1676 /* Check if the chain exists */
1677 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1678 printk(KERN_ERR "Chain doesn't exists\n");
1684 channels = dma_linked_lch[chain_id].linked_dmach_q;
1686 /* Get the current channel */
1687 lch = channels[dma_linked_lch[chain_id].q_head];
1689 *ei = dma_read(CCEN(lch));
1690 *fi = dma_read(CCFN(lch));
1694 EXPORT_SYMBOL(omap_get_dma_chain_index);
1697 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1698 * ongoing DMA in chain
1702 * @return - Success : Destination position
1705 int omap_get_dma_chain_dst_pos(int chain_id)
1710 /* Check for input params */
1711 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1712 printk(KERN_ERR "Invalid chain id\n");
1716 /* Check if the chain exists */
1717 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1718 printk(KERN_ERR "Chain doesn't exists\n");
1722 channels = dma_linked_lch[chain_id].linked_dmach_q;
1724 /* Get the current channel */
1725 lch = channels[dma_linked_lch[chain_id].q_head];
1727 return dma_read(CDAC(lch));
1729 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1732 * @brief omap_get_dma_chain_src_pos - Get the source position
1733 * of the ongoing DMA in chain
1736 * @return - Success : Destination position
1739 int omap_get_dma_chain_src_pos(int chain_id)
1744 /* Check for input params */
1745 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1746 printk(KERN_ERR "Invalid chain id\n");
1750 /* Check if the chain exists */
1751 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1752 printk(KERN_ERR "Chain doesn't exists\n");
1756 channels = dma_linked_lch[chain_id].linked_dmach_q;
1758 /* Get the current channel */
1759 lch = channels[dma_linked_lch[chain_id].q_head];
1761 return dma_read(CSAC(lch));
1763 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1764 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1766 /*----------------------------------------------------------------------------*/
1768 #ifdef CONFIG_ARCH_OMAP1
1770 static int omap1_dma_handle_ch(int ch)
1774 if (enable_1510_mode && ch >= 6) {
1775 csr = dma_chan[ch].saved_csr;
1776 dma_chan[ch].saved_csr = 0;
1778 csr = dma_read(CSR(ch));
1779 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1780 dma_chan[ch + 6].saved_csr = csr >> 7;
1783 if ((csr & 0x3f) == 0)
1785 if (unlikely(dma_chan[ch].dev_id == -1)) {
1786 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1787 "%d (CSR %04x)\n", ch, csr);
1790 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1791 printk(KERN_WARNING "DMA timeout with device %d\n",
1792 dma_chan[ch].dev_id);
1793 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1794 printk(KERN_WARNING "DMA synchronization event drop occurred "
1795 "with device %d\n", dma_chan[ch].dev_id);
1796 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1797 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1798 if (likely(dma_chan[ch].callback != NULL))
1799 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1804 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1806 int ch = ((int) dev_id) - 1;
1810 int handled_now = 0;
1812 handled_now += omap1_dma_handle_ch(ch);
1813 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1814 handled_now += omap1_dma_handle_ch(ch + 6);
1817 handled += handled_now;
1820 return handled ? IRQ_HANDLED : IRQ_NONE;
1824 #define omap1_dma_irq_handler NULL
1827 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1829 static int omap2_dma_handle_ch(int ch)
1831 u32 status = dma_read(CSR(ch));
1834 if (printk_ratelimit())
1835 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1837 dma_write(1 << ch, IRQSTATUS_L0);
1840 if (unlikely(dma_chan[ch].dev_id == -1)) {
1841 if (printk_ratelimit())
1842 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1843 "channel %d\n", status, ch);
1846 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1848 "DMA synchronization event drop occurred with device "
1849 "%d\n", dma_chan[ch].dev_id);
1850 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1851 printk(KERN_INFO "DMA transaction error with device %d\n",
1852 dma_chan[ch].dev_id);
1853 if (cpu_class_is_omap2()) {
1854 /* Errata: sDMA Channel is not disabled
1855 * after a transaction error. So we explicitely
1856 * disable the channel
1860 ccr = dma_read(CCR(ch));
1861 ccr &= ~OMAP_DMA_CCR_EN;
1862 dma_write(ccr, CCR(ch));
1863 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1866 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1867 printk(KERN_INFO "DMA secure error with device %d\n",
1868 dma_chan[ch].dev_id);
1869 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1870 printk(KERN_INFO "DMA misaligned error with device %d\n",
1871 dma_chan[ch].dev_id);
1873 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1874 dma_write(1 << ch, IRQSTATUS_L0);
1876 /* If the ch is not chained then chain_id will be -1 */
1877 if (dma_chan[ch].chain_id != -1) {
1878 int chain_id = dma_chan[ch].chain_id;
1879 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1880 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1881 dma_chan[dma_chan[ch].next_linked_ch].state =
1883 if (dma_linked_lch[chain_id].chain_mode ==
1884 OMAP_DMA_DYNAMIC_CHAIN)
1887 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1888 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1890 status = dma_read(CSR(ch));
1893 dma_write(status, CSR(ch));
1895 if (likely(dma_chan[ch].callback != NULL))
1896 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1901 /* STATUS register count is from 1-32 while our is 0-31 */
1902 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1904 u32 val, enable_reg;
1907 val = dma_read(IRQSTATUS_L0);
1909 if (printk_ratelimit())
1910 printk(KERN_WARNING "Spurious DMA IRQ\n");
1913 enable_reg = dma_read(IRQENABLE_L0);
1914 val &= enable_reg; /* Dispatch only relevant interrupts */
1915 for (i = 0; i < dma_lch_count && val != 0; i++) {
1917 omap2_dma_handle_ch(i);
1924 static struct irqaction omap24xx_dma_irq = {
1926 .handler = omap2_dma_irq_handler,
1927 .flags = IRQF_DISABLED
1931 static struct irqaction omap24xx_dma_irq;
1934 /*----------------------------------------------------------------------------*/
1936 static struct lcd_dma_info {
1939 void (*callback)(u16 status, void *data);
1943 unsigned long addr, size;
1944 int rotate, data_type, xres, yres;
1950 int single_transfer;
1953 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1956 lcd_dma.addr = addr;
1957 lcd_dma.data_type = data_type;
1958 lcd_dma.xres = fb_xres;
1959 lcd_dma.yres = fb_yres;
1961 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1963 void omap_set_lcd_dma_src_port(int port)
1965 lcd_dma.src_port = port;
1968 void omap_set_lcd_dma_ext_controller(int external)
1970 lcd_dma.ext_ctrl = external;
1972 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1974 void omap_set_lcd_dma_single_transfer(int single)
1976 lcd_dma.single_transfer = single;
1978 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1980 void omap_set_lcd_dma_b1_rotation(int rotate)
1982 if (omap_dma_in_1510_mode()) {
1983 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1987 lcd_dma.rotate = rotate;
1989 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1991 void omap_set_lcd_dma_b1_mirror(int mirror)
1993 if (omap_dma_in_1510_mode()) {
1994 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1997 lcd_dma.mirror = mirror;
1999 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2001 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2003 if (omap_dma_in_1510_mode()) {
2004 printk(KERN_ERR "DMA virtual resulotion is not supported "
2008 lcd_dma.vxres = vxres;
2010 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2012 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2014 if (omap_dma_in_1510_mode()) {
2015 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2018 lcd_dma.xscale = xscale;
2019 lcd_dma.yscale = yscale;
2021 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2023 static void set_b1_regs(void)
2025 unsigned long top, bottom;
2028 unsigned long en, fn;
2030 unsigned long vxres;
2031 unsigned int xscale, yscale;
2033 switch (lcd_dma.data_type) {
2034 case OMAP_DMA_DATA_TYPE_S8:
2037 case OMAP_DMA_DATA_TYPE_S16:
2040 case OMAP_DMA_DATA_TYPE_S32:
2048 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2049 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2050 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2051 BUG_ON(vxres < lcd_dma.xres);
2053 #define PIXADDR(x, y) (lcd_dma.addr + \
2054 ((y) * vxres * yscale + (x) * xscale) * es)
2055 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2057 switch (lcd_dma.rotate) {
2059 if (!lcd_dma.mirror) {
2060 top = PIXADDR(0, 0);
2061 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2062 /* 1510 DMA requires the bottom address to be 2 more
2063 * than the actual last memory access location. */
2064 if (omap_dma_in_1510_mode() &&
2065 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2067 ei = PIXSTEP(0, 0, 1, 0);
2068 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2070 top = PIXADDR(lcd_dma.xres - 1, 0);
2071 bottom = PIXADDR(0, lcd_dma.yres - 1);
2072 ei = PIXSTEP(1, 0, 0, 0);
2073 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2079 if (!lcd_dma.mirror) {
2080 top = PIXADDR(0, lcd_dma.yres - 1);
2081 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2082 ei = PIXSTEP(0, 1, 0, 0);
2083 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2085 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2086 bottom = PIXADDR(0, 0);
2087 ei = PIXSTEP(0, 1, 0, 0);
2088 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2094 if (!lcd_dma.mirror) {
2095 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2096 bottom = PIXADDR(0, 0);
2097 ei = PIXSTEP(1, 0, 0, 0);
2098 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2100 top = PIXADDR(0, lcd_dma.yres - 1);
2101 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2102 ei = PIXSTEP(0, 0, 1, 0);
2103 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2109 if (!lcd_dma.mirror) {
2110 top = PIXADDR(lcd_dma.xres - 1, 0);
2111 bottom = PIXADDR(0, lcd_dma.yres - 1);
2112 ei = PIXSTEP(0, 0, 0, 1);
2113 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2115 top = PIXADDR(0, 0);
2116 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2117 ei = PIXSTEP(0, 0, 0, 1);
2118 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2125 return; /* Suppress warning about uninitialized vars */
2128 if (omap_dma_in_1510_mode()) {
2129 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2130 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2131 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2132 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2138 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2139 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2140 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2141 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2143 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2144 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2146 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2148 w |= lcd_dma.data_type;
2149 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2151 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2152 /* Always set the source port as SDRAM for now*/
2154 if (lcd_dma.callback != NULL)
2155 w |= 1 << 1; /* Block interrupt enable */
2158 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2160 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2161 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2164 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2165 /* Set the double-indexed addressing mode */
2167 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2169 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2170 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2171 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2174 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2178 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2179 if (unlikely(!(w & (1 << 3)))) {
2180 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2185 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2187 if (lcd_dma.callback != NULL)
2188 lcd_dma.callback(w, lcd_dma.cb_data);
2193 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2196 spin_lock_irq(&lcd_dma.lock);
2197 if (lcd_dma.reserved) {
2198 spin_unlock_irq(&lcd_dma.lock);
2199 printk(KERN_ERR "LCD DMA channel already reserved\n");
2203 lcd_dma.reserved = 1;
2204 spin_unlock_irq(&lcd_dma.lock);
2205 lcd_dma.callback = callback;
2206 lcd_dma.cb_data = data;
2208 lcd_dma.single_transfer = 0;
2214 lcd_dma.ext_ctrl = 0;
2215 lcd_dma.src_port = 0;
2219 EXPORT_SYMBOL(omap_request_lcd_dma);
2221 void omap_free_lcd_dma(void)
2223 spin_lock(&lcd_dma.lock);
2224 if (!lcd_dma.reserved) {
2225 spin_unlock(&lcd_dma.lock);
2226 printk(KERN_ERR "LCD DMA is not reserved\n");
2230 if (!enable_1510_mode)
2231 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2232 OMAP1610_DMA_LCD_CCR);
2233 lcd_dma.reserved = 0;
2234 spin_unlock(&lcd_dma.lock);
2236 EXPORT_SYMBOL(omap_free_lcd_dma);
2238 void omap_enable_lcd_dma(void)
2243 * Set the Enable bit only if an external controller is
2244 * connected. Otherwise the OMAP internal controller will
2245 * start the transfer when it gets enabled.
2247 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2250 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2252 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2256 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2258 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2260 EXPORT_SYMBOL(omap_enable_lcd_dma);
2262 void omap_setup_lcd_dma(void)
2264 BUG_ON(lcd_dma.active);
2265 if (!enable_1510_mode) {
2266 /* Set some reasonable defaults */
2267 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2268 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2269 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2272 if (!enable_1510_mode) {
2275 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2277 * If DMA was already active set the end_prog bit to have
2278 * the programmed register set loaded into the active
2281 w |= 1 << 11; /* End_prog */
2282 if (!lcd_dma.single_transfer)
2283 w |= (3 << 8); /* Auto_init, repeat */
2284 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2287 EXPORT_SYMBOL(omap_setup_lcd_dma);
2289 void omap_stop_lcd_dma(void)
2294 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2297 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2299 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2301 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2303 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2305 EXPORT_SYMBOL(omap_stop_lcd_dma);
2307 /*----------------------------------------------------------------------------*/
2309 static int __init omap_init_dma(void)
2313 if (cpu_class_is_omap1()) {
2314 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2315 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2316 } else if (cpu_is_omap24xx()) {
2317 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2318 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2319 } else if (cpu_is_omap34xx()) {
2320 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2321 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2323 pr_err("DMA init failed for unsupported omap\n");
2327 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2328 && (omap_dma_reserve_channels <= dma_lch_count))
2329 dma_lch_count = omap_dma_reserve_channels;
2331 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2336 if (cpu_class_is_omap2()) {
2337 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2338 dma_lch_count, GFP_KERNEL);
2339 if (!dma_linked_lch) {
2345 if (cpu_is_omap15xx()) {
2346 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2348 enable_1510_mode = 1;
2349 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2350 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2352 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2353 (dma_read(CAPS_0_U) << 16) |
2355 (dma_read(CAPS_1_U) << 16) |
2357 dma_read(CAPS_2), dma_read(CAPS_3),
2359 if (!enable_1510_mode) {
2362 /* Disable OMAP 3.0/3.1 compatibility mode. */
2366 dma_chan_count = 16;
2369 if (cpu_is_omap16xx()) {
2372 /* this would prevent OMAP sleep */
2373 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2375 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2377 } else if (cpu_class_is_omap2()) {
2378 u8 revision = dma_read(REVISION) & 0xff;
2379 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2380 revision >> 4, revision & 0xf);
2381 dma_chan_count = dma_lch_count;
2387 spin_lock_init(&lcd_dma.lock);
2388 spin_lock_init(&dma_chan_lock);
2390 for (ch = 0; ch < dma_chan_count; ch++) {
2392 dma_chan[ch].dev_id = -1;
2393 dma_chan[ch].next_lch = -1;
2395 if (ch >= 6 && enable_1510_mode)
2398 if (cpu_class_is_omap1()) {
2400 * request_irq() doesn't like dev_id (ie. ch) being
2401 * zero, so we have to kludge around this.
2403 r = request_irq(omap1_dma_irq[ch],
2404 omap1_dma_irq_handler, 0, "DMA",
2409 printk(KERN_ERR "unable to request IRQ %d "
2410 "for DMA (error %d)\n",
2411 omap1_dma_irq[ch], r);
2412 for (i = 0; i < ch; i++)
2413 free_irq(omap1_dma_irq[i],
2420 if (cpu_is_omap2430() || cpu_is_omap34xx())
2421 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2422 DMA_DEFAULT_FIFO_DEPTH, 0);
2424 if (cpu_class_is_omap2())
2425 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2427 /* Enable smartidle idlemodes and autoidle */
2428 if (cpu_is_omap34xx()) {
2429 u32 v = dma_read(OCP_SYSCONFIG);
2430 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2431 DMA_SYSCONFIG_SIDLEMODE_MASK |
2432 DMA_SYSCONFIG_AUTOIDLE);
2433 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2434 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2435 DMA_SYSCONFIG_AUTOIDLE);
2436 dma_write(v , OCP_SYSCONFIG);
2440 /* FIXME: Update LCD DMA to work on 24xx */
2441 if (cpu_class_is_omap1()) {
2442 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2447 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2449 for (i = 0; i < dma_chan_count; i++)
2450 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2458 arch_initcall(omap_init_dma);
2461 * Reserve the omap SDMA channels using cmdline bootarg
2462 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2464 static int __init omap_dma_cmdline_reserve_ch(char *str)
2466 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2467 omap_dma_reserve_channels = 0;
2471 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);