arch/arm/plat-omap/clock.c

   1 /*
   2  *  linux/arch/arm/plat-omap/clock.c
   3  *
   4  *  Copyright (C) 2004 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/list.h>
  14 #include <linux/errno.h>
  15 #include <linux/err.h>
  16
  17 #include <asm/io.h>
  18 #include <asm/semaphore.h>
  19 #include <asm/hardware/clock.h>
  20 #include <asm/arch/board.h>
  21 #include <asm/arch/usb.h>
  22
  23 #include "clock.h"
  24 #include "sram.h"
  25
  26 static LIST_HEAD(clocks);
  27 static DECLARE_MUTEX(clocks_sem);
  28 static DEFINE_SPINLOCK(clockfw_lock);
  29 static void propagate_rate(struct clk *  clk);
  30 /* UART clock function */
  31 static int set_uart_rate(struct clk * clk, unsigned long rate);
  32 /* External clock (MCLK & BCLK) functions */
  33 static int set_ext_clk_rate(struct clk *  clk, unsigned long rate);
  34 static long round_ext_clk_rate(struct clk *  clk, unsigned long rate);
  35 static void init_ext_clk(struct clk *  clk);
  36 /* MPU virtual clock functions */
  37 static int select_table_rate(struct clk *  clk, unsigned long rate);
  38 static long round_to_table_rate(struct clk *  clk, unsigned long rate);
  39 void clk_setdpll(__u16, __u16);
  40
  41 static struct mpu_rate rate_table[] = {
  42         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
  43          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
  44          */
  45 #if defined(CONFIG_OMAP_ARM_216MHZ)
  46         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
  47 #endif
  48 #if defined(CONFIG_OMAP_ARM_195MHZ)
  49         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
  50 #endif
  51 #if defined(CONFIG_OMAP_ARM_192MHZ)
  52         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
  53         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
  54         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
  55         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
  56         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
  57 #endif
  58 #if defined(CONFIG_OMAP_ARM_182MHZ)
  59         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
  60 #endif
  61 #if defined(CONFIG_OMAP_ARM_168MHZ)
  62         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
  63 #endif
  64 #if defined(CONFIG_OMAP_ARM_150MHZ)
  65         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
  66 #endif
  67 #if defined(CONFIG_OMAP_ARM_120MHZ)
  68         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
  69 #endif
  70 #if defined(CONFIG_OMAP_ARM_96MHZ)
  71         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
  72 #endif
  73 #if defined(CONFIG_OMAP_ARM_60MHZ)
  74         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
  75 #endif
  76 #if defined(CONFIG_OMAP_ARM_30MHZ)
  77         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
  78 #endif
  79         { 0, 0, 0, 0, 0 },
  80 };
  81
  82
  83 static void ckctl_recalc(struct clk *  clk);
  84 int __clk_enable(struct clk *clk);
  85 void __clk_disable(struct clk *clk);
  86 void __clk_unuse(struct clk *clk);
  87 int __clk_use(struct clk *clk);
  88
  89
  90 static void followparent_recalc(struct clk *  clk)
  91 {
  92         clk->rate = clk->parent->rate;
  93 }
  94
  95
  96 static void watchdog_recalc(struct clk *  clk)
  97 {
  98         clk->rate = clk->parent->rate / 14;
  99 }
 100
 101 static void uart_recalc(struct clk * clk)
 102 {
 103         unsigned int val = omap_readl(clk->enable_reg);
 104         if (val & clk->enable_bit)
 105                 clk->rate = 48000000;
 106         else
 107                 clk->rate = 12000000;
 108 }
 109
 110 static struct clk ck_ref = {
 111         .name           = "ck_ref",
 112         .rate           = 12000000,
 113         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 114                           ALWAYS_ENABLED,
 115 };
 116
 117 static struct clk ck_dpll1 = {
 118         .name           = "ck_dpll1",
 119         .parent         = &ck_ref,
 120         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 121                           RATE_PROPAGATES | ALWAYS_ENABLED,
 122 };
 123
 124 static struct clk ck_dpll1out = {
 125         .name           = "ck_dpll1out",
 126         .parent         = &ck_dpll1,
 127         .flags          = CLOCK_IN_OMAP16XX,
 128         .enable_reg     = ARM_IDLECT2,
 129         .enable_bit     = EN_CKOUT_ARM,
 130         .recalc         = &followparent_recalc,
 131 };
 132
 133 static struct clk arm_ck = {
 134         .name           = "arm_ck",
 135         .parent         = &ck_dpll1,
 136         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 137                           RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
 138         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 139         .recalc         = &ckctl_recalc,
 140 };
 141
 142 static struct clk armper_ck = {
 143         .name           = "armper_ck",
 144         .parent         = &ck_dpll1,
 145         .flags          = CLOCK_IN_OMAP730 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 146                           RATE_CKCTL,
 147         .enable_reg     = ARM_IDLECT2,
 148         .enable_bit     = EN_PERCK,
 149         .rate_offset    = CKCTL_PERDIV_OFFSET,
 150         .recalc         = &ckctl_recalc,
 151 };
 152
 153 static struct clk arm_gpio_ck = {
 154         .name           = "arm_gpio_ck",
 155         .parent         = &ck_dpll1,
 156         .flags          = CLOCK_IN_OMAP1510,
 157         .enable_reg     = ARM_IDLECT2,
 158         .enable_bit     = EN_GPIOCK,
 159         .recalc         = &followparent_recalc,
 160 };
 161
 162 static struct clk armxor_ck = {
 163         .name           = "armxor_ck",
 164         .parent         = &ck_ref,
 165         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 166         .enable_reg     = ARM_IDLECT2,
 167         .enable_bit     = EN_XORPCK,
 168         .recalc         = &followparent_recalc,
 169 };
 170
 171 static struct clk armtim_ck = {
 172         .name           = "armtim_ck",
 173         .parent         = &ck_ref,
 174         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 175         .enable_reg     = ARM_IDLECT2,
 176         .enable_bit     = EN_TIMCK,
 177         .recalc         = &followparent_recalc,
 178 };
 179
 180 static struct clk armwdt_ck = {
 181         .name           = "armwdt_ck",
 182         .parent         = &ck_ref,
 183         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 184         .enable_reg     = ARM_IDLECT2,
 185         .enable_bit     = EN_WDTCK,
 186         .recalc         = &watchdog_recalc,
 187 };
 188
 189 static struct clk arminth_ck16xx = {
 190         .name           = "arminth_ck",
 191         .parent         = &arm_ck,
 192         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 193         .recalc         = &followparent_recalc,
 194         /* Note: On 16xx the frequency can be divided by 2 by programming
 195          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 196          *
 197          * 1510 version is in TC clocks.
 198          */
 199 };
 200
 201 static struct clk dsp_ck = {
 202         .name           = "dsp_ck",
 203         .parent         = &ck_dpll1,
 204         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 205                           RATE_CKCTL,
 206         .enable_reg     = ARM_CKCTL,
 207         .enable_bit     = EN_DSPCK,
 208         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 209         .recalc         = &ckctl_recalc,
 210 };
 211
 212 static struct clk dspmmu_ck = {
 213         .name           = "dspmmu_ck",
 214         .parent         = &ck_dpll1,
 215         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 216                           RATE_CKCTL | ALWAYS_ENABLED,
 217         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 218         .recalc         = &ckctl_recalc,
 219 };
 220
 221 static struct clk dspper_ck = {
 222         .name           = "dspper_ck",
 223         .parent         = &ck_dpll1,
 224         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 225                           RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
 226         .enable_reg     = DSP_IDLECT2,
 227         .enable_bit     = EN_PERCK,
 228         .rate_offset    = CKCTL_PERDIV_OFFSET,
 229         .recalc         = &followparent_recalc,
 230         //.recalc               = &ckctl_recalc,
 231 };
 232
 233 static struct clk dspxor_ck = {
 234         .name           = "dspxor_ck",
 235         .parent         = &ck_ref,
 236         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 237                           DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
 238         .enable_reg     = DSP_IDLECT2,
 239         .enable_bit     = EN_XORPCK,
 240         .recalc         = &followparent_recalc,
 241 };
 242
 243 static struct clk dsptim_ck = {
 244         .name           = "dsptim_ck",
 245         .parent         = &ck_ref,
 246         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 247                           DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
 248         .enable_reg     = DSP_IDLECT2,
 249         .enable_bit     = EN_DSPTIMCK,
 250         .recalc         = &followparent_recalc,
 251 };
 252
 253 static struct clk tc_ck = {
 254         .name           = "tc_ck",
 255         .parent         = &ck_dpll1,
 256         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
 257                           RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
 258         .rate_offset    = CKCTL_TCDIV_OFFSET,
 259         .recalc         = &ckctl_recalc,
 260 };
 261
 262 static struct clk arminth_ck1510 = {
 263         .name           = "arminth_ck",
 264         .parent         = &tc_ck,
 265         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
 266         .recalc         = &followparent_recalc,
 267         /* Note: On 1510 the frequency follows TC_CK
 268          *
 269          * 16xx version is in MPU clocks.
 270          */
 271 };
 272
 273 static struct clk tipb_ck = {
 274         .name           = "tibp_ck",
 275         .parent         = &tc_ck,
 276         .flags          = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
 277         .recalc         = &followparent_recalc,
 278 };
 279
 280 static struct clk l3_ocpi_ck = {
 281         .name           = "l3_ocpi_ck",
 282         .parent         = &tc_ck,
 283         .flags          = CLOCK_IN_OMAP16XX,
 284         .enable_reg     = ARM_IDLECT3,
 285         .enable_bit     = EN_OCPI_CK,
 286         .recalc         = &followparent_recalc,
 287 };
 288
 289 static struct clk tc1_ck = {
 290         .name           = "tc1_ck",
 291         .parent         = &tc_ck,
 292         .flags          = CLOCK_IN_OMAP16XX,
 293         .enable_reg     = ARM_IDLECT3,
 294         .enable_bit     = EN_TC1_CK,
 295         .recalc         = &followparent_recalc,
 296 };
 297
 298 static struct clk tc2_ck = {
 299         .name           = "tc2_ck",
 300         .parent         = &tc_ck,
 301         .flags          = CLOCK_IN_OMAP16XX,
 302         .enable_reg     = ARM_IDLECT3,
 303         .enable_bit     = EN_TC2_CK,
 304         .recalc         = &followparent_recalc,
 305 };
 306
 307 static struct clk dma_ck = {
 308         .name           = "dma_ck",
 309         .parent         = &tc_ck,
 310         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 311                           ALWAYS_ENABLED,
 312         .recalc         = &followparent_recalc,
 313 };
 314
 315 static struct clk dma_lcdfree_ck = {
 316         .name           = "dma_lcdfree_ck",
 317         .parent         = &tc_ck,
 318         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 319         .recalc         = &followparent_recalc,
 320 };
 321
 322 static struct clk api_ck = {
 323         .name           = "api_ck",
 324         .parent         = &tc_ck,
 325         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 326         .enable_reg     = ARM_IDLECT2,
 327         .enable_bit     = EN_APICK,
 328         .recalc         = &followparent_recalc,
 329 };
 330
 331 static struct clk lb_ck = {
 332         .name           = "lb_ck",
 333         .parent         = &tc_ck,
 334         .flags          = CLOCK_IN_OMAP1510,
 335         .enable_reg     = ARM_IDLECT2,
 336         .enable_bit     = EN_LBCK,
 337         .recalc         = &followparent_recalc,
 338 };
 339
 340 static struct clk rhea1_ck = {
 341         .name           = "rhea1_ck",
 342         .parent         = &tc_ck,
 343         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 344         .recalc         = &followparent_recalc,
 345 };
 346
 347 static struct clk rhea2_ck = {
 348         .name           = "rhea2_ck",
 349         .parent         = &tc_ck,
 350         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 351         .recalc         = &followparent_recalc,
 352 };
 353
 354 static struct clk lcd_ck = {
 355         .name           = "lcd_ck",
 356         .parent         = &ck_dpll1,
 357         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
 358                           RATE_CKCTL,
 359         .enable_reg     = ARM_IDLECT2,
 360         .enable_bit     = EN_LCDCK,
 361         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 362         .recalc         = &ckctl_recalc,
 363 };
 364
 365 static struct clk uart1_1510 = {
 366         .name           = "uart1_ck",
 367         /* Direct from ULPD, no parent */
 368         .rate           = 12000000,
 369         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
 370         .enable_reg     = MOD_CONF_CTRL_0,
 371         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 372         .set_rate       = &set_uart_rate,
 373         .recalc         = &uart_recalc,
 374 };
 375
 376 static struct clk uart1_16xx = {
 377         .name           = "uart1_ck",
 378         /* Direct from ULPD, no parent */
 379         .rate           = 48000000,
 380         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
 381         .enable_reg     = MOD_CONF_CTRL_0,
 382         .enable_bit     = 29,
 383 };
 384
 385 static struct clk uart2_ck = {
 386         .name           = "uart2_ck",
 387         /* Direct from ULPD, no parent */
 388         .rate           = 12000000,
 389         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT,
 390         .enable_reg     = MOD_CONF_CTRL_0,
 391         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 392         .set_rate       = &set_uart_rate,
 393         .recalc         = &uart_recalc,
 394 };
 395
 396 static struct clk uart3_1510 = {
 397         .name           = "uart3_ck",
 398         /* Direct from ULPD, no parent */
 399         .rate           = 12000000,
 400         .flags          = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
 401         .enable_reg     = MOD_CONF_CTRL_0,
 402         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 403         .set_rate       = &set_uart_rate,
 404         .recalc         = &uart_recalc,
 405 };
 406
 407 static struct clk uart3_16xx = {
 408         .name           = "uart3_ck",
 409         /* Direct from ULPD, no parent */
 410         .rate           = 48000000,
 411         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
 412         .enable_reg     = MOD_CONF_CTRL_0,
 413         .enable_bit     = 31,
 414 };
 415
 416 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 417         .name           = "usb_clko",
 418         /* Direct from ULPD, no parent */
 419         .rate           = 6000000,
 420         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 421                           RATE_FIXED | ENABLE_REG_32BIT,
 422         .enable_reg     = ULPD_CLOCK_CTRL,
 423         .enable_bit     = USB_MCLK_EN_BIT,
 424 };
 425
 426 static struct clk usb_hhc_ck1510 = {
 427         .name           = "usb_hhc_ck",
 428         /* Direct from ULPD, no parent */
 429         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 430         .flags          = CLOCK_IN_OMAP1510 |
 431                           RATE_FIXED | ENABLE_REG_32BIT,
 432         .enable_reg     = MOD_CONF_CTRL_0,
 433         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 434 };
 435
 436 static struct clk usb_hhc_ck16xx = {
 437         .name           = "usb_hhc_ck",
 438         /* Direct from ULPD, no parent */
 439         .rate           = 48000000,
 440         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 441         .flags          = CLOCK_IN_OMAP16XX |
 442                           RATE_FIXED | ENABLE_REG_32BIT,
 443         .enable_reg     = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
 444         .enable_bit     = 8 /* UHOST_EN */,
 445 };
 446
 447 static struct clk mclk_1510 = {
 448         .name           = "mclk",
 449         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 450         .rate           = 12000000,
 451         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
 452 };
 453
 454 static struct clk mclk_16xx = {
 455         .name           = "mclk",
 456         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 457         .flags          = CLOCK_IN_OMAP16XX,
 458         .enable_reg     = COM_CLK_DIV_CTRL_SEL,
 459         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 460         .set_rate       = &set_ext_clk_rate,
 461         .round_rate     = &round_ext_clk_rate,
 462         .init           = &init_ext_clk,
 463 };
 464
 465 static struct clk bclk_1510 = {
 466         .name           = "bclk",
 467         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 468         .rate           = 12000000,
 469         .flags          = CLOCK_IN_OMAP1510 | RATE_FIXED,
 470 };
 471
 472 static struct clk bclk_16xx = {
 473         .name           = "bclk",
 474         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 475         .flags          = CLOCK_IN_OMAP16XX,
 476         .enable_reg     = SWD_CLK_DIV_CTRL_SEL,
 477         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 478         .set_rate       = &set_ext_clk_rate,
 479         .round_rate     = &round_ext_clk_rate,
 480         .init           = &init_ext_clk,
 481 };
 482
 483 static struct clk mmc1_ck = {
 484         .name           = "mmc1_ck",
 485         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 486         .parent         = &armper_ck,
 487         .rate           = 48000000,
 488         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 489                           RATE_FIXED | ENABLE_REG_32BIT,
 490         .enable_reg     = MOD_CONF_CTRL_0,
 491         .enable_bit     = 23,
 492 };
 493
 494 static struct clk mmc2_ck = {
 495         .name           = "mmc2_ck",
 496         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 497         .parent         = &armper_ck,
 498         .rate           = 48000000,
 499         .flags          = CLOCK_IN_OMAP16XX |
 500                           RATE_FIXED | ENABLE_REG_32BIT,
 501         .enable_reg     = MOD_CONF_CTRL_0,
 502         .enable_bit     = 20,
 503 };
 504
 505 static struct clk virtual_ck_mpu = {
 506         .name           = "mpu",
 507         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 508                           VIRTUAL_CLOCK | ALWAYS_ENABLED,
 509         .parent         = &arm_ck, /* Is smarter alias for */
 510         .recalc         = &followparent_recalc,
 511         .set_rate       = &select_table_rate,
 512         .round_rate     = &round_to_table_rate,
 513 };
 514
 515
 516 static struct clk *  onchip_clks[] = {
 517         /* non-ULPD clocks */
 518         &ck_ref,
 519         &ck_dpll1,
 520         /* CK_GEN1 clocks */
 521         &ck_dpll1out,
 522         &arm_ck,
 523         &armper_ck,
 524         &arm_gpio_ck,
 525         &armxor_ck,
 526         &armtim_ck,
 527         &armwdt_ck,
 528         &arminth_ck1510,  &arminth_ck16xx,
 529         /* CK_GEN2 clocks */
 530         &dsp_ck,
 531         &dspmmu_ck,
 532         &dspper_ck,
 533         &dspxor_ck,
 534         &dsptim_ck,
 535         /* CK_GEN3 clocks */
 536         &tc_ck,
 537         &tipb_ck,
 538         &l3_ocpi_ck,
 539         &tc1_ck,
 540         &tc2_ck,
 541         &dma_ck,
 542         &dma_lcdfree_ck,
 543         &api_ck,
 544         &lb_ck,
 545         &rhea1_ck,
 546         &rhea2_ck,
 547         &lcd_ck,
 548         /* ULPD clocks */
 549         &uart1_1510,
 550         &uart1_16xx,
 551         &uart2_ck,
 552         &uart3_1510,
 553         &uart3_16xx,
 554         &usb_clko,
 555         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 556         &mclk_1510,  &mclk_16xx,
 557         &bclk_1510,  &bclk_16xx,
 558         &mmc1_ck,
 559         &mmc2_ck,
 560         /* Virtual clocks */
 561         &virtual_ck_mpu,
 562 };
 563
 564 struct clk *clk_get(struct device *dev, const char *id)
 565 {
 566         struct clk *p, *clk = ERR_PTR(-ENOENT);
 567
 568         down(&clocks_sem);
 569         list_for_each_entry(p, &clocks, node) {
 570                 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
 571                         clk = p;
 572                         break;
 573                 }
 574         }
 575         up(&clocks_sem);
 576
 577         return clk;
 578 }
 579 EXPORT_SYMBOL(clk_get);
 580
 581
 582 void clk_put(struct clk *clk)
 583 {
 584         if (clk && !IS_ERR(clk))
 585                 module_put(clk->owner);
 586 }
 587 EXPORT_SYMBOL(clk_put);
 588
 589
 590 int __clk_enable(struct clk *clk)
 591 {
 592         __u16 regval16;
 593         __u32 regval32;
 594
 595         if (clk->flags & ALWAYS_ENABLED)
 596                 return 0;
 597
 598         if (unlikely(clk->enable_reg == 0)) {
 599                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 600                        clk->name);
 601                 return 0;
 602         }
 603
 604         if (clk->flags & DSP_DOMAIN_CLOCK) {
 605                 __clk_use(&api_ck);
 606         }
 607
 608         if (clk->flags & ENABLE_REG_32BIT) {
 609                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 610                         regval32 = __raw_readl(clk->enable_reg);
 611                         regval32 |= (1 << clk->enable_bit);
 612                         __raw_writel(regval32, clk->enable_reg);
 613                 } else {
 614                         regval32 = omap_readl(clk->enable_reg);
 615                         regval32 |= (1 << clk->enable_bit);
 616                         omap_writel(regval32, clk->enable_reg);
 617                 }
 618         } else {
 619                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 620                         regval16 = __raw_readw(clk->enable_reg);
 621                         regval16 |= (1 << clk->enable_bit);
 622                         __raw_writew(regval16, clk->enable_reg);
 623                 } else {
 624                         regval16 = omap_readw(clk->enable_reg);
 625                         regval16 |= (1 << clk->enable_bit);
 626                         omap_writew(regval16, clk->enable_reg);
 627                 }
 628         }
 629
 630         if (clk->flags & DSP_DOMAIN_CLOCK) {
 631                 __clk_unuse(&api_ck);
 632         }
 633
 634         return 0;
 635 }
 636
 637
 638 void __clk_disable(struct clk *clk)
 639 {
 640         __u16 regval16;
 641         __u32 regval32;
 642
 643         if (clk->enable_reg == 0)
 644                 return;
 645
 646         if (clk->flags & DSP_DOMAIN_CLOCK) {
 647                 __clk_use(&api_ck);
 648         }
 649
 650         if (clk->flags & ENABLE_REG_32BIT) {
 651                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 652                         regval32 = __raw_readl(clk->enable_reg);
 653                         regval32 &= ~(1 << clk->enable_bit);
 654                         __raw_writel(regval32, clk->enable_reg);
 655                 } else {
 656                         regval32 = omap_readl(clk->enable_reg);
 657                         regval32 &= ~(1 << clk->enable_bit);
 658                         omap_writel(regval32, clk->enable_reg);
 659                 }
 660         } else {
 661                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 662                         regval16 = __raw_readw(clk->enable_reg);
 663                         regval16 &= ~(1 << clk->enable_bit);
 664                         __raw_writew(regval16, clk->enable_reg);
 665                 } else {
 666                         regval16 = omap_readw(clk->enable_reg);
 667                         regval16 &= ~(1 << clk->enable_bit);
 668                         omap_writew(regval16, clk->enable_reg);
 669                 }
 670         }
 671
 672         if (clk->flags & DSP_DOMAIN_CLOCK) {
 673                 __clk_unuse(&api_ck);
 674         }
 675 }
 676
 677
 678 void __clk_unuse(struct clk *clk)
 679 {
 680         if (clk->usecount > 0 && !(--clk->usecount)) {
 681                 __clk_disable(clk);
 682                 if (likely(clk->parent))
 683                         __clk_unuse(clk->parent);
 684         }
 685 }
 686
 687
 688 int __clk_use(struct clk *clk)
 689 {
 690         int ret = 0;
 691         if (clk->usecount++ == 0) {
 692                 if (likely(clk->parent))
 693                         ret = __clk_use(clk->parent);
 694
 695                 if (unlikely(ret != 0)) {
 696                         clk->usecount--;
 697                         return ret;
 698                 }
 699
 700                 ret = __clk_enable(clk);
 701
 702                 if (unlikely(ret != 0) && clk->parent) {
 703                         __clk_unuse(clk->parent);
 704                         clk->usecount--;
 705                 }
 706         }
 707
 708         return ret;
 709 }
 710
 711
 712 int clk_enable(struct clk *clk)
 713 {
 714         unsigned long flags;
 715         int ret;
 716
 717         spin_lock_irqsave(&clockfw_lock, flags);
 718         ret = __clk_enable(clk);
 719         spin_unlock_irqrestore(&clockfw_lock, flags);
 720         return ret;
 721 }
 722 EXPORT_SYMBOL(clk_enable);
 723
 724
 725 void clk_disable(struct clk *clk)
 726 {
 727         unsigned long flags;
 728
 729         spin_lock_irqsave(&clockfw_lock, flags);
 730         __clk_disable(clk);
 731         spin_unlock_irqrestore(&clockfw_lock, flags);
 732 }
 733 EXPORT_SYMBOL(clk_disable);
 734
 735
 736 int clk_use(struct clk *clk)
 737 {
 738         unsigned long flags;
 739         int ret = 0;
 740
 741         spin_lock_irqsave(&clockfw_lock, flags);
 742         ret = __clk_use(clk);
 743         spin_unlock_irqrestore(&clockfw_lock, flags);
 744         return ret;
 745 }
 746 EXPORT_SYMBOL(clk_use);
 747
 748
 749 void clk_unuse(struct clk *clk)
 750 {
 751         unsigned long flags;
 752
 753         spin_lock_irqsave(&clockfw_lock, flags);
 754         __clk_unuse(clk);
 755         spin_unlock_irqrestore(&clockfw_lock, flags);
 756 }
 757 EXPORT_SYMBOL(clk_unuse);
 758
 759
 760 int clk_get_usecount(struct clk *clk)
 761 {
 762         return clk->usecount;
 763 }
 764 EXPORT_SYMBOL(clk_get_usecount);
 765
 766
 767 unsigned long clk_get_rate(struct clk *clk)
 768 {
 769         return clk->rate;
 770 }
 771 EXPORT_SYMBOL(clk_get_rate);
 772
 773
 774 static __u16 verify_ckctl_value(__u16 newval)
 775 {
 776         /* This function checks for following limitations set
 777          * by the hardware (all conditions must be true):
 778          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 779          * ARM_CK >= TC_CK
 780          * DSP_CK >= TC_CK
 781          * DSPMMU_CK >= TC_CK
 782          *
 783          * In addition following rules are enforced:
 784          * LCD_CK <= TC_CK
 785          * ARMPER_CK <= TC_CK
 786          *
 787          * However, maximum frequencies are not checked for!
 788          */
 789         __u8 per_exp;
 790         __u8 lcd_exp;
 791         __u8 arm_exp;
 792         __u8 dsp_exp;
 793         __u8 tc_exp;
 794         __u8 dspmmu_exp;
 795
 796         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 797         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 798         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 799         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 800         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 801         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 802
 803         if (dspmmu_exp < dsp_exp)
 804                 dspmmu_exp = dsp_exp;
 805         if (dspmmu_exp > dsp_exp+1)
 806                 dspmmu_exp = dsp_exp+1;
 807         if (tc_exp < arm_exp)
 808                 tc_exp = arm_exp;
 809         if (tc_exp < dspmmu_exp)
 810                 tc_exp = dspmmu_exp;
 811         if (tc_exp > lcd_exp)
 812                 lcd_exp = tc_exp;
 813         if (tc_exp > per_exp)
 814                 per_exp = tc_exp;
 815
 816         newval &= 0xf000;
 817         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 818         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 819         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 820         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 821         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 822         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 823
 824         return newval;
 825 }
 826
 827
 828 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 829 {
 830         /* Note: If target frequency is too low, this function will return 4,
 831          * which is invalid value. Caller must check for this value and act
 832          * accordingly.
 833          *
 834          * Note: This function does not check for following limitations set
 835          * by the hardware (all conditions must be true):
 836          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 837          * ARM_CK >= TC_CK
 838          * DSP_CK >= TC_CK
 839          * DSPMMU_CK >= TC_CK
 840          */
 841         unsigned long realrate;
 842         struct clk *  parent;
 843         unsigned  dsor_exp;
 844
 845         if (unlikely(!(clk->flags & RATE_CKCTL)))
 846                 return -EINVAL;
 847
 848         parent = clk->parent;
 849         if (unlikely(parent == 0))
 850                 return -EIO;
 851
 852         realrate = parent->rate;
 853         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 854                 if (realrate <= rate)
 855                         break;
 856
 857                 realrate /= 2;
 858         }
 859
 860         return dsor_exp;
 861 }
 862
 863
 864 static void ckctl_recalc(struct clk *  clk)
 865 {
 866         int dsor;
 867
 868         /* Calculate divisor encoded as 2-bit exponent */
 869         if (clk->flags & DSP_DOMAIN_CLOCK) {
 870                 /* The clock control bits are in DSP domain,
 871                  * so api_ck is needed for access.
 872                  * Note that DSP_CKCTL virt addr = phys addr, so
 873                  * we must use __raw_readw() instead of omap_readw().
 874                  */
 875                 __clk_use(&api_ck);
 876                 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 877                 __clk_unuse(&api_ck);
 878         } else {
 879                 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 880         }
 881         if (unlikely(clk->rate == clk->parent->rate / dsor))
 882                 return; /* No change, quick exit */
 883         clk->rate = clk->parent->rate / dsor;
 884
 885         if (unlikely(clk->flags & RATE_PROPAGATES))
 886                 propagate_rate(clk);
 887 }
 888
 889
 890 long clk_round_rate(struct clk *clk, unsigned long rate)
 891 {
 892         int dsor_exp;
 893
 894         if (clk->flags & RATE_FIXED)
 895                 return clk->rate;
 896
 897         if (clk->flags & RATE_CKCTL) {
 898                 dsor_exp = calc_dsor_exp(clk, rate);
 899                 if (dsor_exp < 0)
 900                         return dsor_exp;
 901                 if (dsor_exp > 3)
 902                         dsor_exp = 3;
 903                 return clk->parent->rate / (1 << dsor_exp);
 904         }
 905
 906         if(clk->round_rate != 0)
 907                 return clk->round_rate(clk, rate);
 908
 909         return clk->rate;
 910 }
 911 EXPORT_SYMBOL(clk_round_rate);
 912
 913
 914 static void propagate_rate(struct clk *  clk)
 915 {
 916         struct clk **  clkp;
 917
 918         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
 919                 if (likely((*clkp)->parent != clk)) continue;
 920                 if (likely((*clkp)->recalc))
 921                         (*clkp)->recalc(*clkp);
 922         }
 923 }
 924
 925
 926 static int select_table_rate(struct clk *  clk, unsigned long rate)
 927 {
 928         /* Find the highest supported frequency <= rate and switch to it */
 929         struct mpu_rate *  ptr;
 930
 931         if (clk != &virtual_ck_mpu)
 932                 return -EINVAL;
 933
 934         for (ptr = rate_table; ptr->rate; ptr++) {
 935                 if (ptr->xtal != ck_ref.rate)
 936                         continue;
 937
 938                 /* DPLL1 cannot be reprogrammed without risking system crash */
 939                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 940                         continue;
 941
 942                 /* Can check only after xtal frequency check */
 943                 if (ptr->rate <= rate)
 944                         break;
 945         }
 946
 947         if (!ptr->rate)
 948                 return -EINVAL;
 949
 950         /*
 951          * In most cases we should not need to reprogram DPLL.
 952          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 953          */
 954         omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 955
 956         ck_dpll1.rate = ptr->pll_rate;
 957         propagate_rate(&ck_dpll1);
 958         return 0;
 959 }
 960
 961
 962 static long round_to_table_rate(struct clk *  clk, unsigned long rate)
 963 {
 964         /* Find the highest supported frequency <= rate */
 965         struct mpu_rate *  ptr;
 966         long  highest_rate;
 967
 968         if (clk != &virtual_ck_mpu)
 969                 return -EINVAL;
 970
 971         highest_rate = -EINVAL;
 972
 973         for (ptr = rate_table; ptr->rate; ptr++) {
 974                 if (ptr->xtal != ck_ref.rate)
 975                         continue;
 976
 977                 highest_rate = ptr->rate;
 978
 979                 /* Can check only after xtal frequency check */
 980                 if (ptr->rate <= rate)
 981                         break;
 982         }
 983
 984         return highest_rate;
 985 }
 986
 987
 988 int clk_set_rate(struct clk *clk, unsigned long rate)
 989 {
 990         int  ret = -EINVAL;
 991         int  dsor_exp;
 992         __u16  regval;
 993         unsigned long  flags;
 994
 995         if (clk->flags & RATE_CKCTL) {
 996                 dsor_exp = calc_dsor_exp(clk, rate);
 997                 if (dsor_exp > 3)
 998                         dsor_exp = -EINVAL;
 999                 if (dsor_exp < 0)
1000                         return dsor_exp;
1001
1002                 spin_lock_irqsave(&clockfw_lock, flags);
1003                 regval = omap_readw(ARM_CKCTL);
1004                 regval &= ~(3 << clk->rate_offset);
1005                 regval |= dsor_exp << clk->rate_offset;
1006                 regval = verify_ckctl_value(regval);
1007                 omap_writew(regval, ARM_CKCTL);
1008                 clk->rate = clk->parent->rate / (1 << dsor_exp);
1009                 spin_unlock_irqrestore(&clockfw_lock, flags);
1010                 ret = 0;
1011         } else if(clk->set_rate != 0) {
1012                 spin_lock_irqsave(&clockfw_lock, flags);
1013                 ret = clk->set_rate(clk, rate);
1014                 spin_unlock_irqrestore(&clockfw_lock, flags);
1015         }
1016
1017         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
1018                 propagate_rate(clk);
1019
1020         return ret;
1021 }
1022 EXPORT_SYMBOL(clk_set_rate);
1023
1024
1025 static unsigned calc_ext_dsor(unsigned long rate)
1026 {
1027         unsigned dsor;
1028
1029         /* MCLK and BCLK divisor selection is not linear:
1030          * freq = 96MHz / dsor
1031          *
1032          * RATIO_SEL range: dsor <-> RATIO_SEL
1033          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
1034          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
1035          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
1036          * can not be used.
1037          */
1038         for (dsor = 2; dsor < 96; ++dsor) {
1039                 if ((dsor & 1) && dsor > 8)
1040                         continue;
1041                 if (rate >= 96000000 / dsor)
1042                         break;
1043         }
1044         return dsor;
1045 }
1046
1047 /* Only needed on 1510 */
1048 static int set_uart_rate(struct clk * clk, unsigned long rate)
1049 {
1050         unsigned int val;
1051
1052         val = omap_readl(clk->enable_reg);
1053         if (rate == 12000000)
1054                 val &= ~(1 << clk->enable_bit);
1055         else if (rate == 48000000)
1056                 val |= (1 << clk->enable_bit);
1057         else
1058                 return -EINVAL;
1059         omap_writel(val, clk->enable_reg);
1060         clk->rate = rate;
1061
1062         return 0;
1063 }
1064
1065 static int set_ext_clk_rate(struct clk *  clk, unsigned long rate)
1066 {
1067         unsigned dsor;
1068         __u16 ratio_bits;
1069
1070         dsor = calc_ext_dsor(rate);
1071         clk->rate = 96000000 / dsor;
1072         if (dsor > 8)
1073                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
1074         else
1075                 ratio_bits = (dsor - 2) << 2;
1076
1077         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
1078         omap_writew(ratio_bits, clk->enable_reg);
1079
1080         return 0;
1081 }
1082
1083
1084 static long round_ext_clk_rate(struct clk *  clk, unsigned long rate)
1085 {
1086         return 96000000 / calc_ext_dsor(rate);
1087 }
1088
1089
1090 static void init_ext_clk(struct clk *  clk)
1091 {
1092         unsigned dsor;
1093         __u16 ratio_bits;
1094
1095         /* Determine current rate and ensure clock is based on 96MHz APLL */
1096         ratio_bits = omap_readw(clk->enable_reg) & ~1;
1097         omap_writew(ratio_bits, clk->enable_reg);
1098
1099         ratio_bits = (ratio_bits & 0xfc) >> 2;
1100         if (ratio_bits > 6)
1101                 dsor = (ratio_bits - 6) * 2 + 8;
1102         else
1103                 dsor = ratio_bits + 2;
1104
1105         clk-> rate = 96000000 / dsor;
1106 }
1107
1108
1109 int clk_register(struct clk *clk)
1110 {
1111         down(&clocks_sem);
1112         list_add(&clk->node, &clocks);
1113         if (clk->init)
1114                 clk->init(clk);
1115         up(&clocks_sem);
1116         return 0;
1117 }
1118 EXPORT_SYMBOL(clk_register);
1119
1120 void clk_unregister(struct clk *clk)
1121 {
1122         down(&clocks_sem);
1123         list_del(&clk->node);
1124         up(&clocks_sem);
1125 }
1126 EXPORT_SYMBOL(clk_unregister);
1127
1128 #ifdef CONFIG_OMAP_RESET_CLOCKS
1129 /*
1130  * Resets some clocks that may be left on from bootloader,
1131  * but leaves serial clocks on. See also omap_late_clk_reset().
1132  */
1133 static inline void omap_early_clk_reset(void)
1134 {
1135         //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
1136 }
1137 #else
1138 #define omap_early_clk_reset()  {}
1139 #endif
1140
1141 int __init clk_init(void)
1142 {
1143         struct clk **  clkp;
1144         const struct omap_clock_config *info;
1145         int crystal_type = 0; /* Default 12 MHz */
1146
1147         omap_early_clk_reset();
1148
1149         for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
1150                 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1151                         clk_register(*clkp);
1152                         continue;
1153                 }
1154
1155                 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1156                         clk_register(*clkp);
1157                         continue;
1158                 }
1159
1160                 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1161                         clk_register(*clkp);
1162                         continue;
1163                 }
1164         }
1165
1166         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1167         if (info != NULL) {
1168                 if (!cpu_is_omap1510())
1169                         crystal_type = info->system_clock_type;
1170         }
1171
1172 #if defined(CONFIG_ARCH_OMAP730)
1173         ck_ref.rate = 13000000;
1174 #elif defined(CONFIG_ARCH_OMAP16XX)
1175         if (crystal_type == 2)
1176                 ck_ref.rate = 19200000;
1177 #endif
1178
1179         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1180                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1181                omap_readw(ARM_CKCTL));
1182
1183         /* We want to be in syncronous scalable mode */
1184         omap_writew(0x1000, ARM_SYSST);
1185
1186 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1187         /* Use values set by bootloader. Determine PLL rate and recalculate
1188          * dependent clocks as if kernel had changed PLL or divisors.
1189          */
1190         {
1191                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1192
1193                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1194                 if (pll_ctl_val & 0x10) {
1195                         /* PLL enabled, apply multiplier and divisor */
1196                         if (pll_ctl_val & 0xf80)
1197                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1198                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1199                 } else {
1200                         /* PLL disabled, apply bypass divisor */
1201                         switch (pll_ctl_val & 0xc) {
1202                         case 0:
1203                                 break;
1204                         case 0x4:
1205                                 ck_dpll1.rate /= 2;
1206                                 break;
1207                         default:
1208                                 ck_dpll1.rate /= 4;
1209                                 break;
1210                         }
1211                 }
1212         }
1213         propagate_rate(&ck_dpll1);
1214 #else
1215         /* Find the highest supported frequency and enable it */
1216         if (select_table_rate(&virtual_ck_mpu, ~0)) {
1217                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1218                 /* Guess sane values (60MHz) */
1219                 omap_writew(0x2290, DPLL_CTL);
1220                 omap_writew(0x1005, ARM_CKCTL);
1221                 ck_dpll1.rate = 60000000;
1222                 propagate_rate(&ck_dpll1);
1223         }
1224 #endif
1225         /* Cache rates for clocks connected to ck_ref (not dpll1) */
1226         propagate_rate(&ck_ref);
1227         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
1228                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
1229                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1230                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
1231                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
1232
1233 #ifdef CONFIG_MACH_OMAP_PERSEUS2
1234         /* Select slicer output as OMAP input clock */
1235         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1236 #endif
1237
1238         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1239         omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1240
1241         /* Put DSP/MPUI into reset until needed */
1242         omap_writew(0, ARM_RSTCT1);
1243         omap_writew(1, ARM_RSTCT2);
1244         omap_writew(0x400, ARM_IDLECT1);
1245
1246         /*
1247          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1248          * of the ARM_IDLECT2 register must be set to zero. The power-on
1249          * default value of this bit is one.
1250          */
1251         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
1252
1253         /*
1254          * Only enable those clocks we will need, let the drivers
1255          * enable other clocks as necessary
1256          */
1257         clk_use(&armper_ck);
1258         clk_use(&armxor_ck);
1259         clk_use(&armtim_ck);
1260
1261         if (cpu_is_omap1510())
1262                 clk_enable(&arm_gpio_ck);
1263
1264         return 0;
1265 }
1266
1267
1268 #ifdef CONFIG_OMAP_RESET_CLOCKS
1269
1270 static int __init omap_late_clk_reset(void)
1271 {
1272         /* Turn off all unused clocks */
1273         struct clk *p;
1274         __u32 regval32;
1275
1276         omap_writew(0, SOFT_REQ_REG);
1277         omap_writew(0, SOFT_REQ_REG2);
1278
1279         list_for_each_entry(p, &clocks, node) {
1280                 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1281                         p->enable_reg == 0)
1282                         continue;
1283
1284                 /* Assume no DSP clocks have been activated by bootloader */
1285                 if (p->flags & DSP_DOMAIN_CLOCK)
1286                         continue;
1287
1288                 /* Is the clock already disabled? */
1289                 if (p->flags & ENABLE_REG_32BIT) {
1290                         if (p->flags & VIRTUAL_IO_ADDRESS)
1291                                 regval32 = __raw_readl(p->enable_reg);
1292                         else
1293                                 regval32 = omap_readl(p->enable_reg);
1294                 } else {
1295                         if (p->flags & VIRTUAL_IO_ADDRESS)
1296                                 regval32 = __raw_readw(p->enable_reg);
1297                         else
1298                                 regval32 = omap_readw(p->enable_reg);
1299                 }
1300
1301                 if ((regval32 & (1 << p->enable_bit)) == 0)
1302                         continue;
1303
1304                 /* FIXME: This clock seems to be necessary but no-one
1305                  * has asked for its activation. */
1306                 if (p == &tc2_ck         // FIX: pm.c (SRAM), CCP, Camera
1307                     || p == &ck_dpll1out // FIX: SoSSI, SSR
1308                     || p == &arm_gpio_ck // FIX: GPIO code for 1510
1309                     ) {
1310                         printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1311                                p->name);
1312                         continue;
1313                 }
1314
1315                 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1316                 __clk_disable(p);
1317                 printk(" done\n");
1318         }
1319
1320         return 0;
1321 }
1322
1323 late_initcall(omap_late_clk_reset);
1324
1325 #endif