2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef __ASM_ARCH_MXC_MX31_H__
12 #define __ASM_ARCH_MXC_MX31_H__
14 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
15 #error "Do not include directly."
22 * ---------------------------------------------------------------------------
23 * FC000000 43F00000 1M AIPS 1
24 * FC100000 50000000 1M SPBA
25 * FC200000 53F00000 1M AIPS 2
26 * FC500000 60000000 128M ROMPATCH
27 * FC400000 68000000 128M AVIC
28 * 70000000 256M IPU (MAX M2)
29 * 80000000 256M CSD0 SDRAM/DDR
30 * 90000000 256M CSD1 SDRAM/DDR
31 * A0000000 128M CS0 Flash
32 * A8000000 128M CS1 Flash
35 * F4000000 B4000000 32M CS4
37 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
38 * C0000000 64M PCMCIA/CF
41 #define CS0_BASE_ADDR 0xA0000000
42 #define CS1_BASE_ADDR 0xA8000000
43 #define CS2_BASE_ADDR 0xB0000000
44 #define CS3_BASE_ADDR 0xB2000000
46 #define CS4_BASE_ADDR 0xB4000000
47 #define CS4_BASE_ADDR_VIRT 0xF4000000
48 #define CS4_SIZE SZ_32M
50 #define CS5_BASE_ADDR 0xB6000000
51 #define PCMCIA_MEM_BASE_ADDR 0xBC000000
56 #define L2CC_BASE_ADDR 0x30000000
57 #define L2CC_SIZE SZ_1M
62 #define AIPS1_BASE_ADDR 0x43F00000
63 #define AIPS1_BASE_ADDR_VIRT 0xFC000000
64 #define AIPS1_SIZE SZ_1M
66 #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
67 #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
68 #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
69 #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
70 #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
71 #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
72 #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
73 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
74 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
75 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
76 #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
77 #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
78 #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
79 #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
80 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
81 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
82 #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
83 #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
86 * SPBA global module enabled #0
88 #define SPBA0_BASE_ADDR 0x50000000
89 #define SPBA0_BASE_ADDR_VIRT 0xFC100000
90 #define SPBA0_SIZE SZ_1M
92 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
93 #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
94 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
95 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
96 #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
97 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
102 #define AIPS2_BASE_ADDR 0x53F00000
103 #define AIPS2_BASE_ADDR_VIRT 0xFC200000
104 #define AIPS2_SIZE SZ_1M
105 #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
106 #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
107 #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
108 #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
109 #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
110 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
111 #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
112 #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
113 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
114 #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
115 #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
116 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
117 #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
118 #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
119 #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
120 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
125 #define ROMP_BASE_ADDR 0x60000000
126 #define ROMP_BASE_ADDR_VIRT 0xFC500000
127 #define ROMP_SIZE SZ_1M
129 #define AVIC_BASE_ADDR 0x68000000
130 #define AVIC_BASE_ADDR_VIRT 0xFC400000
131 #define AVIC_SIZE SZ_1M
134 * NAND, SDRAM, WEIM, M3IF, EMI controllers
136 #define X_MEMC_BASE_ADDR 0xB8000000
137 #define X_MEMC_BASE_ADDR_VIRT 0xFC320000
138 #define X_MEMC_SIZE SZ_64K
140 #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
141 #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
142 #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
143 #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
144 #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
147 * Memory regions and CS
149 #define IPU_MEM_BASE_ADDR 0x70000000
150 #define CSD0_BASE_ADDR 0x80000000
151 #define CSD1_BASE_ADDR 0x90000000
154 * This macro defines the physical to virtual address mapping for all the
155 * peripheral modules. It is used by passing in the physical address as x
156 * and returning the virtual address. If the physical address is not mapped,
157 * it returns 0xDEADBEEF
159 #define IO_ADDRESS(x) \
160 (void __force __iomem *) \
161 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
162 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
163 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
164 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
165 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
166 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
167 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
171 * define the address mapping macros: in physical address order
173 #define L2CC_IO_ADDRESS(x) \
174 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
176 #define AIPS1_IO_ADDRESS(x) \
177 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
179 #define SPBA0_IO_ADDRESS(x) \
180 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
182 #define AIPS2_IO_ADDRESS(x) \
183 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
185 #define ROMP_IO_ADDRESS(x) \
186 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
188 #define AVIC_IO_ADDRESS(x) \
189 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
191 #define CS4_IO_ADDRESS(x) \
192 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
194 #define X_MEMC_IO_ADDRESS(x) \
195 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
197 #define PCMCIA_IO_ADDRESS(x) \
198 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
203 #define MXC_INT_I2C3 3
204 #define MXC_INT_I2C2 4
205 #define MXC_INT_RTIC 6
206 #define MXC_INT_I2C 10
207 #define MXC_INT_CSPI2 13
208 #define MXC_INT_CSPI1 14
209 #define MXC_INT_ATA 15
210 #define MXC_INT_UART3 18
211 #define MXC_INT_IIM 19
212 #define MXC_INT_RNGA 22
213 #define MXC_INT_EVTMON 23
214 #define MXC_INT_KPP 24
215 #define MXC_INT_RTC 25
216 #define MXC_INT_PWM 26
217 #define MXC_INT_EPIT2 27
218 #define MXC_INT_EPIT1 28
219 #define MXC_INT_GPT 29
220 #define MXC_INT_POWER_FAIL 30
221 #define MXC_INT_UART2 32
222 #define MXC_INT_NANDFC 33
223 #define MXC_INT_SDMA 34
224 #define MXC_INT_MSHC1 39
225 #define MXC_INT_IPU_ERR 41
226 #define MXC_INT_IPU_SYN 42
227 #define MXC_INT_UART1 45
228 #define MXC_INT_ECT 48
229 #define MXC_INT_SCC_SCM 49
230 #define MXC_INT_SCC_SMN 50
231 #define MXC_INT_GPIO2 51
232 #define MXC_INT_GPIO1 52
233 #define MXC_INT_WDOG 55
234 #define MXC_INT_GPIO3 56
235 #define MXC_INT_EXT_POWER 58
236 #define MXC_INT_EXT_TEMPER 59
237 #define MXC_INT_EXT_SENSOR60 60
238 #define MXC_INT_EXT_SENSOR61 61
239 #define MXC_INT_EXT_WDOG 62
240 #define MXC_INT_EXT_TV 63
242 #define PROD_SIGNATURE 0x1 /* For MX31 */
244 /* silicon revisions specific to i.MX31 */
245 #define CHIP_REV_1_0 0x10
246 #define CHIP_REV_1_1 0x11
247 #define CHIP_REV_1_2 0x12
248 #define CHIP_REV_1_3 0x13
249 #define CHIP_REV_2_0 0x20
250 #define CHIP_REV_2_1 0x21
251 #define CHIP_REV_2_2 0x22
252 #define CHIP_REV_2_3 0x23
253 #define CHIP_REV_3_0 0x30
254 #define CHIP_REV_3_1 0x31
255 #define CHIP_REV_3_2 0x32
257 #define SYSTEM_REV_MIN CHIP_REV_1_0
258 #define SYSTEM_REV_NUM 3
260 /* gpio and gpio based interrupt handling */
262 #define GPIO_GDIR 0x04
263 #define GPIO_PSR 0x08
264 #define GPIO_ICR1 0x0C
265 #define GPIO_ICR2 0x10
266 #define GPIO_IMR 0x14
267 #define GPIO_ISR 0x18
268 #define GPIO_INT_LOW_LEV 0x0
269 #define GPIO_INT_HIGH_LEV 0x1
270 #define GPIO_INT_RISE_EDGE 0x2
271 #define GPIO_INT_FALL_EDGE 0x3
272 #define GPIO_INT_NONE 0x4
274 /* Mandatory defines used globally */
276 /* this CPU supports up to 96 GPIOs */
277 #define ARCH_NR_GPIOS 96
279 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
281 extern unsigned int system_rev;
283 static inline int mx31_revision(void)
289 #endif /* __ASM_ARCH_MXC_MX31_H__ */