arch/arm/mm/proc-xscale.S

   1 /*
   2  *  linux/arch/arm/mm/proc-xscale.S
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    November 2000
   6  *  Copyright:  (C) 2000, 2001 MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * MMU functions for the Intel XScale CPUs
  13  *
  14  * 2001 Aug 21:
  15  *      some contributions by Brett Gaines <brett.w.gaines@intel.com>
  16  *      Copyright 2001 by Intel Corp.
  17  *
  18  * 2001 Sep 08:
  19  *      Completely revisited, many important fixes
  20  *      Nicolas Pitre <nico@cam.org>
  21  */
  22
  23 #include <linux/linkage.h>
  24 #include <linux/init.h>
  25 #include <asm/assembler.h>
  26 #include <asm/elf.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/pgtable-hwdef.h>
  29 #include <asm/page.h>
  30 #include <asm/ptrace.h>
  31 #include "proc-macros.S"
  32
  33 /*
  34  * This is the maximum size of an area which will be flushed.  If the area
  35  * is larger than this, then we flush the whole cache
  36  */
  37 #define MAX_AREA_SIZE   32768
  38
  39 /*
  40  * the cache line size of the I and D cache
  41  */
  42 #define CACHELINESIZE   32
  43
  44 /*
  45  * the size of the data cache
  46  */
  47 #define CACHESIZE       32768
  48
  49 /*
  50  * Virtual address used to allocate the cache when flushed
  51  *
  52  * This must be an address range which is _never_ used.  It should
  53  * apparently have a mapping in the corresponding page table for
  54  * compatibility with future CPUs that _could_ require it.  For instance we
  55  * don't care.
  56  *
  57  * This must be aligned on a 2*CACHESIZE boundary.  The code selects one of
  58  * the 2 areas in alternance each time the clean_d_cache macro is used.
  59  * Without this the XScale core exhibits cache eviction problems and no one
  60  * knows why.
  61  *
  62  * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
  63  */
  64 #define CLEAN_ADDR      0xfffe0000
  65
  66 /*
  67  * This macro is used to wait for a CP15 write and is needed
  68  * when we have to ensure that the last operation to the co-pro
  69  * was completed before continuing with operation.
  70  */
  71         .macro  cpwait, rd
  72         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
  73         mov     \rd, \rd                        @ wait for completion
  74         sub     pc, pc, #4                      @ flush instruction pipeline
  75         .endm
  76
  77         .macro  cpwait_ret, lr, rd
  78         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
  79         sub     pc, \lr, \rd, LSR #32           @ wait for completion and
  80                                                 @ flush instruction pipeline
  81         .endm
  82
  83 /*
  84  * This macro cleans the entire dcache using line allocate.
  85  * The main loop has been unrolled to reduce loop overhead.
  86  * rd and rs are two scratch registers.
  87  */
  88         .macro  clean_d_cache, rd, rs
  89         ldr     \rs, =clean_addr
  90         ldr     \rd, [\rs]
  91         eor     \rd, \rd, #CACHESIZE
  92         str     \rd, [\rs]
  93         add     \rs, \rd, #CACHESIZE
  94 1:      mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  95         add     \rd, \rd, #CACHELINESIZE
  96         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  97         add     \rd, \rd, #CACHELINESIZE
  98         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  99         add     \rd, \rd, #CACHELINESIZE
 100         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
 101         add     \rd, \rd, #CACHELINESIZE
 102         teq     \rd, \rs
 103         bne     1b
 104         .endm
 105
 106         .data
 107 clean_addr:     .word   CLEAN_ADDR
 108
 109         .text
 110
 111 /*
 112  * cpu_xscale_proc_init()
 113  *
 114  * Nothing too exciting at the moment
 115  */
 116 ENTRY(cpu_xscale_proc_init)
 117         mov     pc, lr
 118
 119 /*
 120  * cpu_xscale_proc_fin()
 121  */
 122 ENTRY(cpu_xscale_proc_fin)
 123         str     lr, [sp, #-4]!
 124         mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 125         msr     cpsr_c, r0
 126         bl      xscale_flush_kern_cache_all     @ clean caches
 127         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
 128         bic     r0, r0, #0x1800                 @ ...IZ...........
 129         bic     r0, r0, #0x0006                 @ .............CA.
 130         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
 131         ldr     pc, [sp], #4
 132
 133 /*
 134  * cpu_xscale_reset(loc)
 135  *
 136  * Perform a soft reset of the system.  Put the CPU into the
 137  * same state as it would be if it had been reset, and branch
 138  * to what would be the reset vector.
 139  *
 140  * loc: location to jump to for soft reset
 141  *
 142  * Beware PXA270 erratum E7.
 143  */
 144         .align  5
 145 ENTRY(cpu_xscale_reset)
 146         mov     r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 147         msr     cpsr_c, r1                      @ reset CPSR
 148         mcr     p15, 0, r1, c10, c4, 1          @ unlock I-TLB
 149         mcr     p15, 0, r1, c8, c5, 0           @ invalidate I-TLB
 150         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
 151         bic     r1, r1, #0x0086                 @ ........B....CA.
 152         bic     r1, r1, #0x3900                 @ ..VIZ..S........
 153         sub     pc, pc, #4                      @ flush pipeline
 154         @ *** cache line aligned ***
 155         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
 156         bic     r1, r1, #0x0001                 @ ...............M
 157         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches & BTB
 158         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
 159         @ CAUTION: MMU turned off from this point. We count on the pipeline
 160         @ already containing those two last instructions to survive.
 161         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 162         mov     pc, r0
 163
 164 /*
 165  * cpu_xscale_do_idle()
 166  *
 167  * Cause the processor to idle
 168  *
 169  * For now we do nothing but go to idle mode for every case
 170  *
 171  * XScale supports clock switching, but using idle mode support
 172  * allows external hardware to react to system state changes.
 173  */
 174         .align  5
 175
 176 ENTRY(cpu_xscale_do_idle)
 177         mov     r0, #1
 178         mcr     p14, 0, r0, c7, c0, 0           @ Go to IDLE
 179         mov     pc, lr
 180
 181 /* ================================= CACHE ================================ */
 182
 183 /*
 184  *      flush_user_cache_all()
 185  *
 186  *      Invalidate all cache entries in a particular address
 187  *      space.
 188  */
 189 ENTRY(xscale_flush_user_cache_all)
 190         /* FALLTHROUGH */
 191
 192 /*
 193  *      flush_kern_cache_all()
 194  *
 195  *      Clean and invalidate the entire cache.
 196  */
 197 ENTRY(xscale_flush_kern_cache_all)
 198         mov     r2, #VM_EXEC
 199         mov     ip, #0
 200 __flush_whole_cache:
 201         clean_d_cache r0, r1
 202         tst     r2, #VM_EXEC
 203         mcrne   p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
 204         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 205         mov     pc, lr
 206
 207 /*
 208  *      flush_user_cache_range(start, end, vm_flags)
 209  *
 210  *      Invalidate a range of cache entries in the specified
 211  *      address space.
 212  *
 213  *      - start - start address (may not be aligned)
 214  *      - end   - end address (exclusive, may not be aligned)
 215  *      - vma   - vma_area_struct describing address space
 216  */
 217         .align  5
 218 ENTRY(xscale_flush_user_cache_range)
 219         mov     ip, #0
 220         sub     r3, r1, r0                      @ calculate total size
 221         cmp     r3, #MAX_AREA_SIZE
 222         bhs     __flush_whole_cache
 223
 224 1:      tst     r2, #VM_EXEC
 225         mcrne   p15, 0, r0, c7, c5, 1           @ Invalidate I cache line
 226         mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
 227         mcr     p15, 0, r0, c7, c6, 1           @ Invalidate D cache line
 228         add     r0, r0, #CACHELINESIZE
 229         cmp     r0, r1
 230         blo     1b
 231         tst     r2, #VM_EXEC
 232         mcrne   p15, 0, ip, c7, c5, 6           @ Invalidate BTB
 233         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 234         mov     pc, lr
 235
 236 /*
 237  *      coherent_kern_range(start, end)
 238  *
 239  *      Ensure coherency between the Icache and the Dcache in the
 240  *      region described by start.  If you have non-snooping
 241  *      Harvard caches, you need to implement this function.
 242  *
 243  *      - start  - virtual start address
 244  *      - end    - virtual end address
 245  *
 246  *      Note: single I-cache line invalidation isn't used here since
 247  *      it also trashes the mini I-cache used by JTAG debuggers.
 248  */
 249 ENTRY(xscale_coherent_kern_range)
 250         bic     r0, r0, #CACHELINESIZE - 1
 251 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 252         add     r0, r0, #CACHELINESIZE
 253         cmp     r0, r1
 254         blo     1b
 255         mov     r0, #0
 256         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
 257         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 258         mov     pc, lr
 259
 260 /*
 261  *      coherent_user_range(start, end)
 262  *
 263  *      Ensure coherency between the Icache and the Dcache in the
 264  *      region described by start.  If you have non-snooping
 265  *      Harvard caches, you need to implement this function.
 266  *
 267  *      - start  - virtual start address
 268  *      - end    - virtual end address
 269  */
 270 ENTRY(xscale_coherent_user_range)
 271         bic     r0, r0, #CACHELINESIZE - 1
 272 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 273         mcr     p15, 0, r0, c7, c5, 1           @ Invalidate I cache entry
 274         add     r0, r0, #CACHELINESIZE
 275         cmp     r0, r1
 276         blo     1b
 277         mov     r0, #0
 278         mcr     p15, 0, r0, c7, c5, 6           @ Invalidate BTB
 279         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 280         mov     pc, lr
 281
 282 /*
 283  *      flush_kern_dcache_page(void *page)
 284  *
 285  *      Ensure no D cache aliasing occurs, either with itself or
 286  *      the I cache
 287  *
 288  *      - addr  - page aligned address
 289  */
 290 ENTRY(xscale_flush_kern_dcache_page)
 291         add     r1, r0, #PAGE_SZ
 292 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 293         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 294         add     r0, r0, #CACHELINESIZE
 295         cmp     r0, r1
 296         blo     1b
 297         mov     r0, #0
 298         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
 299         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 300         mov     pc, lr
 301
 302 /*
 303  *      dma_inv_range(start, end)
 304  *
 305  *      Invalidate (discard) the specified virtual address range.
 306  *      May not write back any entries.  If 'start' or 'end'
 307  *      are not cache line aligned, those lines must be written
 308  *      back.
 309  *
 310  *      - start  - virtual start address
 311  *      - end    - virtual end address
 312  */
 313 ENTRY(xscale_dma_inv_range)
 314         tst     r0, #CACHELINESIZE - 1
 315         bic     r0, r0, #CACHELINESIZE - 1
 316         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 317         tst     r1, #CACHELINESIZE - 1
 318         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 319 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 320         add     r0, r0, #CACHELINESIZE
 321         cmp     r0, r1
 322         blo     1b
 323         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 324         mov     pc, lr
 325
 326 /*
 327  *      dma_clean_range(start, end)
 328  *
 329  *      Clean the specified virtual address range.
 330  *
 331  *      - start  - virtual start address
 332  *      - end    - virtual end address
 333  */
 334 ENTRY(xscale_dma_clean_range)
 335         bic     r0, r0, #CACHELINESIZE - 1
 336 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 337         add     r0, r0, #CACHELINESIZE
 338         cmp     r0, r1
 339         blo     1b
 340         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 341         mov     pc, lr
 342
 343 /*
 344  *      dma_flush_range(start, end)
 345  *
 346  *      Clean and invalidate the specified virtual address range.
 347  *
 348  *      - start  - virtual start address
 349  *      - end    - virtual end address
 350  */
 351 ENTRY(xscale_dma_flush_range)
 352         bic     r0, r0, #CACHELINESIZE - 1
 353 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 354         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 355         add     r0, r0, #CACHELINESIZE
 356         cmp     r0, r1
 357         blo     1b
 358         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 359         mov     pc, lr
 360
 361 ENTRY(xscale_cache_fns)
 362         .long   xscale_flush_kern_cache_all
 363         .long   xscale_flush_user_cache_all
 364         .long   xscale_flush_user_cache_range
 365         .long   xscale_coherent_kern_range
 366         .long   xscale_coherent_user_range
 367         .long   xscale_flush_kern_dcache_page
 368         .long   xscale_dma_inv_range
 369         .long   xscale_dma_clean_range
 370         .long   xscale_dma_flush_range
 371
 372 /*
 373  * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
 374  * clear the dirty bits, which means that if we invalidate a dirty line,
 375  * the dirty data can still be written back to external memory later on.
 376  *
 377  * The recommended workaround is to always do a clean D-cache line before
 378  * doing an invalidate D-cache line, so on the affected processors,
 379  * dma_inv_range() is implemented as dma_flush_range().
 380  *
 381  * See erratum #25 of "Intel 80200 Processor Specification Update",
 382  * revision January 22, 2003, available at:
 383  *     http://www.intel.com/design/iio/specupdt/273415.htm
 384  */
 385 ENTRY(xscale_80200_A0_A1_cache_fns)
 386         .long   xscale_flush_kern_cache_all
 387         .long   xscale_flush_user_cache_all
 388         .long   xscale_flush_user_cache_range
 389         .long   xscale_coherent_kern_range
 390         .long   xscale_coherent_user_range
 391         .long   xscale_flush_kern_dcache_page
 392         .long   xscale_dma_flush_range
 393         .long   xscale_dma_clean_range
 394         .long   xscale_dma_flush_range
 395
 396 ENTRY(cpu_xscale_dcache_clean_area)
 397 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 398         add     r0, r0, #CACHELINESIZE
 399         subs    r1, r1, #CACHELINESIZE
 400         bhi     1b
 401         mov     pc, lr
 402
 403 /* =============================== PageTable ============================== */
 404
 405 #define PTE_CACHE_WRITE_ALLOCATE 0
 406
 407 /*
 408  * cpu_xscale_switch_mm(pgd)
 409  *
 410  * Set the translation base pointer to be as described by pgd.
 411  *
 412  * pgd: new page tables
 413  */
 414         .align  5
 415 ENTRY(cpu_xscale_switch_mm)
 416         clean_d_cache r1, r2
 417         mcr     p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
 418         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 419         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 420         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 421         cpwait_ret lr, ip
 422
 423 /*
 424  * cpu_xscale_set_pte_ext(ptep, pte, ext)
 425  *
 426  * Set a PTE and flush it out
 427  *
 428  * Errata 40: must set memory to write-through for user read-only pages.
 429  */
 430         .align  5
 431 ENTRY(cpu_xscale_set_pte_ext)
 432         str     r1, [r0], #-2048                @ linux version
 433
 434         bic     r2, r1, #0xff0
 435         orr     r2, r2, #PTE_TYPE_EXT           @ extended page
 436
 437         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 438
 439         tst     r3, #L_PTE_USER                 @ User?
 440         orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
 441
 442         tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 443         orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
 444                                                 @ combined with user -> user r/w
 445
 446         @
 447         @ Handle the X bit.  We want to set this bit for the minicache
 448         @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
 449         @ and we have a writeable, cacheable region.  If we ignore the
 450         @ U and E bits, we can allow user space to use the minicache as
 451         @ well.
 452         @
 453         @  X = (C & ~W & ~B) | (C & W & B & write_allocate)
 454         @
 455         eor     ip, r1, #L_PTE_CACHEABLE
 456         tst     ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
 457 #if PTE_CACHE_WRITE_ALLOCATE
 458         eorne   ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
 459         tstne   ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
 460 #endif
 461         orreq   r2, r2, #PTE_EXT_TEX(1)
 462
 463         @
 464         @ Erratum 40: The B bit must be cleared for a user read-only
 465         @ cacheable page.
 466         @
 467         @  B = B & ~(U & C & ~W)
 468         @
 469         and     ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
 470         teq     ip, #L_PTE_USER | L_PTE_CACHEABLE
 471         biceq   r2, r2, #PTE_BUFFERABLE
 472
 473         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 474         movne   r2, #0                          @ no -> fault
 475
 476         str     r2, [r0]                        @ hardware version
 477         mov     ip, #0
 478         mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
 479         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 480         mov     pc, lr
 481
 482
 483         .ltorg
 484
 485         .align
 486
 487         __INIT
 488
 489         .type   __xscale_setup, #function
 490 __xscale_setup:
 491         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
 492         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 493         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I, D TLBs
 494         mov     r0, #1 << 6                     @ cp6 for IOP3xx and Bulverde
 495         orr     r0, r0, #1 << 13                @ Its undefined whether this
 496         mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
 497
 498         adr     r5, xscale_crval
 499         ldmia   r5, {r5, r6}
 500         mrc     p15, 0, r0, c1, c0, 0           @ get control register
 501         bic     r0, r0, r5
 502         orr     r0, r0, r6
 503         mov     pc, lr
 504         .size   __xscale_setup, . - __xscale_setup
 505
 506         /*
 507          *  R
 508          * .RVI ZFRS BLDP WCAM
 509          * ..11 1.01 .... .101
 510          *
 511          */
 512         .type   xscale_crval, #object
 513 xscale_crval:
 514         crval   clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
 515
 516         __INITDATA
 517
 518 /*
 519  * Purpose : Function pointers used to access above functions - all calls
 520  *           come through these
 521  */
 522
 523         .type   xscale_processor_functions, #object
 524 ENTRY(xscale_processor_functions)
 525         .word   v5t_early_abort
 526         .word   cpu_xscale_proc_init
 527         .word   cpu_xscale_proc_fin
 528         .word   cpu_xscale_reset
 529         .word   cpu_xscale_do_idle
 530         .word   cpu_xscale_dcache_clean_area
 531         .word   cpu_xscale_switch_mm
 532         .word   cpu_xscale_set_pte_ext
 533         .word   pabort_noifar
 534         .size   xscale_processor_functions, . - xscale_processor_functions
 535
 536         .section ".rodata"
 537
 538         .type   cpu_arch_name, #object
 539 cpu_arch_name:
 540         .asciz  "armv5te"
 541         .size   cpu_arch_name, . - cpu_arch_name
 542
 543         .type   cpu_elf_name, #object
 544 cpu_elf_name:
 545         .asciz  "v5"
 546         .size   cpu_elf_name, . - cpu_elf_name
 547
 548         .type   cpu_80200_A0_A1_name, #object
 549 cpu_80200_A0_A1_name:
 550         .asciz  "XScale-80200 A0/A1"
 551         .size   cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
 552
 553         .type   cpu_80200_name, #object
 554 cpu_80200_name:
 555         .asciz  "XScale-80200"
 556         .size   cpu_80200_name, . - cpu_80200_name
 557
 558         .type   cpu_80219_name, #object
 559 cpu_80219_name:
 560         .asciz  "XScale-80219"
 561         .size   cpu_80219_name, . - cpu_80219_name
 562
 563         .type   cpu_8032x_name, #object
 564 cpu_8032x_name:
 565         .asciz  "XScale-IOP8032x Family"
 566         .size   cpu_8032x_name, . - cpu_8032x_name
 567
 568         .type   cpu_8033x_name, #object
 569 cpu_8033x_name:
 570         .asciz  "XScale-IOP8033x Family"
 571         .size   cpu_8033x_name, . - cpu_8033x_name
 572
 573         .type   cpu_pxa250_name, #object
 574 cpu_pxa250_name:
 575         .asciz  "XScale-PXA250"
 576         .size   cpu_pxa250_name, . - cpu_pxa250_name
 577
 578         .type   cpu_pxa210_name, #object
 579 cpu_pxa210_name:
 580         .asciz  "XScale-PXA210"
 581         .size   cpu_pxa210_name, . - cpu_pxa210_name
 582
 583         .type   cpu_ixp42x_name, #object
 584 cpu_ixp42x_name:
 585         .asciz  "XScale-IXP42x Family"
 586         .size   cpu_ixp42x_name, . - cpu_ixp42x_name
 587
 588         .type   cpu_ixp43x_name, #object
 589 cpu_ixp43x_name:
 590         .asciz  "XScale-IXP43x Family"
 591         .size   cpu_ixp43x_name, . - cpu_ixp43x_name
 592
 593         .type   cpu_ixp46x_name, #object
 594 cpu_ixp46x_name:
 595         .asciz  "XScale-IXP46x Family"
 596         .size   cpu_ixp46x_name, . - cpu_ixp46x_name
 597
 598         .type   cpu_ixp2400_name, #object
 599 cpu_ixp2400_name:
 600         .asciz  "XScale-IXP2400"
 601         .size   cpu_ixp2400_name, . - cpu_ixp2400_name
 602
 603         .type   cpu_ixp2800_name, #object
 604 cpu_ixp2800_name:
 605         .asciz  "XScale-IXP2800"
 606         .size   cpu_ixp2800_name, . - cpu_ixp2800_name
 607
 608         .type   cpu_pxa255_name, #object
 609 cpu_pxa255_name:
 610         .asciz  "XScale-PXA255"
 611         .size   cpu_pxa255_name, . - cpu_pxa255_name
 612
 613         .type   cpu_pxa270_name, #object
 614 cpu_pxa270_name:
 615         .asciz  "XScale-PXA270"
 616         .size   cpu_pxa270_name, . - cpu_pxa270_name
 617
 618         .align
 619
 620         .section ".proc.info.init", #alloc, #execinstr
 621
 622         .type   __80200_A0_A1_proc_info,#object
 623 __80200_A0_A1_proc_info:
 624         .long   0x69052000
 625         .long   0xfffffffe
 626         .long   PMD_TYPE_SECT | \
 627                 PMD_SECT_BUFFERABLE | \
 628                 PMD_SECT_CACHEABLE | \
 629                 PMD_SECT_AP_WRITE | \
 630                 PMD_SECT_AP_READ
 631         .long   PMD_TYPE_SECT | \
 632                 PMD_SECT_AP_WRITE | \
 633                 PMD_SECT_AP_READ
 634         b       __xscale_setup
 635         .long   cpu_arch_name
 636         .long   cpu_elf_name
 637         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 638         .long   cpu_80200_name
 639         .long   xscale_processor_functions
 640         .long   v4wbi_tlb_fns
 641         .long   xscale_mc_user_fns
 642         .long   xscale_80200_A0_A1_cache_fns
 643         .size   __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
 644
 645         .type   __80200_proc_info,#object
 646 __80200_proc_info:
 647         .long   0x69052000
 648         .long   0xfffffff0
 649         .long   PMD_TYPE_SECT | \
 650                 PMD_SECT_BUFFERABLE | \
 651                 PMD_SECT_CACHEABLE | \
 652                 PMD_SECT_AP_WRITE | \
 653                 PMD_SECT_AP_READ
 654         .long   PMD_TYPE_SECT | \
 655                 PMD_SECT_AP_WRITE | \
 656                 PMD_SECT_AP_READ
 657         b       __xscale_setup
 658         .long   cpu_arch_name
 659         .long   cpu_elf_name
 660         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 661         .long   cpu_80200_name
 662         .long   xscale_processor_functions
 663         .long   v4wbi_tlb_fns
 664         .long   xscale_mc_user_fns
 665         .long   xscale_cache_fns
 666         .size   __80200_proc_info, . - __80200_proc_info
 667
 668         .type   __80219_proc_info,#object
 669 __80219_proc_info:
 670         .long   0x69052e20
 671         .long   0xffffffe0
 672         .long   PMD_TYPE_SECT | \
 673                 PMD_SECT_BUFFERABLE | \
 674                 PMD_SECT_CACHEABLE | \
 675                 PMD_SECT_AP_WRITE | \
 676                 PMD_SECT_AP_READ
 677         .long   PMD_TYPE_SECT | \
 678                 PMD_SECT_AP_WRITE | \
 679                 PMD_SECT_AP_READ
 680         b       __xscale_setup
 681         .long   cpu_arch_name
 682         .long   cpu_elf_name
 683         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 684         .long   cpu_80219_name
 685         .long   xscale_processor_functions
 686         .long   v4wbi_tlb_fns
 687         .long   xscale_mc_user_fns
 688         .long   xscale_cache_fns
 689         .size   __80219_proc_info, . - __80219_proc_info
 690
 691         .type   __8032x_proc_info,#object
 692 __8032x_proc_info:
 693         .long   0x69052420
 694         .long   0xfffff7e0
 695         .long   PMD_TYPE_SECT | \
 696                 PMD_SECT_BUFFERABLE | \
 697                 PMD_SECT_CACHEABLE | \
 698                 PMD_SECT_AP_WRITE | \
 699                 PMD_SECT_AP_READ
 700         .long   PMD_TYPE_SECT | \
 701                 PMD_SECT_AP_WRITE | \
 702                 PMD_SECT_AP_READ
 703         b       __xscale_setup
 704         .long   cpu_arch_name
 705         .long   cpu_elf_name
 706         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 707         .long   cpu_8032x_name
 708         .long   xscale_processor_functions
 709         .long   v4wbi_tlb_fns
 710         .long   xscale_mc_user_fns
 711         .long   xscale_cache_fns
 712         .size   __8032x_proc_info, . - __8032x_proc_info
 713
 714         .type   __8033x_proc_info,#object
 715 __8033x_proc_info:
 716         .long   0x69054010
 717         .long   0xfffffd30
 718         .long   PMD_TYPE_SECT | \
 719                 PMD_SECT_BUFFERABLE | \
 720                 PMD_SECT_CACHEABLE | \
 721                 PMD_SECT_AP_WRITE | \
 722                 PMD_SECT_AP_READ
 723         .long   PMD_TYPE_SECT | \
 724                 PMD_SECT_AP_WRITE | \
 725                 PMD_SECT_AP_READ
 726         b       __xscale_setup
 727         .long   cpu_arch_name
 728         .long   cpu_elf_name
 729         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 730         .long   cpu_8033x_name
 731         .long   xscale_processor_functions
 732         .long   v4wbi_tlb_fns
 733         .long   xscale_mc_user_fns
 734         .long   xscale_cache_fns
 735         .size   __8033x_proc_info, . - __8033x_proc_info
 736
 737         .type   __pxa250_proc_info,#object
 738 __pxa250_proc_info:
 739         .long   0x69052100
 740         .long   0xfffff7f0
 741         .long   PMD_TYPE_SECT | \
 742                 PMD_SECT_BUFFERABLE | \
 743                 PMD_SECT_CACHEABLE | \
 744                 PMD_SECT_AP_WRITE | \
 745                 PMD_SECT_AP_READ
 746         .long   PMD_TYPE_SECT | \
 747                 PMD_SECT_AP_WRITE | \
 748                 PMD_SECT_AP_READ
 749         b       __xscale_setup
 750         .long   cpu_arch_name
 751         .long   cpu_elf_name
 752         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 753         .long   cpu_pxa250_name
 754         .long   xscale_processor_functions
 755         .long   v4wbi_tlb_fns
 756         .long   xscale_mc_user_fns
 757         .long   xscale_cache_fns
 758         .size   __pxa250_proc_info, . - __pxa250_proc_info
 759
 760         .type   __pxa210_proc_info,#object
 761 __pxa210_proc_info:
 762         .long   0x69052120
 763         .long   0xfffff3f0
 764         .long   PMD_TYPE_SECT | \
 765                 PMD_SECT_BUFFERABLE | \
 766                 PMD_SECT_CACHEABLE | \
 767                 PMD_SECT_AP_WRITE | \
 768                 PMD_SECT_AP_READ
 769         .long   PMD_TYPE_SECT | \
 770                 PMD_SECT_AP_WRITE | \
 771                 PMD_SECT_AP_READ
 772         b       __xscale_setup
 773         .long   cpu_arch_name
 774         .long   cpu_elf_name
 775         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 776         .long   cpu_pxa210_name
 777         .long   xscale_processor_functions
 778         .long   v4wbi_tlb_fns
 779         .long   xscale_mc_user_fns
 780         .long   xscale_cache_fns
 781         .size   __pxa210_proc_info, . - __pxa210_proc_info
 782
 783         .type   __ixp2400_proc_info, #object
 784 __ixp2400_proc_info:
 785         .long   0x69054190
 786         .long   0xfffffff0
 787         .long   PMD_TYPE_SECT | \
 788                 PMD_SECT_BUFFERABLE | \
 789                 PMD_SECT_CACHEABLE | \
 790                 PMD_SECT_AP_WRITE | \
 791                 PMD_SECT_AP_READ
 792         .long   PMD_TYPE_SECT | \
 793                 PMD_SECT_AP_WRITE | \
 794                 PMD_SECT_AP_READ
 795         b       __xscale_setup
 796         .long   cpu_arch_name
 797         .long   cpu_elf_name
 798         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 799         .long   cpu_ixp2400_name
 800         .long   xscale_processor_functions
 801         .long   v4wbi_tlb_fns
 802         .long   xscale_mc_user_fns
 803         .long   xscale_cache_fns
 804         .size   __ixp2400_proc_info, . - __ixp2400_proc_info
 805
 806         .type   __ixp2800_proc_info, #object
 807 __ixp2800_proc_info:
 808         .long   0x690541a0
 809         .long   0xfffffff0
 810         .long   PMD_TYPE_SECT | \
 811                 PMD_SECT_BUFFERABLE | \
 812                 PMD_SECT_CACHEABLE | \
 813                 PMD_SECT_AP_WRITE | \
 814                 PMD_SECT_AP_READ
 815         .long   PMD_TYPE_SECT | \
 816                 PMD_SECT_AP_WRITE | \
 817                 PMD_SECT_AP_READ
 818         b       __xscale_setup
 819         .long   cpu_arch_name
 820         .long   cpu_elf_name
 821         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 822         .long   cpu_ixp2800_name
 823         .long   xscale_processor_functions
 824         .long   v4wbi_tlb_fns
 825         .long   xscale_mc_user_fns
 826         .long   xscale_cache_fns
 827         .size   __ixp2800_proc_info, . - __ixp2800_proc_info
 828
 829         .type   __ixp42x_proc_info, #object
 830 __ixp42x_proc_info:
 831         .long   0x690541c0
 832         .long   0xffffffc0
 833         .long   PMD_TYPE_SECT | \
 834                 PMD_SECT_BUFFERABLE | \
 835                 PMD_SECT_CACHEABLE | \
 836                 PMD_SECT_AP_WRITE | \
 837                 PMD_SECT_AP_READ
 838         .long   PMD_TYPE_SECT | \
 839                 PMD_SECT_AP_WRITE | \
 840                 PMD_SECT_AP_READ
 841         b       __xscale_setup
 842         .long   cpu_arch_name
 843         .long   cpu_elf_name
 844         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 845         .long   cpu_ixp42x_name
 846         .long   xscale_processor_functions
 847         .long   v4wbi_tlb_fns
 848         .long   xscale_mc_user_fns
 849         .long   xscale_cache_fns
 850         .size   __ixp42x_proc_info, . - __ixp42x_proc_info
 851
 852         .type   __ixp43x_proc_info, #object
 853 __ixp43x_proc_info:
 854         .long   0x69054040
 855         .long   0xfffffff0
 856         .long   PMD_TYPE_SECT | \
 857                 PMD_SECT_BUFFERABLE | \
 858                 PMD_SECT_CACHEABLE | \
 859                 PMD_SECT_AP_WRITE | \
 860                 PMD_SECT_AP_READ
 861         .long   PMD_TYPE_SECT | \
 862                 PMD_SECT_AP_WRITE | \
 863                 PMD_SECT_AP_READ
 864         b       __xscale_setup
 865         .long   cpu_arch_name
 866         .long   cpu_elf_name
 867         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 868         .long   cpu_ixp43x_name
 869         .long   xscale_processor_functions
 870         .long   v4wbi_tlb_fns
 871         .long   xscale_mc_user_fns
 872         .long   xscale_cache_fns
 873         .size   __ixp43x_proc_info, . - __ixp43x_proc_info
 874
 875         .type   __ixp46x_proc_info, #object
 876 __ixp46x_proc_info:
 877         .long   0x69054200
 878         .long   0xffffff00
 879         .long   PMD_TYPE_SECT | \
 880                 PMD_SECT_BUFFERABLE | \
 881                 PMD_SECT_CACHEABLE | \
 882                 PMD_SECT_AP_WRITE | \
 883                 PMD_SECT_AP_READ
 884         .long   PMD_TYPE_SECT | \
 885                 PMD_SECT_AP_WRITE | \
 886                 PMD_SECT_AP_READ
 887         b       __xscale_setup
 888         .long   cpu_arch_name
 889         .long   cpu_elf_name
 890         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 891         .long   cpu_ixp46x_name
 892         .long   xscale_processor_functions
 893         .long   v4wbi_tlb_fns
 894         .long   xscale_mc_user_fns
 895         .long   xscale_cache_fns
 896         .size   __ixp46x_proc_info, . - __ixp46x_proc_info
 897
 898         .type   __pxa255_proc_info,#object
 899 __pxa255_proc_info:
 900         .long   0x69052d00
 901         .long   0xfffffff0
 902         .long   PMD_TYPE_SECT | \
 903                 PMD_SECT_BUFFERABLE | \
 904                 PMD_SECT_CACHEABLE | \
 905                 PMD_SECT_AP_WRITE | \
 906                 PMD_SECT_AP_READ
 907         .long   PMD_TYPE_SECT | \
 908                 PMD_SECT_AP_WRITE | \
 909                 PMD_SECT_AP_READ
 910         b       __xscale_setup
 911         .long   cpu_arch_name
 912         .long   cpu_elf_name
 913         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 914         .long   cpu_pxa255_name
 915         .long   xscale_processor_functions
 916         .long   v4wbi_tlb_fns
 917         .long   xscale_mc_user_fns
 918         .long   xscale_cache_fns
 919         .size   __pxa255_proc_info, . - __pxa255_proc_info
 920
 921         .type   __pxa270_proc_info,#object
 922 __pxa270_proc_info:
 923         .long   0x69054110
 924         .long   0xfffffff0
 925         .long   PMD_TYPE_SECT | \
 926                 PMD_SECT_BUFFERABLE | \
 927                 PMD_SECT_CACHEABLE | \
 928                 PMD_SECT_AP_WRITE | \
 929                 PMD_SECT_AP_READ
 930         .long   PMD_TYPE_SECT | \
 931                 PMD_SECT_AP_WRITE | \
 932                 PMD_SECT_AP_READ
 933         b       __xscale_setup
 934         .long   cpu_arch_name
 935         .long   cpu_elf_name
 936         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 937         .long   cpu_pxa270_name
 938         .long   xscale_processor_functions
 939         .long   v4wbi_tlb_fns
 940         .long   xscale_mc_user_fns
 941         .long   xscale_cache_fns
 942         .size   __pxa270_proc_info, . - __pxa270_proc_info
 943