2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/linkage.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
17 #include <asm/pgtable.h>
19 #include "proc-macros.S"
21 #define TTB_C (1 << 0)
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_OC_WT (2 << 3)
24 #define TTB_RGN_OC_WB (3 << 3)
26 ENTRY(cpu_v7_proc_init)
29 ENTRY(cpu_v7_proc_fin)
35 * Perform a soft reset of the system. Put the CPU into the
36 * same state as it would be if it had been reset, and branch
37 * to what would be the reset vector.
39 * - loc - location to jump to for soft reset
50 * Idle the processor (eg, wait for interrupt).
52 * IRQs are already disabled.
55 .long 0xe320f003 @ ARM V7 WFI instruction
58 ENTRY(cpu_v7_dcache_clean_area)
59 #ifndef TLB_CAN_READ_FROM_L1_CACHE
60 dcache_line_size r2, r3
61 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
70 * cpu_v7_switch_mm(pgd_phys, tsk)
72 * Set the translation table base pointer to be pgd_phys
74 * - pgd_phys - physical address of new TTB
77 * - we are not using split page tables
79 ENTRY(cpu_v7_switch_mm)
82 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
83 orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
84 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
86 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
88 mcr p15, 0, r1, c13, c0, 1 @ set context ID
94 * cpu_v7_set_pte_ext(ptep, pte)
96 * Set a level 2 translation table entry.
98 * - ptep - pointer to level 2 translation table entry
99 * (hardware version is stored at -1024 bytes)
100 * - pte - PTE value to store
101 * - ext - value for extended PTE bits
103 ENTRY(cpu_v7_set_pte_ext)
105 str r1, [r0], #-2048 @ linux version
107 bic r3, r1, #0x000003f0
108 bic r3, r3, #PTE_TYPE_MASK
110 orr r3, r3, #PTE_EXT_AP0 | 2
113 orrne r3, r3, #PTE_EXT_TEX(1)
116 tstne r1, #L_PTE_DIRTY
117 orreq r3, r3, #PTE_EXT_APX
120 orrne r3, r3, #PTE_EXT_AP1
121 tstne r3, #PTE_EXT_APX
122 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
125 orreq r3, r3, #PTE_EXT_XN
128 tstne r1, #L_PTE_PRESENT
132 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
137 .ascii "ARMv7 Processor"
140 .section ".text.init", #alloc, #execinstr
145 * Initialise TLB, Caches, and MMU state ready to switch the MMU
146 * on. Return in r0 the new CP15 C1 control register setting.
148 * We automatically detect if we have a Harvard cache, and use the
149 * Harvard cache control instructions insead of the unified cache
150 * control instructions.
152 * This should be able to cover all ARMv7 cores.
154 * It is assumed that:
155 * - cache type register is implemented
158 adr r12, __v7_setup_stack @ the local stack
159 stmia r12, {r0-r5, r7, r9, r11, lr}
160 bl v7_flush_dcache_all
161 ldmia r12, {r0-r5, r7, r9, r11, lr}
164 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
168 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
169 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
170 orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
171 mcr p15, 0, r4, c2, c0, 0 @ load TTB0
172 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
173 mov r10, #0x1f @ domains 0, 1 = manager
174 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
178 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
179 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
182 mrc p15, 0, r0, c1, c0, 0 @ read control register
183 bic r0, r0, r5 @ clear bits them
184 orr r0, r0, r6 @ set them
185 mov pc, lr @ return to head.S:__ret
189 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
190 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
191 * 0 110 0011 1.00 .111 1101 < we want
193 .type v7_crval, #object
195 crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
198 .space 4 * 11 @ 11 registers
200 .type v7_processor_functions, #object
201 ENTRY(v7_processor_functions)
204 .word cpu_v7_proc_init
205 .word cpu_v7_proc_fin
208 .word cpu_v7_dcache_clean_area
209 .word cpu_v7_switch_mm
210 .word cpu_v7_set_pte_ext
211 .size v7_processor_functions, . - v7_processor_functions
213 .type cpu_arch_name, #object
216 .size cpu_arch_name, . - cpu_arch_name
218 .type cpu_elf_name, #object
221 .size cpu_elf_name, . - cpu_elf_name
224 .section ".proc.info.init", #alloc, #execinstr
227 * Match any ARMv7 processor core.
229 .type __v7_proc_info, #object
231 .long 0x000f0000 @ Required ID value
232 .long 0x000f0000 @ Mask for ID
233 .long PMD_TYPE_SECT | \
234 PMD_SECT_BUFFERABLE | \
235 PMD_SECT_CACHEABLE | \
236 PMD_SECT_AP_WRITE | \
238 .long PMD_TYPE_SECT | \
240 PMD_SECT_AP_WRITE | \
245 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
247 .long v7_processor_functions
251 .size __v7_proc_info, . - __v7_proc_info