2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv6 processor support.
12 #include <linux/linkage.h>
13 #include <asm/assembler.h>
14 #include <asm/constants.h>
15 #include <asm/procinfo.h>
16 #include <asm/pgtable.h>
18 #include "proc-macros.S"
20 #define D_CACHE_LINE_SIZE 32
54 ENTRY(cpu_v6_proc_init)
57 ENTRY(cpu_v6_proc_fin)
63 * Perform a soft reset of the system. Put the CPU into the
64 * same state as it would be if it had been reset, and branch
65 * to what would be the reset vector.
67 * - loc - location to jump to for soft reset
78 * Idle the processor (eg, wait for interrupt).
80 * IRQs are already disabled.
83 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
86 ENTRY(cpu_v6_dcache_clean_area)
87 #ifndef TLB_CAN_READ_FROM_L1_CACHE
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, #D_CACHE_LINE_SIZE
90 subs r1, r1, #D_CACHE_LINE_SIZE
96 * cpu_arm926_switch_mm(pgd_phys, tsk)
98 * Set the translation table base pointer to be pgd_phys
100 * - pgd_phys - physical address of new TTB
102 * It is assumed that:
103 * - we are not using split page tables
105 ENTRY(cpu_v6_switch_mm)
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
109 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
110 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
115 * cpu_v6_set_pte(ptep, pte)
117 * Set a level 2 translation table entry.
119 * - ptep - pointer to level 2 translation table entry
120 * (hardware version is stored at -1024 bytes)
121 * - pte - PTE value to store
124 * YUWD APX AP1 AP0 SVC User
125 * 0xxx 0 0 0 no acc no acc
126 * 10x0 1 0 1 r/o no acc
127 * 1001 0 0 1 r/w no acc
128 * 1011 0 0 1 r/w no acc
133 ENTRY(cpu_v6_set_pte)
134 str r1, [r0], #-2048 @ linux version
136 bic r2, r1, #0x000007f0
137 bic r2, r2, #0x00000003
138 orr r2, r2, #PTE_EXT_AP0 | 2
141 orreq r2, r2, #PTE_EXT_APX
144 orrne r2, r2, #PTE_EXT_AP1
145 bicne r2, r2, #PTE_EXT_AP0
146 tstne r1, #L_PTE_WRITE
147 tstne r1, #L_PTE_DIRTY
148 eorne r2, r2, #PTE_EXT_AP0
151 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
153 @ tst r1, #L_PTE_EXEC
154 @ orreq r2, r2, #PTE_EXT_XN
156 tst r1, #L_PTE_PRESENT
160 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
167 .asciz "Some Random V6 Processor"
170 .section ".text.init", #alloc, #execinstr
175 * Initialise TLB, Caches, and MMU state ready to switch the MMU
176 * on. Return in r0 the new CP15 C1 control register setting.
178 * We automatically detect if we have a Harvard cache, and use the
179 * Harvard cache control instructions insead of the unified cache
180 * control instructions.
182 * This should be able to cover all ARMv6 cores.
184 * It is assumed that:
185 * - cache type register is implemented
189 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
190 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
191 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
192 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
193 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
194 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
195 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
197 mrc p15, 0, r0, c1, c0, 2
198 orr r0, r0, #(0xf << 20)
199 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
201 mrc p15, 0, r0, c1, c0, 0 @ read control register
202 ldr r5, v6_cr1_clear @ get mask for bits to clear
203 bic r0, r0, r5 @ clear bits them
204 ldr r5, v6_cr1_set @ get mask for bits to set
205 orr r0, r0, r5 @ set them
206 mov pc, lr @ return to head.S:__ret
210 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
211 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
212 * 0 110 0011 1.00 .111 1101 < we want
214 .type v6_cr1_clear, #object
215 .type v6_cr1_set, #object
221 .type v6_processor_functions, #object
222 ENTRY(v6_processor_functions)
224 .word cpu_v6_proc_init
225 .word cpu_v6_proc_fin
228 .word cpu_v6_dcache_clean_area
229 .word cpu_v6_switch_mm
231 .size v6_processor_functions, . - v6_processor_functions
233 .type cpu_arch_name, #object
236 .size cpu_arch_name, . - cpu_arch_name
238 .type cpu_elf_name, #object
241 .size cpu_elf_name, . - cpu_elf_name
244 .section ".proc.info", #alloc, #execinstr
247 * Match any ARMv6 processor core.
249 .type __v6_proc_info, #object
253 .long PMD_TYPE_SECT | \
254 PMD_SECT_BUFFERABLE | \
255 PMD_SECT_CACHEABLE | \
256 PMD_SECT_AP_WRITE | \
261 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
263 .long v6_processor_functions
267 .size __v6_proc_info, . - __v6_proc_info