2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/setup.h>
21 #include <asm/sizes.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
29 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
32 * empty_zero_page is a special page that is used for
33 * zero-initialized data and COW.
35 struct page *empty_zero_page;
36 EXPORT_SYMBOL(empty_zero_page);
39 * The pmd table for the upper-most set of pages.
43 #define CPOLICY_UNCACHED 0
44 #define CPOLICY_BUFFERED 1
45 #define CPOLICY_WRITETHROUGH 2
46 #define CPOLICY_WRITEBACK 3
47 #define CPOLICY_WRITEALLOC 4
49 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
50 static unsigned int ecc_mask __initdata = 0;
52 pgprot_t pgprot_kernel;
54 EXPORT_SYMBOL(pgprot_user);
55 EXPORT_SYMBOL(pgprot_kernel);
58 const char policy[16];
64 static struct cachepolicy cache_policies[] __initdata = {
68 .pmd = PMD_SECT_UNCACHED,
69 .pte = L_PTE_MT_UNCACHED,
73 .pmd = PMD_SECT_BUFFERED,
74 .pte = L_PTE_MT_BUFFERABLE,
76 .policy = "writethrough",
79 .pte = L_PTE_MT_WRITETHROUGH,
81 .policy = "writeback",
84 .pte = L_PTE_MT_WRITEBACK,
86 .policy = "writealloc",
89 .pte = L_PTE_MT_WRITEALLOC,
94 * These are useful for identifying cache coherency
95 * problems by allowing the cache or the cache and
96 * writebuffer to be turned off. (Note: the write
97 * buffer should not be on and the cache off).
99 static void __init early_cachepolicy(char **p)
103 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
104 int len = strlen(cache_policies[i].policy);
106 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
108 cr_alignment &= ~cache_policies[i].cr_mask;
109 cr_no_alignment &= ~cache_policies[i].cr_mask;
114 if (i == ARRAY_SIZE(cache_policies))
115 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
116 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
117 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
118 cachepolicy = CPOLICY_WRITEBACK;
121 set_cr(cr_alignment);
123 __early_param("cachepolicy=", early_cachepolicy);
125 static void __init early_nocache(char **__unused)
127 char *p = "buffered";
128 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
129 early_cachepolicy(&p);
131 __early_param("nocache", early_nocache);
133 static void __init early_nowrite(char **__unused)
135 char *p = "uncached";
136 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
137 early_cachepolicy(&p);
139 __early_param("nowb", early_nowrite);
141 static void __init early_ecc(char **p)
143 if (memcmp(*p, "on", 2) == 0) {
144 ecc_mask = PMD_PROTECTION;
146 } else if (memcmp(*p, "off", 3) == 0) {
151 __early_param("ecc=", early_ecc);
153 static int __init noalign_setup(char *__unused)
155 cr_alignment &= ~CR_A;
156 cr_no_alignment &= ~CR_A;
157 set_cr(cr_alignment);
160 __setup("noalign", noalign_setup);
163 void adjust_cr(unsigned long mask, unsigned long set)
171 local_irq_save(flags);
173 cr_no_alignment = (cr_no_alignment & ~mask) | set;
174 cr_alignment = (cr_alignment & ~mask) | set;
176 set_cr((get_cr() & ~mask) | set);
178 local_irq_restore(flags);
182 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
183 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
185 static struct mem_type mem_types[] = {
186 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
187 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
189 .prot_l1 = PMD_TYPE_TABLE,
190 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
193 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
194 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
195 .prot_l1 = PMD_TYPE_TABLE,
196 .prot_sect = PROT_SECT_DEVICE,
199 [MT_DEVICE_CACHED] = { /* ioremap_cached */
200 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
205 [MT_DEVICE_WC] = { /* ioremap_wc */
206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE,
212 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
213 .domain = DOMAIN_KERNEL,
216 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
217 .domain = DOMAIN_KERNEL,
220 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
222 .prot_l1 = PMD_TYPE_TABLE,
223 .domain = DOMAIN_USER,
225 [MT_HIGH_VECTORS] = {
226 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
227 L_PTE_USER | L_PTE_EXEC,
228 .prot_l1 = PMD_TYPE_TABLE,
229 .domain = DOMAIN_USER,
232 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
233 .domain = DOMAIN_KERNEL,
236 .prot_sect = PMD_TYPE_SECT,
237 .domain = DOMAIN_KERNEL,
240 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED,
241 .domain = DOMAIN_KERNEL,
245 const struct mem_type *get_mem_type(unsigned int type)
247 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
251 * Adjust the PMD section entries according to the CPU in use.
253 static void __init build_mem_type_table(void)
255 struct cachepolicy *cp;
256 unsigned int cr = get_cr();
257 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
258 int cpu_arch = cpu_architecture();
261 if (cpu_arch < CPU_ARCH_ARMv6) {
262 #if defined(CONFIG_CPU_DCACHE_DISABLE)
263 if (cachepolicy > CPOLICY_BUFFERED)
264 cachepolicy = CPOLICY_BUFFERED;
265 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
266 if (cachepolicy > CPOLICY_WRITETHROUGH)
267 cachepolicy = CPOLICY_WRITETHROUGH;
270 if (cpu_arch < CPU_ARCH_ARMv5) {
271 if (cachepolicy >= CPOLICY_WRITEALLOC)
272 cachepolicy = CPOLICY_WRITEBACK;
276 cachepolicy = CPOLICY_WRITEALLOC;
280 * Strip out features not present on earlier architectures.
281 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
282 * without extended page tables don't have the 'Shared' bit.
284 if (cpu_arch < CPU_ARCH_ARMv5)
285 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
286 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
287 if (cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP))
288 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
289 mem_types[i].prot_sect &= ~PMD_SECT_S;
292 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
293 * "update-able on write" bit on ARM610). However, Xscale and
294 * Xscale3 require this bit to be cleared.
296 if (cpu_is_xscale() || cpu_is_xsc3()) {
297 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
298 mem_types[i].prot_sect &= ~PMD_BIT4;
299 mem_types[i].prot_l1 &= ~PMD_BIT4;
301 } else if (cpu_arch < CPU_ARCH_ARMv6) {
302 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
303 if (mem_types[i].prot_l1)
304 mem_types[i].prot_l1 |= PMD_BIT4;
305 if (mem_types[i].prot_sect)
306 mem_types[i].prot_sect |= PMD_BIT4;
311 * Mark the device areas according to the CPU/architecture.
313 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
314 if (!cpu_is_xsc3()) {
316 * Mark device regions on ARMv6+ as execute-never
317 * to prevent speculative instruction fetches.
319 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
320 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
321 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
322 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
324 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
326 * For ARMv7 with TEX remapping,
327 * - shared device is SXCB=1100
328 * - nonshared device is SXCB=0100
329 * - write combine device mem is SXCB=0001
330 * (Uncached Normal memory)
332 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
333 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
334 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
337 * For Xscale3, ARMv6 and ARMv7 without TEX remapping,
338 * - shared device is TEXCB=00001
339 * - nonshared device is TEXCB=01000
340 * - write combine device mem is TEXCB=00100
341 * (Inner/Outer Uncacheable in xsc3 parlance, Uncached
342 * Normal in ARMv6 parlance).
344 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
345 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
346 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
350 * On others, write combining is "Uncached/Buffered"
352 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
356 * Now deal with the memory-type mappings
358 cp = &cache_policies[cachepolicy];
359 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
363 * Only use write-through for non-SMP systems
365 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
366 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
370 * Enable CPU-specific coherency if supported.
371 * (Only available on XSC3 at the moment.)
373 if (arch_is_coherent() && cpu_is_xsc3())
374 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
377 * ARMv6 and above have extended page tables.
379 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
381 * Mark cache clean areas and XIP ROM read only
382 * from SVC mode and no access from userspace.
384 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
385 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
386 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
390 * Mark memory with the "shared" attribute for SMP systems
392 user_pgprot |= L_PTE_SHARED;
393 kern_pgprot |= L_PTE_SHARED;
394 vecs_pgprot |= L_PTE_SHARED;
395 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
399 for (i = 0; i < 16; i++) {
400 unsigned long v = pgprot_val(protection_map[i]);
401 protection_map[i] = __pgprot(v | user_pgprot);
404 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
405 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
407 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
408 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
409 L_PTE_DIRTY | L_PTE_WRITE |
410 L_PTE_EXEC | kern_pgprot);
412 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
413 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
414 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
415 mem_types[MT_ROM].prot_sect |= cp->pmd;
419 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
423 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
426 printk("Memory policy: ECC %sabled, Data cache %s\n",
427 ecc_mask ? "en" : "dis", cp->policy);
429 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
430 struct mem_type *t = &mem_types[i];
432 #define T(n) if (i == (n)) s = #n;
435 T(MT_DEVICE_NONSHARED);
444 printk(KERN_INFO "%-19s: DOM=%#3x S=%#010x L1=%#010x P=%#010x\n",
445 s, t->domain, t->prot_sect, t->prot_l1, t->prot_pte);
448 t->prot_l1 |= PMD_DOMAIN(t->domain);
450 t->prot_sect |= PMD_DOMAIN(t->domain);
454 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
456 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
457 unsigned long end, unsigned long pfn,
458 const struct mem_type *type)
462 if (pmd_none(*pmd)) {
463 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
464 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
467 pte = pte_offset_kernel(pmd, addr);
469 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
471 } while (pte++, addr += PAGE_SIZE, addr != end);
474 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
475 unsigned long end, unsigned long phys,
476 const struct mem_type *type)
478 pmd_t *pmd = pmd_offset(pgd, addr);
481 * Try a section mapping - end, addr and phys must all be aligned
482 * to a section boundary. Note that PMDs refer to the individual
483 * L1 entries, whereas PGDs refer to a group of L1 entries making
484 * up one logical pointer to an L2 table.
486 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
489 if (addr & SECTION_SIZE)
493 *pmd = __pmd(phys | type->prot_sect);
494 phys += SECTION_SIZE;
495 } while (pmd++, addr += SECTION_SIZE, addr != end);
500 * No need to loop; pte's aren't interested in the
501 * individual L1 entries.
503 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
507 static void __init create_36bit_mapping(struct map_desc *md,
508 const struct mem_type *type)
510 unsigned long phys, addr, length, end;
514 phys = (unsigned long)__pfn_to_phys(md->pfn);
515 length = PAGE_ALIGN(md->length);
517 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
518 printk(KERN_ERR "MM: CPU does not support supersection "
519 "mapping for 0x%08llx at 0x%08lx\n",
520 __pfn_to_phys((u64)md->pfn), addr);
524 /* N.B. ARMv6 supersections are only defined to work with domain 0.
525 * Since domain assignments can in fact be arbitrary, the
526 * 'domain == 0' check below is required to insure that ARMv6
527 * supersections are only allocated for domain 0 regardless
528 * of the actual domain assignments in use.
531 printk(KERN_ERR "MM: invalid domain in supersection "
532 "mapping for 0x%08llx at 0x%08lx\n",
533 __pfn_to_phys((u64)md->pfn), addr);
537 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
538 printk(KERN_ERR "MM: cannot create mapping for "
539 "0x%08llx at 0x%08lx invalid alignment\n",
540 __pfn_to_phys((u64)md->pfn), addr);
545 * Shift bits [35:32] of address into bits [23:20] of PMD
548 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
550 pgd = pgd_offset_k(addr);
553 pmd_t *pmd = pmd_offset(pgd, addr);
556 for (i = 0; i < 16; i++)
557 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
559 addr += SUPERSECTION_SIZE;
560 phys += SUPERSECTION_SIZE;
561 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
562 } while (addr != end);
566 * Create the page directory entries and any necessary
567 * page tables for the mapping specified by `md'. We
568 * are able to cope here with varying sizes and address
569 * offsets, and we take full advantage of sections and
572 void __init create_mapping(struct map_desc *md)
574 unsigned long phys, addr, length, end;
575 const struct mem_type *type;
578 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
579 printk(KERN_WARNING "BUG: not creating mapping for "
580 "0x%08llx at 0x%08lx in user region\n",
581 __pfn_to_phys((u64)md->pfn), md->virtual);
585 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
586 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
587 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
588 "overlaps vmalloc space\n",
589 __pfn_to_phys((u64)md->pfn), md->virtual);
592 type = &mem_types[md->type];
595 * Catch 36-bit addresses
597 if (md->pfn >= 0x100000) {
598 create_36bit_mapping(md, type);
602 addr = md->virtual & PAGE_MASK;
603 phys = (unsigned long)__pfn_to_phys(md->pfn);
604 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
606 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
607 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
608 "be mapped using pages, ignoring.\n",
609 __pfn_to_phys(md->pfn), addr);
613 pgd = pgd_offset_k(addr);
616 unsigned long next = pgd_addr_end(addr, end);
618 alloc_init_section(pgd, addr, next, phys, type);
622 } while (pgd++, addr != end);
626 * Create the architecture specific mappings
628 void __init iotable_init(struct map_desc *io_desc, int nr)
632 for (i = 0; i < nr; i++)
633 create_mapping(io_desc + i);
636 static unsigned long __initdata vmalloc_reserve = SZ_128M;
639 * vmalloc=size forces the vmalloc area to be exactly 'size'
640 * bytes. This can be used to increase (or decrease) the vmalloc
641 * area - the default is 128m.
643 static void __init early_vmalloc(char **arg)
645 vmalloc_reserve = memparse(*arg, arg);
647 if (vmalloc_reserve < SZ_16M) {
648 vmalloc_reserve = SZ_16M;
650 "vmalloc area too small, limiting to %luMB\n",
651 vmalloc_reserve >> 20);
654 __early_param("vmalloc=", early_vmalloc);
656 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
658 static int __init check_membank_valid(struct membank *mb)
661 * Check whether this memory region has non-zero size or
662 * invalid node number.
664 if (mb->size == 0 || mb->node >= MAX_NUMNODES)
668 * Check whether this memory region would entirely overlap
671 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
672 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
673 "(vmalloc region overlap).\n",
674 mb->start, mb->start + mb->size - 1);
679 * Check whether this memory region would partially overlap
682 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
683 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
684 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
686 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
687 "to -%.8lx (vmalloc region overlap).\n",
688 mb->start, mb->start + mb->size - 1,
689 mb->start + newsize - 1);
696 static void __init sanity_check_meminfo(struct meminfo *mi)
700 for (i = 0, j = 0; i < mi->nr_banks; i++) {
701 if (check_membank_valid(&mi->bank[i]))
702 mi->bank[j++] = mi->bank[i];
707 static inline void prepare_page_table(struct meminfo *mi)
712 * Clear out all the mappings below the kernel image.
714 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
715 pmd_clear(pmd_off_k(addr));
717 #ifdef CONFIG_XIP_KERNEL
718 /* The XIP kernel is mapped in the module area -- skip over it */
719 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
721 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
722 pmd_clear(pmd_off_k(addr));
725 * Clear out all the kernel space mappings, except for the first
726 * memory bank, up to the end of the vmalloc region.
728 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
729 addr < VMALLOC_END; addr += PGDIR_SIZE)
730 pmd_clear(pmd_off_k(addr));
734 * Reserve the various regions of node 0
736 void __init reserve_node_zero(pg_data_t *pgdat)
738 unsigned long res_size = 0;
741 * Register the kernel text and data with bootmem.
742 * Note that this can only be in node 0.
744 #ifdef CONFIG_XIP_KERNEL
745 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
748 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
753 * Reserve the page tables. These are already in use,
754 * and can only be in node 0.
756 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
757 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
760 * Hmm... This should go elsewhere, but we really really need to
761 * stop things allocating the low memory; ideally we need a better
762 * implementation of GFP_DMA which does not assume that DMA-able
763 * memory starts at zero.
765 if (machine_is_integrator() || machine_is_cintegrator())
766 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
769 * These should likewise go elsewhere. They pre-reserve the
770 * screen memory region at the start of main system memory.
772 if (machine_is_edb7211())
773 res_size = 0x00020000;
774 if (machine_is_p720t())
775 res_size = 0x00014000;
777 /* H1940 and RX3715 need to reserve this for suspend */
779 if (machine_is_h1940() || machine_is_rx3715()) {
780 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
782 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
788 * Because of the SA1111 DMA bug, we want to preserve our
789 * precious DMA-able memory...
791 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
794 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
799 * Set up device the mappings. Since we clear out the page tables for all
800 * mappings above VMALLOC_END, we will remove any debug device mappings.
801 * This means you have to be careful how you debug this function, or any
802 * called function. This means you can't use any function or debugging
803 * method which may touch any device, otherwise the kernel _will_ crash.
805 static void __init devicemaps_init(struct machine_desc *mdesc)
812 * Allocate the vector page early.
814 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
817 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
818 pmd_clear(pmd_off_k(addr));
821 * Map the kernel if it is XIP.
822 * It is always first in the modulearea.
824 #ifdef CONFIG_XIP_KERNEL
825 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
826 map.virtual = MODULE_START;
827 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
829 create_mapping(&map);
833 * Map the cache flushing regions.
836 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
837 map.virtual = FLUSH_BASE;
839 map.type = MT_CACHECLEAN;
840 create_mapping(&map);
842 #ifdef FLUSH_BASE_MINICACHE
843 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
844 map.virtual = FLUSH_BASE_MINICACHE;
846 map.type = MT_MINICLEAN;
847 create_mapping(&map);
851 * Create a mapping for the machine vectors at the high-vectors
852 * location (0xffff0000). If we aren't using high-vectors, also
853 * create a mapping at the low-vectors virtual address.
855 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
856 map.virtual = 0xffff0000;
857 map.length = PAGE_SIZE;
858 map.type = MT_HIGH_VECTORS;
859 create_mapping(&map);
861 if (!vectors_high()) {
863 map.type = MT_LOW_VECTORS;
864 create_mapping(&map);
868 * Ask the machine support to map in the statically mapped devices.
874 * Finally flush the caches and tlb to ensure that we're in a
875 * consistent state wrt the writebuffer. This also ensures that
876 * any write-allocated cache lines in the vector page are written
877 * back. After this point, we can start to touch devices again.
879 local_flush_tlb_all();
884 * paging_init() sets up the page tables, initialises the zone memory
885 * maps, and sets up the zero page, bad page and bad page tables.
887 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
891 build_mem_type_table();
892 sanity_check_meminfo(mi);
893 prepare_page_table(mi);
895 devicemaps_init(mdesc);
897 top_pmd = pmd_off_k(0xffff0000);
900 * allocate the zero page. Note that we count on this going ok.
902 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
903 memzero(zero_page, PAGE_SIZE);
904 empty_zero_page = virt_to_page(zero_page);
905 flush_dcache_page(empty_zero_page);
909 * In order to soft-boot, we need to insert a 1:1 mapping in place of
910 * the user-mode pages. This will then ensure that we have predictable
911 * results when turning the mmu off
913 void setup_mm_for_reboot(char mode)
915 unsigned long base_pmdval;
919 if (current->mm && current->mm->pgd)
920 pgd = current->mm->pgd;
924 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
925 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
926 base_pmdval |= PMD_BIT4;
928 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
929 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
932 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
933 pmd[0] = __pmd(pmdval);
934 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
935 flush_pmd_entry(pmd);