2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/setup.h>
21 #include <asm/sizes.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
29 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
32 * empty_zero_page is a special page that is used for
33 * zero-initialized data and COW.
35 struct page *empty_zero_page;
36 EXPORT_SYMBOL(empty_zero_page);
39 * The pmd table for the upper-most set of pages.
43 #define CPOLICY_UNCACHED 0
44 #define CPOLICY_BUFFERED 1
45 #define CPOLICY_WRITETHROUGH 2
46 #define CPOLICY_WRITEBACK 3
47 #define CPOLICY_WRITEALLOC 4
49 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
50 static unsigned int ecc_mask __initdata = 0;
52 pgprot_t pgprot_kernel;
54 EXPORT_SYMBOL(pgprot_user);
55 EXPORT_SYMBOL(pgprot_kernel);
58 const char policy[16];
64 static struct cachepolicy cache_policies[] __initdata = {
68 .pmd = PMD_SECT_UNCACHED,
69 .pte = L_PTE_MT_UNCACHED,
73 .pmd = PMD_SECT_BUFFERED,
74 .pte = L_PTE_MT_BUFFERABLE,
76 .policy = "writethrough",
79 .pte = L_PTE_MT_WRITETHROUGH,
81 .policy = "writeback",
84 .pte = L_PTE_MT_WRITEBACK,
86 .policy = "writealloc",
89 .pte = L_PTE_MT_WRITEALLOC,
94 * These are useful for identifying cache coherency
95 * problems by allowing the cache or the cache and
96 * writebuffer to be turned off. (Note: the write
97 * buffer should not be on and the cache off).
99 static void __init early_cachepolicy(char **p)
103 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
104 int len = strlen(cache_policies[i].policy);
106 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
108 cr_alignment &= ~cache_policies[i].cr_mask;
109 cr_no_alignment &= ~cache_policies[i].cr_mask;
114 if (i == ARRAY_SIZE(cache_policies))
115 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
116 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
117 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
118 cachepolicy = CPOLICY_WRITEBACK;
121 set_cr(cr_alignment);
123 __early_param("cachepolicy=", early_cachepolicy);
125 static void __init early_nocache(char **__unused)
127 char *p = "buffered";
128 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
129 early_cachepolicy(&p);
131 __early_param("nocache", early_nocache);
133 static void __init early_nowrite(char **__unused)
135 char *p = "uncached";
136 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
137 early_cachepolicy(&p);
139 __early_param("nowb", early_nowrite);
141 static void __init early_ecc(char **p)
143 if (memcmp(*p, "on", 2) == 0) {
144 ecc_mask = PMD_PROTECTION;
146 } else if (memcmp(*p, "off", 3) == 0) {
151 __early_param("ecc=", early_ecc);
153 static int __init noalign_setup(char *__unused)
155 cr_alignment &= ~CR_A;
156 cr_no_alignment &= ~CR_A;
157 set_cr(cr_alignment);
160 __setup("noalign", noalign_setup);
163 void adjust_cr(unsigned long mask, unsigned long set)
171 local_irq_save(flags);
173 cr_no_alignment = (cr_no_alignment & ~mask) | set;
174 cr_alignment = (cr_alignment & ~mask) | set;
176 set_cr((get_cr() & ~mask) | set);
178 local_irq_restore(flags);
182 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
183 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
185 static struct mem_type mem_types[] = {
186 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
187 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
189 .prot_l1 = PMD_TYPE_TABLE,
190 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
193 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
194 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
195 .prot_l1 = PMD_TYPE_TABLE,
196 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
199 [MT_DEVICE_CACHED] = { /* ioremap_cached */
200 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
205 [MT_DEVICE_WC] = { /* ioremap_wc */
206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE,
212 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
213 .domain = DOMAIN_KERNEL,
216 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
217 .domain = DOMAIN_KERNEL,
220 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
222 .prot_l1 = PMD_TYPE_TABLE,
223 .domain = DOMAIN_USER,
225 [MT_HIGH_VECTORS] = {
226 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
227 L_PTE_USER | L_PTE_EXEC,
228 .prot_l1 = PMD_TYPE_TABLE,
229 .domain = DOMAIN_USER,
232 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
233 .domain = DOMAIN_KERNEL,
236 .prot_sect = PMD_TYPE_SECT,
237 .domain = DOMAIN_KERNEL,
240 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED,
241 .domain = DOMAIN_KERNEL,
245 const struct mem_type *get_mem_type(unsigned int type)
247 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
251 * Adjust the PMD section entries according to the CPU in use.
253 static void __init build_mem_type_table(void)
255 struct cachepolicy *cp;
256 unsigned int cr = get_cr();
257 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
258 int cpu_arch = cpu_architecture();
261 if (cpu_arch < CPU_ARCH_ARMv6) {
262 #if defined(CONFIG_CPU_DCACHE_DISABLE)
263 if (cachepolicy > CPOLICY_BUFFERED)
264 cachepolicy = CPOLICY_BUFFERED;
265 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
266 if (cachepolicy > CPOLICY_WRITETHROUGH)
267 cachepolicy = CPOLICY_WRITETHROUGH;
270 if (cpu_arch < CPU_ARCH_ARMv5) {
271 if (cachepolicy >= CPOLICY_WRITEALLOC)
272 cachepolicy = CPOLICY_WRITEBACK;
276 cachepolicy = CPOLICY_WRITEALLOC;
280 * On non-Xscale3 ARMv5-and-older systems, use CB=01
281 * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3
282 * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable
283 * in xsc3 parlance, Uncached Normal in ARMv6 parlance).
285 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
286 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
287 mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
291 * ARMv5 and lower, bit 4 must be set for page tables.
292 * (was: cache "update-able on write" bit on ARM610)
293 * However, Xscale cores require this bit to be cleared.
295 if (cpu_is_xscale()) {
296 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
297 mem_types[i].prot_sect &= ~PMD_BIT4;
298 mem_types[i].prot_l1 &= ~PMD_BIT4;
300 } else if (cpu_arch < CPU_ARCH_ARMv6) {
301 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
302 if (mem_types[i].prot_l1)
303 mem_types[i].prot_l1 |= PMD_BIT4;
304 if (mem_types[i].prot_sect)
305 mem_types[i].prot_sect |= PMD_BIT4;
309 cp = &cache_policies[cachepolicy];
310 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
314 * Only use write-through for non-SMP systems
316 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
317 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
321 * Enable CPU-specific coherency if supported.
322 * (Only available on XSC3 at the moment.)
324 if (arch_is_coherent()) {
326 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
327 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
332 * ARMv6 and above have extended page tables.
334 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
336 * Mark cache clean areas and XIP ROM read only
337 * from SVC mode and no access from userspace.
339 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
340 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
341 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
344 * Mark the device area as "shared device"
346 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
350 * Mark memory with the "shared" attribute for SMP systems
352 user_pgprot |= L_PTE_SHARED;
353 kern_pgprot |= L_PTE_SHARED;
354 vecs_pgprot |= L_PTE_SHARED;
355 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
359 for (i = 0; i < 16; i++) {
360 unsigned long v = pgprot_val(protection_map[i]);
361 protection_map[i] = __pgprot(v | user_pgprot);
364 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
365 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
367 if (cpu_arch < CPU_ARCH_ARMv5)
368 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
370 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
371 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
372 L_PTE_DIRTY | L_PTE_WRITE |
373 L_PTE_EXEC | kern_pgprot);
375 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
376 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
377 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
378 mem_types[MT_ROM].prot_sect |= cp->pmd;
382 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
386 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
389 printk("Memory policy: ECC %sabled, Data cache %s\n",
390 ecc_mask ? "en" : "dis", cp->policy);
392 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
393 struct mem_type *t = &mem_types[i];
395 t->prot_l1 |= PMD_DOMAIN(t->domain);
397 t->prot_sect |= PMD_DOMAIN(t->domain);
401 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
403 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
404 unsigned long end, unsigned long pfn,
405 const struct mem_type *type)
409 if (pmd_none(*pmd)) {
410 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
411 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
414 pte = pte_offset_kernel(pmd, addr);
416 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
418 } while (pte++, addr += PAGE_SIZE, addr != end);
421 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
422 unsigned long end, unsigned long phys,
423 const struct mem_type *type)
425 pmd_t *pmd = pmd_offset(pgd, addr);
428 * Try a section mapping - end, addr and phys must all be aligned
429 * to a section boundary. Note that PMDs refer to the individual
430 * L1 entries, whereas PGDs refer to a group of L1 entries making
431 * up one logical pointer to an L2 table.
433 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
436 if (addr & SECTION_SIZE)
440 *pmd = __pmd(phys | type->prot_sect);
441 phys += SECTION_SIZE;
442 } while (pmd++, addr += SECTION_SIZE, addr != end);
447 * No need to loop; pte's aren't interested in the
448 * individual L1 entries.
450 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
454 static void __init create_36bit_mapping(struct map_desc *md,
455 const struct mem_type *type)
457 unsigned long phys, addr, length, end;
461 phys = (unsigned long)__pfn_to_phys(md->pfn);
462 length = PAGE_ALIGN(md->length);
464 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
465 printk(KERN_ERR "MM: CPU does not support supersection "
466 "mapping for 0x%08llx at 0x%08lx\n",
467 __pfn_to_phys((u64)md->pfn), addr);
471 /* N.B. ARMv6 supersections are only defined to work with domain 0.
472 * Since domain assignments can in fact be arbitrary, the
473 * 'domain == 0' check below is required to insure that ARMv6
474 * supersections are only allocated for domain 0 regardless
475 * of the actual domain assignments in use.
478 printk(KERN_ERR "MM: invalid domain in supersection "
479 "mapping for 0x%08llx at 0x%08lx\n",
480 __pfn_to_phys((u64)md->pfn), addr);
484 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
485 printk(KERN_ERR "MM: cannot create mapping for "
486 "0x%08llx at 0x%08lx invalid alignment\n",
487 __pfn_to_phys((u64)md->pfn), addr);
492 * Shift bits [35:32] of address into bits [23:20] of PMD
495 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
497 pgd = pgd_offset_k(addr);
500 pmd_t *pmd = pmd_offset(pgd, addr);
503 for (i = 0; i < 16; i++)
504 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
506 addr += SUPERSECTION_SIZE;
507 phys += SUPERSECTION_SIZE;
508 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
509 } while (addr != end);
513 * Create the page directory entries and any necessary
514 * page tables for the mapping specified by `md'. We
515 * are able to cope here with varying sizes and address
516 * offsets, and we take full advantage of sections and
519 void __init create_mapping(struct map_desc *md)
521 unsigned long phys, addr, length, end;
522 const struct mem_type *type;
525 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
526 printk(KERN_WARNING "BUG: not creating mapping for "
527 "0x%08llx at 0x%08lx in user region\n",
528 __pfn_to_phys((u64)md->pfn), md->virtual);
532 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
533 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
534 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
535 "overlaps vmalloc space\n",
536 __pfn_to_phys((u64)md->pfn), md->virtual);
539 type = &mem_types[md->type];
542 * Catch 36-bit addresses
544 if (md->pfn >= 0x100000) {
545 create_36bit_mapping(md, type);
549 addr = md->virtual & PAGE_MASK;
550 phys = (unsigned long)__pfn_to_phys(md->pfn);
551 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
553 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
554 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
555 "be mapped using pages, ignoring.\n",
556 __pfn_to_phys(md->pfn), addr);
560 pgd = pgd_offset_k(addr);
563 unsigned long next = pgd_addr_end(addr, end);
565 alloc_init_section(pgd, addr, next, phys, type);
569 } while (pgd++, addr != end);
573 * Create the architecture specific mappings
575 void __init iotable_init(struct map_desc *io_desc, int nr)
579 for (i = 0; i < nr; i++)
580 create_mapping(io_desc + i);
583 static unsigned long __initdata vmalloc_reserve = SZ_128M;
586 * vmalloc=size forces the vmalloc area to be exactly 'size'
587 * bytes. This can be used to increase (or decrease) the vmalloc
588 * area - the default is 128m.
590 static void __init early_vmalloc(char **arg)
592 vmalloc_reserve = memparse(*arg, arg);
594 if (vmalloc_reserve < SZ_16M) {
595 vmalloc_reserve = SZ_16M;
597 "vmalloc area too small, limiting to %luMB\n",
598 vmalloc_reserve >> 20);
601 __early_param("vmalloc=", early_vmalloc);
603 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
605 static int __init check_membank_valid(struct membank *mb)
608 * Check whether this memory region has non-zero size or
609 * invalid node number.
611 if (mb->size == 0 || mb->node >= MAX_NUMNODES)
615 * Check whether this memory region would entirely overlap
618 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
619 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
620 "(vmalloc region overlap).\n",
621 mb->start, mb->start + mb->size - 1);
626 * Check whether this memory region would partially overlap
629 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
630 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
631 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
633 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
634 "to -%.8lx (vmalloc region overlap).\n",
635 mb->start, mb->start + mb->size - 1,
636 mb->start + newsize - 1);
643 static void __init sanity_check_meminfo(struct meminfo *mi)
647 for (i = 0, j = 0; i < mi->nr_banks; i++) {
648 if (check_membank_valid(&mi->bank[i]))
649 mi->bank[j++] = mi->bank[i];
654 static inline void prepare_page_table(struct meminfo *mi)
659 * Clear out all the mappings below the kernel image.
661 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
662 pmd_clear(pmd_off_k(addr));
664 #ifdef CONFIG_XIP_KERNEL
665 /* The XIP kernel is mapped in the module area -- skip over it */
666 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
668 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
669 pmd_clear(pmd_off_k(addr));
672 * Clear out all the kernel space mappings, except for the first
673 * memory bank, up to the end of the vmalloc region.
675 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
676 addr < VMALLOC_END; addr += PGDIR_SIZE)
677 pmd_clear(pmd_off_k(addr));
681 * Reserve the various regions of node 0
683 void __init reserve_node_zero(pg_data_t *pgdat)
685 unsigned long res_size = 0;
688 * Register the kernel text and data with bootmem.
689 * Note that this can only be in node 0.
691 #ifdef CONFIG_XIP_KERNEL
692 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
695 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
700 * Reserve the page tables. These are already in use,
701 * and can only be in node 0.
703 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
704 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
707 * Hmm... This should go elsewhere, but we really really need to
708 * stop things allocating the low memory; ideally we need a better
709 * implementation of GFP_DMA which does not assume that DMA-able
710 * memory starts at zero.
712 if (machine_is_integrator() || machine_is_cintegrator())
713 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
716 * These should likewise go elsewhere. They pre-reserve the
717 * screen memory region at the start of main system memory.
719 if (machine_is_edb7211())
720 res_size = 0x00020000;
721 if (machine_is_p720t())
722 res_size = 0x00014000;
724 /* H1940 and RX3715 need to reserve this for suspend */
726 if (machine_is_h1940() || machine_is_rx3715()) {
727 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
729 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
735 * Because of the SA1111 DMA bug, we want to preserve our
736 * precious DMA-able memory...
738 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
741 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
746 * Set up device the mappings. Since we clear out the page tables for all
747 * mappings above VMALLOC_END, we will remove any debug device mappings.
748 * This means you have to be careful how you debug this function, or any
749 * called function. This means you can't use any function or debugging
750 * method which may touch any device, otherwise the kernel _will_ crash.
752 static void __init devicemaps_init(struct machine_desc *mdesc)
759 * Allocate the vector page early.
761 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
764 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
765 pmd_clear(pmd_off_k(addr));
768 * Map the kernel if it is XIP.
769 * It is always first in the modulearea.
771 #ifdef CONFIG_XIP_KERNEL
772 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
773 map.virtual = MODULE_START;
774 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
776 create_mapping(&map);
780 * Map the cache flushing regions.
783 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
784 map.virtual = FLUSH_BASE;
786 map.type = MT_CACHECLEAN;
787 create_mapping(&map);
789 #ifdef FLUSH_BASE_MINICACHE
790 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
791 map.virtual = FLUSH_BASE_MINICACHE;
793 map.type = MT_MINICLEAN;
794 create_mapping(&map);
798 * Create a mapping for the machine vectors at the high-vectors
799 * location (0xffff0000). If we aren't using high-vectors, also
800 * create a mapping at the low-vectors virtual address.
802 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
803 map.virtual = 0xffff0000;
804 map.length = PAGE_SIZE;
805 map.type = MT_HIGH_VECTORS;
806 create_mapping(&map);
808 if (!vectors_high()) {
810 map.type = MT_LOW_VECTORS;
811 create_mapping(&map);
815 * Ask the machine support to map in the statically mapped devices.
821 * Finally flush the caches and tlb to ensure that we're in a
822 * consistent state wrt the writebuffer. This also ensures that
823 * any write-allocated cache lines in the vector page are written
824 * back. After this point, we can start to touch devices again.
826 local_flush_tlb_all();
831 * paging_init() sets up the page tables, initialises the zone memory
832 * maps, and sets up the zero page, bad page and bad page tables.
834 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
838 build_mem_type_table();
839 sanity_check_meminfo(mi);
840 prepare_page_table(mi);
842 devicemaps_init(mdesc);
844 top_pmd = pmd_off_k(0xffff0000);
847 * allocate the zero page. Note that we count on this going ok.
849 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
850 memzero(zero_page, PAGE_SIZE);
851 empty_zero_page = virt_to_page(zero_page);
852 flush_dcache_page(empty_zero_page);
856 * In order to soft-boot, we need to insert a 1:1 mapping in place of
857 * the user-mode pages. This will then ensure that we have predictable
858 * results when turning the mmu off
860 void setup_mm_for_reboot(char mode)
862 unsigned long base_pmdval;
866 if (current->mm && current->mm->pgd)
867 pgd = current->mm->pgd;
871 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
872 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
873 base_pmdval |= PMD_BIT4;
875 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
876 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
879 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
880 pmd[0] = __pmd(pmdval);
881 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
882 flush_pmd_entry(pmd);