1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor" if ARCH_RPC
18 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU
20 select CPU_PABRT_NOIFAR
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
34 select CPU_PABRT_NOIFAR
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 which has no memory control unit and cache.
40 Say Y if you want support for the ARM7TDMI processor.
45 bool "Support ARM710 processor" if ARCH_RPC
50 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU
52 select CPU_PABRT_NOIFAR
54 A 32-bit RISC microprocessor based on the ARM7 processor core
55 designed by Advanced RISC Machines Ltd. The ARM710 is the
56 successor to the ARM610 processor. It was released in
57 July 1994 by VLSI Technology Inc.
59 Say Y if you want support for the ARM710 processor.
64 bool "Support ARM720T processor" if ARCH_INTEGRATOR
67 select CPU_PABRT_NOIFAR
71 select CPU_COPY_V4WT if MMU
72 select CPU_TLB_V4WT if MMU
74 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
75 MMU built around an ARM7TDMI core.
77 Say Y if you want support for the ARM720T processor.
82 bool "Support ARM740T processor" if ARCH_INTEGRATOR
86 select CPU_PABRT_NOIFAR
87 select CPU_CACHE_V3 # although the core is v4t
90 A 32-bit RISC processor with 8KB cache or 4KB variants,
91 write buffer and MPU(Protection Unit) built around
94 Say Y if you want support for the ARM740T processor.
99 bool "Support ARM9TDMI processor"
102 select CPU_ABRT_NOMMU
103 select CPU_PABRT_NOIFAR
106 A 32-bit RISC microprocessor based on the ARM9 processor core
107 which has no memory control unit and cache.
109 Say Y if you want support for the ARM9TDMI processor.
114 bool "Support ARM920T processor" if ARCH_INTEGRATOR
117 select CPU_PABRT_NOIFAR
118 select CPU_CACHE_V4WT
119 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_TLB_V4WBI if MMU
124 The ARM920T is licensed to be produced by numerous vendors,
125 and is used in the Maverick EP9312 and the Samsung S3C2410.
127 More information on the Maverick EP9312 at
128 <http://linuxdevices.com/products/PD2382866068.html>.
130 Say Y if you want support for the ARM920T processor.
135 bool "Support ARM922T processor" if ARCH_INTEGRATOR
138 select CPU_PABRT_NOIFAR
139 select CPU_CACHE_V4WT
140 select CPU_CACHE_VIVT
142 select CPU_COPY_V4WB if MMU
143 select CPU_TLB_V4WBI if MMU
145 The ARM922T is a version of the ARM920T, but with smaller
146 instruction and data caches. It is used in Altera's
147 Excalibur XA device family and Micrel's KS8695 Centaur.
149 Say Y if you want support for the ARM922T processor.
154 bool "Support ARM925T processor" if ARCH_OMAP1
157 select CPU_PABRT_NOIFAR
158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT
161 select CPU_COPY_V4WB if MMU
162 select CPU_TLB_V4WBI if MMU
164 The ARM925T is a mix between the ARM920T and ARM926T, but with
165 different instruction and data caches. It is used in TI's OMAP
168 Say Y if you want support for the ARM925T processor.
173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
175 select CPU_ABRT_EV5TJ
176 select CPU_PABRT_NOIFAR
177 select CPU_CACHE_VIVT
179 select CPU_COPY_V4WB if MMU
180 select CPU_TLB_V4WBI if MMU
182 This is a variant of the ARM920. It has slightly different
183 instruction sequences for cache and TLB operations. Curiously,
184 there is no documentation on it at the ARM corporate website.
186 Say Y if you want support for the ARM926T processor.
191 bool "Support ARM940T processor" if ARCH_INTEGRATOR
194 select CPU_ABRT_NOMMU
195 select CPU_PABRT_NOIFAR
196 select CPU_CACHE_VIVT
199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and separate 4KB
201 instruction and 4KB data cases, each with a 4-word line
204 Say Y if you want support for the ARM940T processor.
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
212 select CPU_ABRT_NOMMU
213 select CPU_PABRT_NOIFAR
214 select CPU_CACHE_VIVT
217 ARM946E-S is a member of the ARM9E-S family of high-
218 performance, 32-bit system-on-chip processor solutions.
219 The TCM and ARMv5TE 32-bit instruction set is supported.
221 Say Y if you want support for the ARM946E-S processor.
224 # ARM1020 - needs validating
226 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
229 select CPU_PABRT_NOIFAR
230 select CPU_CACHE_V4WT
231 select CPU_CACHE_VIVT
233 select CPU_COPY_V4WB if MMU
234 select CPU_TLB_V4WBI if MMU
236 The ARM1020 is the 32K cached version of the ARM10 processor,
237 with an addition of a floating-point unit.
239 Say Y if you want support for the ARM1020 processor.
242 # ARM1020E - needs validating
244 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
247 select CPU_PABRT_NOIFAR
248 select CPU_CACHE_V4WT
249 select CPU_CACHE_VIVT
251 select CPU_COPY_V4WB if MMU
252 select CPU_TLB_V4WBI if MMU
257 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
260 select CPU_PABRT_NOIFAR
261 select CPU_CACHE_VIVT
263 select CPU_COPY_V4WB if MMU # can probably do better
264 select CPU_TLB_V4WBI if MMU
266 The ARM1022E is an implementation of the ARMv5TE architecture
267 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
268 embedded trace macrocell, and a floating-point unit.
270 Say Y if you want support for the ARM1022E processor.
275 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
278 select CPU_PABRT_NOIFAR
279 select CPU_CACHE_VIVT
281 select CPU_COPY_V4WB if MMU # can probably do better
282 select CPU_TLB_V4WBI if MMU
284 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
285 based upon the ARM10 integer core.
287 Say Y if you want support for the ARM1026EJ-S processor.
292 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
293 select CPU_32v3 if ARCH_RPC
294 select CPU_32v4 if !ARCH_RPC
296 select CPU_PABRT_NOIFAR
297 select CPU_CACHE_V4WB
298 select CPU_CACHE_VIVT
300 select CPU_COPY_V4WB if MMU
301 select CPU_TLB_V4WB if MMU
303 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
304 is available at five speeds ranging from 100 MHz to 233 MHz.
305 More information is available at
306 <http://developer.intel.com/design/strong/sa110.htm>.
308 Say Y if you want support for the SA-110 processor.
316 select CPU_PABRT_NOIFAR
317 select CPU_CACHE_V4WB
318 select CPU_CACHE_VIVT
320 select CPU_TLB_V4WB if MMU
327 select CPU_PABRT_NOIFAR
328 select CPU_CACHE_VIVT
330 select CPU_TLB_V4WBI if MMU
332 # XScale Core Version 3
337 select CPU_PABRT_NOIFAR
338 select CPU_CACHE_VIVT
340 select CPU_TLB_V4WBI if MMU
343 # Marvell PJ1 (Mohawk)
348 select CPU_PABRT_NOIFAR
349 select CPU_CACHE_VIVT
351 select CPU_TLB_V4WBI if MMU
352 select CPU_COPY_V4WB if MMU
359 select CPU_PABRT_NOIFAR
360 select CPU_CACHE_VIVT
362 select CPU_COPY_FEROCEON if MMU
363 select CPU_TLB_FEROCEON if MMU
365 config CPU_FEROCEON_OLD_ID
366 bool "Accept early Feroceon cores with an ARM926 ID"
367 depends on CPU_FEROCEON && !CPU_ARM926T
370 This enables the usage of some old Feroceon cores
371 for which the CPU ID is equal to the ARM926 ID.
372 Relevant for Feroceon-1850 and early Feroceon-2850.
376 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
379 select CPU_PABRT_NOIFAR
381 select CPU_CACHE_VIPT
383 select CPU_HAS_ASID if MMU
384 select CPU_COPY_V6 if MMU
385 select CPU_TLB_V6 if MMU
389 bool "Support ARM V6K processor extensions" if !SMP
391 default y if SMP && !ARCH_MX3
393 Say Y here if your ARMv6 processor supports the 'K' extension.
394 This enables the kernel to use some instructions not present
395 on previous processors, and as such a kernel build with this
396 enabled will not boot on processors with do not support these
401 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
405 select CPU_PABRT_IFAR
407 select CPU_CACHE_VIPT
409 select CPU_HAS_ASID if MMU
410 select CPU_COPY_V6 if MMU
411 select CPU_TLB_V7 if MMU
413 # Figure out what processor architecture version we should be using.
414 # This defines the compiler instruction set which depends on the machine type.
417 select TLS_REG_EMUL if SMP || !MMU
418 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
422 select TLS_REG_EMUL if SMP || !MMU
423 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
427 select TLS_REG_EMUL if SMP || !MMU
428 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
432 select TLS_REG_EMUL if SMP || !MMU
433 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437 select TLS_REG_EMUL if !CPU_32v6K && !MMU
443 config CPU_ABRT_NOMMU
458 config CPU_ABRT_EV5TJ
467 config CPU_PABRT_IFAR
470 config CPU_PABRT_NOIFAR
480 config CPU_CACHE_V4WT
483 config CPU_CACHE_V4WB
492 config CPU_CACHE_VIVT
495 config CPU_CACHE_VIPT
499 # The copy-page model
509 config CPU_COPY_FEROCEON
515 # This selects the TLB model
519 ARM Architecture Version 3 TLB.
524 ARM Architecture Version 4 TLB with writethrough cache.
529 ARM Architecture Version 4 TLB with writeback cache.
534 ARM Architecture Version 4 TLB with writeback cache and invalidate
535 instruction cache entry.
537 config CPU_TLB_FEROCEON
540 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
553 This indicates whether the CPU has the ASID register; used to
554 tag TLB and possibly cache entries.
559 Processor has the CP15 register.
565 Processor has the CP15 register, which has MMU related registers.
571 Processor has the CP15 register, which has MPU related registers.
574 # CPU supports 36-bit I/O
579 comment "Processor Features"
582 bool "Support Thumb user binaries"
583 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
586 Say Y if you want to include kernel support for running user space
589 The Thumb instruction set is a compressed form of the standard ARM
590 instruction set resulting in smaller binaries at the expense of
591 slightly less efficient code.
593 If you don't know what this all is, saying Y is a safe choice.
596 bool "Enable ThumbEE CPU extension"
599 Say Y here if you have a CPU with the ThumbEE extension and code to
600 make use of it. Say N for code that can run on CPUs without ThumbEE.
602 config CPU_BIG_ENDIAN
603 bool "Build big-endian kernel"
604 depends on ARCH_SUPPORTS_BIG_ENDIAN
606 Say Y if you plan on running a kernel in big-endian mode.
607 Note that your board must be properly built and your board
608 port must properly enable any big-endian related features
609 of your chipset/board/processor.
611 config CPU_HIGH_VECTOR
612 depends on !MMU && CPU_CP15 && !CPU_ARM740T
613 bool "Select the High exception vector"
616 Say Y here to select high exception vector(0xFFFF0000~).
617 The exception vector can be vary depending on the platform
618 design in nommu mode. If your platform needs to select
619 high exception vector, say Y.
620 Otherwise or if you are unsure, say N, and the low exception
621 vector (0x00000000~) will be used.
623 config CPU_ICACHE_DISABLE
624 bool "Disable I-Cache (I-bit)"
625 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
627 Say Y here to disable the processor instruction cache. Unless
628 you have a reason not to or are unsure, say N.
630 config CPU_DCACHE_DISABLE
631 bool "Disable D-Cache (C-bit)"
634 Say Y here to disable the processor data cache. Unless
635 you have a reason not to or are unsure, say N.
637 config CPU_DCACHE_SIZE
639 depends on CPU_ARM740T || CPU_ARM946E
640 default 0x00001000 if CPU_ARM740T
641 default 0x00002000 # default size for ARM946E-S
643 Some cores are synthesizable to have various sized cache. For
644 ARM946E-S case, it can vary from 0KB to 1MB.
645 To support such cache operations, it is efficient to know the size
647 If your SoC is configured to have a different size, define the value
648 here with proper conditions.
650 config CPU_DCACHE_WRITETHROUGH
651 bool "Force write through D-cache"
652 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
653 default y if CPU_ARM925T
655 Say Y here to use the data cache in writethrough mode. Unless you
656 specifically require this or are unsure, say N.
658 config CPU_CACHE_ROUND_ROBIN
659 bool "Round robin I and D cache replacement algorithm"
660 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
662 Say Y here to use the predictable round-robin cache replacement
663 policy. Unless you specifically require this or are unsure, say N.
665 config CPU_BPREDICT_DISABLE
666 bool "Disable branch prediction"
667 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7
669 Say Y here to disable branch prediction. If unsure, say N.
674 An SMP system using a pre-ARMv6 processor (there are apparently
675 a few prototypes like that in existence) and therefore access to
676 that required register must be emulated.
680 depends on !TLS_REG_EMUL
681 default y if SMP || CPU_32v7
683 This selects support for the CP15 thread register.
684 It is defined to be available on some ARMv6 processors (including
685 all SMP capable ARMv6's) or later processors. User space may
686 assume directly accessing that register and always obtain the
687 expected value only on ARMv7 and above.
689 config NEEDS_SYSCALL_FOR_CMPXCHG
692 SMP on a pre-ARMv6 processor? Well OK then.
693 Forget about fast user space cmpxchg support.
694 It is just not possible.
700 config CACHE_FEROCEON_L2
701 bool "Enable the Feroceon L2 cache controller"
702 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
706 This option enables the Feroceon L2 cache controller.
708 config CACHE_FEROCEON_L2_WRITETHROUGH
709 bool "Force Feroceon L2 cache write through"
710 depends on CACHE_FEROCEON_L2
713 Say Y here to use the Feroceon L2 cache in writethrough mode.
714 Unless you specifically require this, say N for writeback mode.
717 bool "Enable the L2x0 outer cache controller"
718 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
719 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
723 This option enables the L2x0 PrimeCell.
726 bool "Enable the L2 cache on XScale3"
731 This option enables the L2 cache on XScale3.