1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
21 select CPU_PABRT_NOIFAR
23 The ARM610 is the successor to the ARM3 processor
24 and was produced by VLSI Technology Inc.
26 Say Y if you want support for the ARM610 processor.
31 bool "Support ARM7TDMI processor"
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 which has no memory control unit and cache.
40 Say Y if you want support for the ARM7TDMI processor.
45 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
46 default y if ARCH_CLPS7500
51 select CPU_COPY_V3 if MMU
52 select CPU_TLB_V3 if MMU
53 select CPU_PABRT_NOIFAR
55 A 32-bit RISC microprocessor based on the ARM7 processor core
56 designed by Advanced RISC Machines Ltd. The ARM710 is the
57 successor to the ARM610 processor. It was released in
58 July 1994 by VLSI Technology Inc.
60 Say Y if you want support for the ARM710 processor.
65 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
66 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
69 select CPU_PABRT_NOIFAR
73 select CPU_COPY_V4WT if MMU
74 select CPU_TLB_V4WT if MMU
76 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
77 MMU built around an ARM7TDMI core.
79 Say Y if you want support for the ARM720T processor.
84 bool "Support ARM740T processor" if ARCH_INTEGRATOR
88 select CPU_CACHE_V3 # although the core is v4t
91 A 32-bit RISC processor with 8KB cache or 4KB variants,
92 write buffer and MPU(Protection Unit) built around
95 Say Y if you want support for the ARM740T processor.
100 bool "Support ARM9TDMI processor"
103 select CPU_ABRT_NOMMU
106 A 32-bit RISC microprocessor based on the ARM9 processor core
107 which has no memory control unit and cache.
109 Say Y if you want support for the ARM9TDMI processor.
114 bool "Support ARM920T processor"
115 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
116 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
119 select CPU_PABRT_NOIFAR
120 select CPU_CACHE_V4WT
121 select CPU_CACHE_VIVT
123 select CPU_COPY_V4WB if MMU
124 select CPU_TLB_V4WBI if MMU
126 The ARM920T is licensed to be produced by numerous vendors,
127 and is used in the Maverick EP9312 and the Samsung S3C2410.
129 More information on the Maverick EP9312 at
130 <http://linuxdevices.com/products/PD2382866068.html>.
132 Say Y if you want support for the ARM920T processor.
137 bool "Support ARM922T processor" if ARCH_INTEGRATOR
138 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
139 default y if ARCH_LH7A40X || ARCH_KS8695
142 select CPU_PABRT_NOIFAR
143 select CPU_CACHE_V4WT
144 select CPU_CACHE_VIVT
146 select CPU_COPY_V4WB if MMU
147 select CPU_TLB_V4WBI if MMU
149 The ARM922T is a version of the ARM920T, but with smaller
150 instruction and data caches. It is used in Altera's
151 Excalibur XA device family and Micrel's KS8695 Centaur.
153 Say Y if you want support for the ARM922T processor.
158 bool "Support ARM925T processor" if ARCH_OMAP1
159 depends on ARCH_OMAP15XX
160 default y if ARCH_OMAP15XX
163 select CPU_PABRT_NOIFAR
164 select CPU_CACHE_V4WT
165 select CPU_CACHE_VIVT
167 select CPU_COPY_V4WB if MMU
168 select CPU_TLB_V4WBI if MMU
170 The ARM925T is a mix between the ARM920T and ARM926T, but with
171 different instruction and data caches. It is used in TI's OMAP
174 Say Y if you want support for the ARM925T processor.
179 bool "Support ARM926T processor"
180 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
181 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
183 select CPU_ABRT_EV5TJ
184 select CPU_PABRT_NOIFAR
185 select CPU_CACHE_VIVT
187 select CPU_COPY_V4WB if MMU
188 select CPU_TLB_V4WBI if MMU
190 This is a variant of the ARM920. It has slightly different
191 instruction sequences for cache and TLB operations. Curiously,
192 there is no documentation on it at the ARM corporate website.
194 Say Y if you want support for the ARM926T processor.
199 bool "Support ARM940T processor" if ARCH_INTEGRATOR
202 select CPU_ABRT_NOMMU
203 select CPU_CACHE_VIVT
206 ARM940T is a member of the ARM9TDMI family of general-
207 purpose microprocessors with MPU and separate 4KB
208 instruction and 4KB data cases, each with a 4-word line
211 Say Y if you want support for the ARM940T processor.
216 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
219 select CPU_ABRT_NOMMU
220 select CPU_CACHE_VIVT
223 ARM946E-S is a member of the ARM9E-S family of high-
224 performance, 32-bit system-on-chip processor solutions.
225 The TCM and ARMv5TE 32-bit instruction set is supported.
227 Say Y if you want support for the ARM946E-S processor.
230 # ARM1020 - needs validating
232 bool "Support ARM1020T (rev 0) processor"
233 depends on ARCH_INTEGRATOR
236 select CPU_PABRT_NOIFAR
237 select CPU_CACHE_V4WT
238 select CPU_CACHE_VIVT
240 select CPU_COPY_V4WB if MMU
241 select CPU_TLB_V4WBI if MMU
243 The ARM1020 is the 32K cached version of the ARM10 processor,
244 with an addition of a floating-point unit.
246 Say Y if you want support for the ARM1020 processor.
249 # ARM1020E - needs validating
251 bool "Support ARM1020E processor"
252 depends on ARCH_INTEGRATOR
255 select CPU_PABRT_NOIFAR
256 select CPU_CACHE_V4WT
257 select CPU_CACHE_VIVT
259 select CPU_COPY_V4WB if MMU
260 select CPU_TLB_V4WBI if MMU
265 bool "Support ARM1022E processor"
266 depends on ARCH_INTEGRATOR
269 select CPU_PABRT_NOIFAR
270 select CPU_CACHE_VIVT
272 select CPU_COPY_V4WB if MMU # can probably do better
273 select CPU_TLB_V4WBI if MMU
275 The ARM1022E is an implementation of the ARMv5TE architecture
276 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
277 embedded trace macrocell, and a floating-point unit.
279 Say Y if you want support for the ARM1022E processor.
284 bool "Support ARM1026EJ-S processor"
285 depends on ARCH_INTEGRATOR
287 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
288 select CPU_PABRT_NOIFAR
289 select CPU_CACHE_VIVT
291 select CPU_COPY_V4WB if MMU # can probably do better
292 select CPU_TLB_V4WBI if MMU
294 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
295 based upon the ARM10 integer core.
297 Say Y if you want support for the ARM1026EJ-S processor.
302 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
303 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
307 select CPU_PABRT_NOIFAR
308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
319 Say Y if you want support for the SA-110 processor.
325 depends on ARCH_SA1100
329 select CPU_PABRT_NOIFAR
330 select CPU_CACHE_V4WB
331 select CPU_CACHE_VIVT
333 select CPU_TLB_V4WB if MMU
338 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
342 select CPU_PABRT_NOIFAR
343 select CPU_CACHE_VIVT
345 select CPU_TLB_V4WBI if MMU
347 # XScale Core Version 3
350 depends on ARCH_IXP23XX || ARCH_IOP13XX
354 select CPU_CACHE_VIVT
356 select CPU_TLB_V4WBI if MMU
361 bool "Support ARM V6 processor"
362 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
363 default y if ARCH_MX3
366 select CPU_PABRT_NOIFAR
368 select CPU_CACHE_VIPT
370 select CPU_HAS_ASID if MMU
371 select CPU_COPY_V6 if MMU
372 select CPU_TLB_V6 if MMU
376 bool "Support ARM V6K processor extensions" if !SMP
378 default y if SMP && !ARCH_MX3
380 Say Y here if your ARMv6 processor supports the 'K' extension.
381 This enables the kernel to use some instructions not present
382 on previous processors, and as such a kernel build with this
383 enabled will not boot on processors with do not support these
388 bool "Support ARM V7 processor"
389 depends on ARCH_INTEGRATOR || ARCH_OMAP3
393 select CPU_PABRT_IFAR
395 select CPU_CACHE_VIPT
397 select CPU_HAS_ASID if MMU
398 select CPU_COPY_V6 if MMU
399 select CPU_TLB_V7 if MMU
401 # Figure out what processor architecture version we should be using.
402 # This defines the compiler instruction set which depends on the machine type.
405 select TLS_REG_EMUL if SMP || !MMU
406 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
410 select TLS_REG_EMUL if SMP || !MMU
411 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
415 select TLS_REG_EMUL if SMP || !MMU
416 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
420 select TLS_REG_EMUL if SMP || !MMU
421 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
425 select TLS_REG_EMUL if !CPU_32v6K && !MMU
431 config CPU_ABRT_NOMMU
446 config CPU_ABRT_EV5TJ
455 config CPU_PABRT_IFAR
458 config CPU_PABRT_NOIFAR
468 config CPU_CACHE_V4WT
471 config CPU_CACHE_V4WB
480 config CPU_CACHE_VIVT
483 config CPU_CACHE_VIPT
487 # The copy-page model
500 # This selects the TLB model
504 ARM Architecture Version 3 TLB.
509 ARM Architecture Version 4 TLB with writethrough cache.
514 ARM Architecture Version 4 TLB with writeback cache.
519 ARM Architecture Version 4 TLB with writeback cache and invalidate
520 instruction cache entry.
533 This indicates whether the CPU has the ASID register; used to
534 tag TLB and possibly cache entries.
539 Processor has the CP15 register.
545 Processor has the CP15 register, which has MMU related registers.
551 Processor has the CP15 register, which has MPU related registers.
554 # CPU supports 36-bit I/O
559 comment "Processor Features"
562 bool "Support Thumb user binaries"
563 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
566 Say Y if you want to include kernel support for running user space
569 The Thumb instruction set is a compressed form of the standard ARM
570 instruction set resulting in smaller binaries at the expense of
571 slightly less efficient code.
573 If you don't know what this all is, saying Y is a safe choice.
576 bool "Enable Xenon extension"
579 Say Y here if you have a CPU with Xenon extension and code to make
580 use of it. Say N for code that can run on CPUs without Xenon.
582 config CPU_BIG_ENDIAN
583 bool "Build big-endian kernel"
584 depends on ARCH_SUPPORTS_BIG_ENDIAN
586 Say Y if you plan on running a kernel in big-endian mode.
587 Note that your board must be properly built and your board
588 port must properly enable any big-endian related features
589 of your chipset/board/processor.
591 config CPU_HIGH_VECTOR
592 depends on !MMU && CPU_CP15 && !CPU_ARM740T
593 bool "Select the High exception vector"
596 Say Y here to select high exception vector(0xFFFF0000~).
597 The exception vector can be vary depending on the platform
598 design in nommu mode. If your platform needs to select
599 high exception vector, say Y.
600 Otherwise or if you are unsure, say N, and the low exception
601 vector (0x00000000~) will be used.
603 config CPU_ICACHE_DISABLE
604 bool "Disable I-Cache (I-bit)"
605 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
607 Say Y here to disable the processor instruction cache. Unless
608 you have a reason not to or are unsure, say N.
610 config CPU_DCACHE_DISABLE
611 bool "Disable D-Cache (C-bit)"
614 Say Y here to disable the processor data cache. Unless
615 you have a reason not to or are unsure, say N.
617 config CPU_DCACHE_SIZE
619 depends on CPU_ARM740T || CPU_ARM946E
620 default 0x00001000 if CPU_ARM740T
621 default 0x00002000 # default size for ARM946E-S
623 Some cores are synthesizable to have various sized cache. For
624 ARM946E-S case, it can vary from 0KB to 1MB.
625 To support such cache operations, it is efficient to know the size
627 If your SoC is configured to have a different size, define the value
628 here with proper conditions.
630 config CPU_DCACHE_WRITETHROUGH
631 bool "Force write through D-cache"
632 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
633 default y if CPU_ARM925T
635 Say Y here to use the data cache in writethrough mode. Unless you
636 specifically require this or are unsure, say N.
638 config CPU_CACHE_ROUND_ROBIN
639 bool "Round robin I and D cache replacement algorithm"
640 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
642 Say Y here to use the predictable round-robin cache replacement
643 policy. Unless you specifically require this or are unsure, say N.
645 config CPU_BPREDICT_DISABLE
646 bool "Disable branch prediction"
647 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
649 Say Y here to disable branch prediction. If unsure, say N.
654 An SMP system using a pre-ARMv6 processor (there are apparently
655 a few prototypes like that in existence) and therefore access to
656 that required register must be emulated.
660 depends on !TLS_REG_EMUL
661 default y if SMP || CPU_32v7
663 This selects support for the CP15 thread register.
664 It is defined to be available on some ARMv6 processors (including
665 all SMP capable ARMv6's) or later processors. User space may
666 assume directly accessing that register and always obtain the
667 expected value only on ARMv7 and above.
669 config NEEDS_SYSCALL_FOR_CMPXCHG
672 SMP on a pre-ARMv6 processor? Well OK then.
673 Forget about fast user space cmpxchg support.
674 It is just not possible.