2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
31 #include <linux/smc911x.h>
33 #include <asm/system.h>
34 #include <mach/hardware.h>
37 #include <asm/mach-types.h>
38 #include <asm/hardware/arm_timer.h>
39 #include <asm/hardware/icst307.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/flash.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/mmc.h>
47 #include <asm/hardware/gic.h>
52 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
54 /* used by entry-macro.S and platsmp.c */
55 void __iomem *gic_cpu_base_addr;
58 * This is the RealView sched_clock implementation. This has
59 * a resolution of 41.7ns, and a maximum value of about 179s.
61 unsigned long long sched_clock(void)
65 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
72 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
74 static int realview_flash_init(void)
78 val = __raw_readl(REALVIEW_FLASHCTRL);
79 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
80 __raw_writel(val, REALVIEW_FLASHCTRL);
85 static void realview_flash_exit(void)
89 val = __raw_readl(REALVIEW_FLASHCTRL);
90 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
91 __raw_writel(val, REALVIEW_FLASHCTRL);
94 static void realview_flash_set_vpp(int on)
98 val = __raw_readl(REALVIEW_FLASHCTRL);
100 val |= REALVIEW_FLASHPROG_FLVPPEN;
102 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
103 __raw_writel(val, REALVIEW_FLASHCTRL);
106 static struct flash_platform_data realview_flash_data = {
107 .map_name = "cfi_probe",
109 .init = realview_flash_init,
110 .exit = realview_flash_exit,
111 .set_vpp = realview_flash_set_vpp,
114 struct platform_device realview_flash_device = {
118 .platform_data = &realview_flash_data,
122 int realview_flash_register(struct resource *res, u32 num)
124 realview_flash_device.resource = res;
125 realview_flash_device.num_resources = num;
126 return platform_device_register(&realview_flash_device);
129 static struct smc911x_platdata realview_smc911x_platdata = {
130 .flags = SMC911X_USE_32BIT,
131 .irq_flags = IRQF_SHARED,
135 static struct platform_device realview_eth_device = {
141 int realview_eth_register(const char *name, struct resource *res)
144 realview_eth_device.name = name;
145 realview_eth_device.resource = res;
146 if (strcmp(realview_eth_device.name, "smc911x") == 0)
147 realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
149 return platform_device_register(&realview_eth_device);
152 static struct resource realview_i2c_resource = {
153 .start = REALVIEW_I2C_BASE,
154 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
155 .flags = IORESOURCE_MEM,
158 struct platform_device realview_i2c_device = {
159 .name = "versatile-i2c",
162 .resource = &realview_i2c_resource,
165 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
167 static unsigned int realview_mmc_status(struct device *dev)
169 struct amba_device *adev = container_of(dev, struct amba_device, dev);
172 if (adev->res.start == REALVIEW_MMCI0_BASE)
177 return readl(REALVIEW_SYSMCI) & mask;
180 struct mmc_platform_data realview_mmc0_plat_data = {
181 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
182 .status = realview_mmc_status,
185 struct mmc_platform_data realview_mmc1_plat_data = {
186 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
187 .status = realview_mmc_status,
193 static const struct icst307_params realview_oscvco_params = {
202 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
204 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
205 void __iomem *sys_osc;
208 if (machine_is_realview_pb1176())
209 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
211 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
213 val = readl(sys_osc) & ~0x7ffff;
214 val |= vco.v | (vco.r << 9) | (vco.s << 16);
216 writel(0xa05f, sys_lock);
217 writel(val, sys_osc);
221 struct clk realview_clcd_clk = {
223 .params = &realview_oscvco_params,
224 .setvco = realview_oscvco_set,
230 #define SYS_CLCD_NLCDIOON (1 << 2)
231 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
232 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
233 #define SYS_CLCD_ID_MASK (0x1f << 8)
234 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
235 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
236 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
237 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
238 #define SYS_CLCD_ID_VGA (0x1f << 8)
240 static struct clcd_panel vga = {
254 .vmode = FB_VMODE_NONINTERLACED,
258 .tim2 = TIM2_BCD | TIM2_IPC,
259 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
263 static struct clcd_panel xvga = {
277 .vmode = FB_VMODE_NONINTERLACED,
281 .tim2 = TIM2_BCD | TIM2_IPC,
282 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
286 static struct clcd_panel sanyo_3_8_in = {
288 .name = "Sanyo QVGA",
300 .vmode = FB_VMODE_NONINTERLACED,
305 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
309 static struct clcd_panel sanyo_2_5_in = {
311 .name = "Sanyo QVGA Portrait",
322 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
323 .vmode = FB_VMODE_NONINTERLACED,
327 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
328 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
332 static struct clcd_panel epson_2_2_in = {
334 .name = "Epson QCIF",
346 .vmode = FB_VMODE_NONINTERLACED,
350 .tim2 = TIM2_BCD | TIM2_IPC,
351 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
356 * Detect which LCD panel is connected, and return the appropriate
357 * clcd_panel structure. Note: we do not have any information on
358 * the required timings for the 8.4in panel, so we presently assume
361 static struct clcd_panel *realview_clcd_panel(void)
363 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
364 struct clcd_panel *vga_panel;
365 struct clcd_panel *panel;
368 if (machine_is_realview_eb())
373 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
374 if (val == SYS_CLCD_ID_SANYO_3_8)
375 panel = &sanyo_3_8_in;
376 else if (val == SYS_CLCD_ID_SANYO_2_5)
377 panel = &sanyo_2_5_in;
378 else if (val == SYS_CLCD_ID_EPSON_2_2)
379 panel = &epson_2_2_in;
380 else if (val == SYS_CLCD_ID_VGA)
383 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
392 * Disable all display connectors on the interface module.
394 static void realview_clcd_disable(struct clcd_fb *fb)
396 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
399 val = readl(sys_clcd);
400 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
401 writel(val, sys_clcd);
405 * Enable the relevant connector on the interface module.
407 static void realview_clcd_enable(struct clcd_fb *fb)
409 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
415 val = readl(sys_clcd);
416 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
417 writel(val, sys_clcd);
420 static int realview_clcd_setup(struct clcd_fb *fb)
422 unsigned long framesize;
425 if (machine_is_realview_eb())
427 framesize = 640 * 480 * 2;
430 framesize = 1024 * 768 * 2;
432 fb->panel = realview_clcd_panel();
434 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
436 if (!fb->fb.screen_base) {
437 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
441 fb->fb.fix.smem_start = dma;
442 fb->fb.fix.smem_len = framesize;
447 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
449 return dma_mmap_writecombine(&fb->dev->dev, vma,
451 fb->fb.fix.smem_start,
452 fb->fb.fix.smem_len);
455 static void realview_clcd_remove(struct clcd_fb *fb)
457 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
458 fb->fb.screen_base, fb->fb.fix.smem_start);
461 struct clcd_board clcd_plat_data = {
463 .check = clcdfb_check,
464 .decode = clcdfb_decode,
465 .disable = realview_clcd_disable,
466 .enable = realview_clcd_enable,
467 .setup = realview_clcd_setup,
468 .mmap = realview_clcd_mmap,
469 .remove = realview_clcd_remove,
473 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
475 void realview_leds_event(led_event_t ledevt)
480 local_irq_save(flags);
481 val = readl(VA_LEDS_BASE);
485 val = val & ~REALVIEW_SYS_LED0;
489 val = val | REALVIEW_SYS_LED0;
493 val = val ^ REALVIEW_SYS_LED1;
504 writel(val, VA_LEDS_BASE);
505 local_irq_restore(flags);
507 #endif /* CONFIG_LEDS */
510 * Where is the timer (VA)?
512 void __iomem *timer0_va_base;
513 void __iomem *timer1_va_base;
514 void __iomem *timer2_va_base;
515 void __iomem *timer3_va_base;
518 * How long is the timer interval?
520 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
521 #if TIMER_INTERVAL >= 0x100000
522 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
523 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
524 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
525 #elif TIMER_INTERVAL >= 0x10000
526 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
527 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
528 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
530 #define TIMER_RELOAD (TIMER_INTERVAL)
531 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
532 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
535 static void timer_set_mode(enum clock_event_mode mode,
536 struct clock_event_device *clk)
541 case CLOCK_EVT_MODE_PERIODIC:
542 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
544 ctrl = TIMER_CTRL_PERIODIC;
545 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
547 case CLOCK_EVT_MODE_ONESHOT:
548 /* period set, and timer enabled in 'next_event' hook */
549 ctrl = TIMER_CTRL_ONESHOT;
550 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
552 case CLOCK_EVT_MODE_UNUSED:
553 case CLOCK_EVT_MODE_SHUTDOWN:
558 writel(ctrl, timer0_va_base + TIMER_CTRL);
561 static int timer_set_next_event(unsigned long evt,
562 struct clock_event_device *unused)
564 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
566 writel(evt, timer0_va_base + TIMER_LOAD);
567 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
572 static struct clock_event_device timer0_clockevent = {
575 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
576 .set_mode = timer_set_mode,
577 .set_next_event = timer_set_next_event,
579 .cpumask = CPU_MASK_ALL,
582 static void __init realview_clockevents_init(unsigned int timer_irq)
584 timer0_clockevent.irq = timer_irq;
585 timer0_clockevent.mult =
586 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
587 timer0_clockevent.max_delta_ns =
588 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
589 timer0_clockevent.min_delta_ns =
590 clockevent_delta2ns(0xf, &timer0_clockevent);
592 clockevents_register_device(&timer0_clockevent);
596 * IRQ handler for the timer
598 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
600 struct clock_event_device *evt = &timer0_clockevent;
602 /* clear the interrupt */
603 writel(1, timer0_va_base + TIMER_INTCLR);
605 evt->event_handler(evt);
610 static struct irqaction realview_timer_irq = {
611 .name = "RealView Timer Tick",
612 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
613 .handler = realview_timer_interrupt,
616 static cycle_t realview_get_cycles(void)
618 return ~readl(timer3_va_base + TIMER_VALUE);
621 static struct clocksource clocksource_realview = {
624 .read = realview_get_cycles,
625 .mask = CLOCKSOURCE_MASK(32),
627 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
630 static void __init realview_clocksource_init(void)
632 /* setup timer 0 as free-running clocksource */
633 writel(0, timer3_va_base + TIMER_CTRL);
634 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
635 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
636 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
637 timer3_va_base + TIMER_CTRL);
639 clocksource_realview.mult =
640 clocksource_khz2mult(1000, clocksource_realview.shift);
641 clocksource_register(&clocksource_realview);
645 * Set up the clock source and clock events devices
647 void __init realview_timer_init(unsigned int timer_irq)
651 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
653 * The dummy clock device has to be registered before the main device
654 * so that the latter will broadcast the clock events
660 * set clock frequency:
661 * REALVIEW_REFCLK is 32KHz
662 * REALVIEW_TIMCLK is 1MHz
664 val = readl(__io_address(REALVIEW_SCTL_BASE));
665 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
666 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
667 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
668 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
669 __io_address(REALVIEW_SCTL_BASE));
672 * Initialise to a known state (all timers off)
674 writel(0, timer0_va_base + TIMER_CTRL);
675 writel(0, timer1_va_base + TIMER_CTRL);
676 writel(0, timer2_va_base + TIMER_CTRL);
677 writel(0, timer3_va_base + TIMER_CTRL);
680 * Make irqs happen for the system timer
682 setup_irq(timer_irq, &realview_timer_irq);
684 realview_clocksource_init();
685 realview_clockevents_init(timer_irq);