arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/hardware.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst307.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/flash.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /*
  54  * This is the RealView sched_clock implementation.  This has
  55  * a resolution of 41.7ns, and a maximum value of about 179s.
  56  */
  57 unsigned long long sched_clock(void)
  58 {
  59         unsigned long long v;
  60
  61         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  62         do_div(v, 3);
  63
  64         return v;
  65 }
  66
  67
  68 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  69
  70 static int realview_flash_init(void)
  71 {
  72         u32 val;
  73
  74         val = __raw_readl(REALVIEW_FLASHCTRL);
  75         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  76         __raw_writel(val, REALVIEW_FLASHCTRL);
  77
  78         return 0;
  79 }
  80
  81 static void realview_flash_exit(void)
  82 {
  83         u32 val;
  84
  85         val = __raw_readl(REALVIEW_FLASHCTRL);
  86         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  87         __raw_writel(val, REALVIEW_FLASHCTRL);
  88 }
  89
  90 static void realview_flash_set_vpp(int on)
  91 {
  92         u32 val;
  93
  94         val = __raw_readl(REALVIEW_FLASHCTRL);
  95         if (on)
  96                 val |= REALVIEW_FLASHPROG_FLVPPEN;
  97         else
  98                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  99         __raw_writel(val, REALVIEW_FLASHCTRL);
 100 }
 101
 102 static struct flash_platform_data realview_flash_data = {
 103         .map_name               = "cfi_probe",
 104         .width                  = 4,
 105         .init                   = realview_flash_init,
 106         .exit                   = realview_flash_exit,
 107         .set_vpp                = realview_flash_set_vpp,
 108 };
 109
 110 static struct resource realview_flash_resource = {
 111         .start                  = REALVIEW_FLASH_BASE,
 112         .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
 113         .flags                  = IORESOURCE_MEM,
 114 };
 115
 116 struct platform_device realview_flash_device = {
 117         .name                   = "armflash",
 118         .id                     = 0,
 119         .dev                    = {
 120                 .platform_data  = &realview_flash_data,
 121         },
 122         .num_resources          = 1,
 123         .resource               = &realview_flash_resource,
 124 };
 125
 126 static struct resource realview_smc91x_resources[] = {
 127         [0] = {
 128                 .start          = REALVIEW_ETH_BASE,
 129                 .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
 130                 .flags          = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start          = IRQ_ETH,
 134                 .end            = IRQ_ETH,
 135                 .flags          = IORESOURCE_IRQ,
 136         },
 137 };
 138
 139 struct platform_device realview_smc91x_device = {
 140         .name           = "smc91x",
 141         .id             = 0,
 142         .num_resources  = ARRAY_SIZE(realview_smc91x_resources),
 143         .resource       = realview_smc91x_resources,
 144 };
 145
 146 static struct resource realview_i2c_resource = {
 147         .start          = REALVIEW_I2C_BASE,
 148         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 149         .flags          = IORESOURCE_MEM,
 150 };
 151
 152 struct platform_device realview_i2c_device = {
 153         .name           = "versatile-i2c",
 154         .id             = -1,
 155         .num_resources  = 1,
 156         .resource       = &realview_i2c_resource,
 157 };
 158
 159 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 160
 161 static unsigned int realview_mmc_status(struct device *dev)
 162 {
 163         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 164         u32 mask;
 165
 166         if (adev->res.start == REALVIEW_MMCI0_BASE)
 167                 mask = 1;
 168         else
 169                 mask = 2;
 170
 171         return readl(REALVIEW_SYSMCI) & mask;
 172 }
 173
 174 struct mmc_platform_data realview_mmc0_plat_data = {
 175         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 176         .status         = realview_mmc_status,
 177 };
 178
 179 struct mmc_platform_data realview_mmc1_plat_data = {
 180         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 181         .status         = realview_mmc_status,
 182 };
 183
 184 /*
 185  * Clock handling
 186  */
 187 static const struct icst307_params realview_oscvco_params = {
 188         .ref            = 24000,
 189         .vco_max        = 200000,
 190         .vd_min         = 4 + 8,
 191         .vd_max         = 511 + 8,
 192         .rd_min         = 1 + 2,
 193         .rd_max         = 127 + 2,
 194 };
 195
 196 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 197 {
 198         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 199         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 200         u32 val;
 201
 202         val = readl(sys_osc) & ~0x7ffff;
 203         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 204
 205         writel(0xa05f, sys_lock);
 206         writel(val, sys_osc);
 207         writel(0, sys_lock);
 208 }
 209
 210 struct clk realview_clcd_clk = {
 211         .name   = "CLCDCLK",
 212         .params = &realview_oscvco_params,
 213         .setvco = realview_oscvco_set,
 214 };
 215
 216 /*
 217  * CLCD support.
 218  */
 219 #define SYS_CLCD_NLCDIOON       (1 << 2)
 220 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 221 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 222 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 223 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 224 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 225 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 226 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 227 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 228
 229 static struct clcd_panel vga = {
 230         .mode           = {
 231                 .name           = "VGA",
 232                 .refresh        = 60,
 233                 .xres           = 640,
 234                 .yres           = 480,
 235                 .pixclock       = 39721,
 236                 .left_margin    = 40,
 237                 .right_margin   = 24,
 238                 .upper_margin   = 32,
 239                 .lower_margin   = 11,
 240                 .hsync_len      = 96,
 241                 .vsync_len      = 2,
 242                 .sync           = 0,
 243                 .vmode          = FB_VMODE_NONINTERLACED,
 244         },
 245         .width          = -1,
 246         .height         = -1,
 247         .tim2           = TIM2_BCD | TIM2_IPC,
 248         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 249         .bpp            = 16,
 250 };
 251
 252 static struct clcd_panel sanyo_3_8_in = {
 253         .mode           = {
 254                 .name           = "Sanyo QVGA",
 255                 .refresh        = 116,
 256                 .xres           = 320,
 257                 .yres           = 240,
 258                 .pixclock       = 100000,
 259                 .left_margin    = 6,
 260                 .right_margin   = 6,
 261                 .upper_margin   = 5,
 262                 .lower_margin   = 5,
 263                 .hsync_len      = 6,
 264                 .vsync_len      = 6,
 265                 .sync           = 0,
 266                 .vmode          = FB_VMODE_NONINTERLACED,
 267         },
 268         .width          = -1,
 269         .height         = -1,
 270         .tim2           = TIM2_BCD,
 271         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 272         .bpp            = 16,
 273 };
 274
 275 static struct clcd_panel sanyo_2_5_in = {
 276         .mode           = {
 277                 .name           = "Sanyo QVGA Portrait",
 278                 .refresh        = 116,
 279                 .xres           = 240,
 280                 .yres           = 320,
 281                 .pixclock       = 100000,
 282                 .left_margin    = 20,
 283                 .right_margin   = 10,
 284                 .upper_margin   = 2,
 285                 .lower_margin   = 2,
 286                 .hsync_len      = 10,
 287                 .vsync_len      = 2,
 288                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 289                 .vmode          = FB_VMODE_NONINTERLACED,
 290         },
 291         .width          = -1,
 292         .height         = -1,
 293         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 294         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 295         .bpp            = 16,
 296 };
 297
 298 static struct clcd_panel epson_2_2_in = {
 299         .mode           = {
 300                 .name           = "Epson QCIF",
 301                 .refresh        = 390,
 302                 .xres           = 176,
 303                 .yres           = 220,
 304                 .pixclock       = 62500,
 305                 .left_margin    = 3,
 306                 .right_margin   = 2,
 307                 .upper_margin   = 1,
 308                 .lower_margin   = 0,
 309                 .hsync_len      = 3,
 310                 .vsync_len      = 2,
 311                 .sync           = 0,
 312                 .vmode          = FB_VMODE_NONINTERLACED,
 313         },
 314         .width          = -1,
 315         .height         = -1,
 316         .tim2           = TIM2_BCD | TIM2_IPC,
 317         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 318         .bpp            = 16,
 319 };
 320
 321 /*
 322  * Detect which LCD panel is connected, and return the appropriate
 323  * clcd_panel structure.  Note: we do not have any information on
 324  * the required timings for the 8.4in panel, so we presently assume
 325  * VGA timings.
 326  */
 327 static struct clcd_panel *realview_clcd_panel(void)
 328 {
 329         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 330         struct clcd_panel *panel = &vga;
 331         u32 val;
 332
 333         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 334         if (val == SYS_CLCD_ID_SANYO_3_8)
 335                 panel = &sanyo_3_8_in;
 336         else if (val == SYS_CLCD_ID_SANYO_2_5)
 337                 panel = &sanyo_2_5_in;
 338         else if (val == SYS_CLCD_ID_EPSON_2_2)
 339                 panel = &epson_2_2_in;
 340         else if (val == SYS_CLCD_ID_VGA)
 341                 panel = &vga;
 342         else {
 343                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 344                         val);
 345                 panel = &vga;
 346         }
 347
 348         return panel;
 349 }
 350
 351 /*
 352  * Disable all display connectors on the interface module.
 353  */
 354 static void realview_clcd_disable(struct clcd_fb *fb)
 355 {
 356         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 357         u32 val;
 358
 359         val = readl(sys_clcd);
 360         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 361         writel(val, sys_clcd);
 362 }
 363
 364 /*
 365  * Enable the relevant connector on the interface module.
 366  */
 367 static void realview_clcd_enable(struct clcd_fb *fb)
 368 {
 369         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 370         u32 val;
 371
 372         /*
 373          * Enable the PSUs
 374          */
 375         val = readl(sys_clcd);
 376         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 377         writel(val, sys_clcd);
 378 }
 379
 380 static unsigned long framesize = SZ_1M;
 381
 382 static int realview_clcd_setup(struct clcd_fb *fb)
 383 {
 384         dma_addr_t dma;
 385
 386         fb->panel               = realview_clcd_panel();
 387
 388         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 389                                                     &dma, GFP_KERNEL);
 390         if (!fb->fb.screen_base) {
 391                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 392                 return -ENOMEM;
 393         }
 394
 395         fb->fb.fix.smem_start   = dma;
 396         fb->fb.fix.smem_len     = framesize;
 397
 398         return 0;
 399 }
 400
 401 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 402 {
 403         return dma_mmap_writecombine(&fb->dev->dev, vma,
 404                                      fb->fb.screen_base,
 405                                      fb->fb.fix.smem_start,
 406                                      fb->fb.fix.smem_len);
 407 }
 408
 409 static void realview_clcd_remove(struct clcd_fb *fb)
 410 {
 411         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 412                               fb->fb.screen_base, fb->fb.fix.smem_start);
 413 }
 414
 415 struct clcd_board clcd_plat_data = {
 416         .name           = "RealView",
 417         .check          = clcdfb_check,
 418         .decode         = clcdfb_decode,
 419         .disable        = realview_clcd_disable,
 420         .enable         = realview_clcd_enable,
 421         .setup          = realview_clcd_setup,
 422         .mmap           = realview_clcd_mmap,
 423         .remove         = realview_clcd_remove,
 424 };
 425
 426 #ifdef CONFIG_LEDS
 427 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 428
 429 void realview_leds_event(led_event_t ledevt)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         local_irq_save(flags);
 435         val = readl(VA_LEDS_BASE);
 436
 437         switch (ledevt) {
 438         case led_idle_start:
 439                 val = val & ~REALVIEW_SYS_LED0;
 440                 break;
 441
 442         case led_idle_end:
 443                 val = val | REALVIEW_SYS_LED0;
 444                 break;
 445
 446         case led_timer:
 447                 val = val ^ REALVIEW_SYS_LED1;
 448                 break;
 449
 450         case led_halted:
 451                 val = 0;
 452                 break;
 453
 454         default:
 455                 break;
 456         }
 457
 458         writel(val, VA_LEDS_BASE);
 459         local_irq_restore(flags);
 460 }
 461 #endif  /* CONFIG_LEDS */
 462
 463 /*
 464  * Where is the timer (VA)?
 465  */
 466 #define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
 467 #define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
 468 #define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
 469 #define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
 470
 471 /*
 472  * How long is the timer interval?
 473  */
 474 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 475 #if TIMER_INTERVAL >= 0x100000
 476 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 477 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 478 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 479 #elif TIMER_INTERVAL >= 0x10000
 480 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 481 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 482 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 483 #else
 484 #define TIMER_RELOAD    (TIMER_INTERVAL)
 485 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 486 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 487 #endif
 488
 489 static void timer_set_mode(enum clock_event_mode mode,
 490                            struct clock_event_device *clk)
 491 {
 492         unsigned long ctrl;
 493
 494         switch(mode) {
 495         case CLOCK_EVT_MODE_PERIODIC:
 496                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 497
 498                 ctrl = TIMER_CTRL_PERIODIC;
 499                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 500                 break;
 501         case CLOCK_EVT_MODE_ONESHOT:
 502                 /* period set, and timer enabled in 'next_event' hook */
 503                 ctrl = TIMER_CTRL_ONESHOT;
 504                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 505                 break;
 506         case CLOCK_EVT_MODE_UNUSED:
 507         case CLOCK_EVT_MODE_SHUTDOWN:
 508         default:
 509                 ctrl = 0;
 510         }
 511
 512         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 513 }
 514
 515 static int timer_set_next_event(unsigned long evt,
 516                                 struct clock_event_device *unused)
 517 {
 518         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 519
 520         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 521         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 522
 523         return 0;
 524 }
 525
 526 static struct clock_event_device timer0_clockevent =     {
 527         .name           = "timer0",
 528         .shift          = 32,
 529         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 530         .set_mode       = timer_set_mode,
 531         .set_next_event = timer_set_next_event,
 532         .rating         = 300,
 533         .irq            = IRQ_TIMERINT0_1,
 534         .cpumask        = CPU_MASK_ALL,
 535 };
 536
 537 static void __init realview_clockevents_init(void)
 538 {
 539         timer0_clockevent.mult =
 540                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 541         timer0_clockevent.max_delta_ns =
 542                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 543         timer0_clockevent.min_delta_ns =
 544                 clockevent_delta2ns(0xf, &timer0_clockevent);
 545
 546         clockevents_register_device(&timer0_clockevent);
 547 }
 548
 549 /*
 550  * IRQ handler for the timer
 551  */
 552 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 553 {
 554         struct clock_event_device *evt = &timer0_clockevent;
 555
 556         /* clear the interrupt */
 557         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 558
 559         evt->event_handler(evt);
 560
 561         return IRQ_HANDLED;
 562 }
 563
 564 static struct irqaction realview_timer_irq = {
 565         .name           = "RealView Timer Tick",
 566         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 567         .handler        = realview_timer_interrupt,
 568 };
 569
 570 static cycle_t realview_get_cycles(void)
 571 {
 572         return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 573 }
 574
 575 static struct clocksource clocksource_realview = {
 576         .name   = "timer3",
 577         .rating = 200,
 578         .read   = realview_get_cycles,
 579         .mask   = CLOCKSOURCE_MASK(32),
 580         .shift  = 20,
 581         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 582 };
 583
 584 static void __init realview_clocksource_init(void)
 585 {
 586         /* setup timer 0 as free-running clocksource */
 587         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 588         writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 589         writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 590         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 591                 TIMER3_VA_BASE + TIMER_CTRL);
 592
 593         clocksource_realview.mult =
 594                 clocksource_khz2mult(1000, clocksource_realview.shift);
 595         clocksource_register(&clocksource_realview);
 596 }
 597
 598 /*
 599  * Set up the clock source and clock events devices
 600  */
 601 static void __init realview_timer_init(void)
 602 {
 603         u32 val;
 604
 605 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 606         /*
 607          * The dummy clock device has to be registered before the main device
 608          * so that the latter will broadcast the clock events
 609          */
 610         local_timer_setup(smp_processor_id());
 611 #endif
 612
 613         /*
 614          * set clock frequency:
 615          *      REALVIEW_REFCLK is 32KHz
 616          *      REALVIEW_TIMCLK is 1MHz
 617          */
 618         val = readl(__io_address(REALVIEW_SCTL_BASE));
 619         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 620                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 621                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 622                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 623                __io_address(REALVIEW_SCTL_BASE));
 624
 625         /*
 626          * Initialise to a known state (all timers off)
 627          */
 628         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 629         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 630         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 631         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 632
 633         /*
 634          * Make irqs happen for the system timer
 635          */
 636         setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
 637
 638         realview_clocksource_init();
 639         realview_clockevents_init();
 640 }
 641
 642 struct sys_timer realview_timer = {
 643         .init           = realview_timer_init,
 644 };