2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
31 #include <asm/system.h>
32 #include <asm/hardware.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
46 #include <asm/hardware/gic.h>
51 #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
53 /* used by entry-macro.S */
54 void __iomem *gic_cpu_base_addr;
57 * This is the RealView sched_clock implementation. This has
58 * a resolution of 41.7ns, and a maximum value of about 179s.
60 unsigned long long sched_clock(void)
64 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
71 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
73 static int realview_flash_init(void)
77 val = __raw_readl(REALVIEW_FLASHCTRL);
78 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
79 __raw_writel(val, REALVIEW_FLASHCTRL);
84 static void realview_flash_exit(void)
88 val = __raw_readl(REALVIEW_FLASHCTRL);
89 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
90 __raw_writel(val, REALVIEW_FLASHCTRL);
93 static void realview_flash_set_vpp(int on)
97 val = __raw_readl(REALVIEW_FLASHCTRL);
99 val |= REALVIEW_FLASHPROG_FLVPPEN;
101 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
102 __raw_writel(val, REALVIEW_FLASHCTRL);
105 static struct flash_platform_data realview_flash_data = {
106 .map_name = "cfi_probe",
108 .init = realview_flash_init,
109 .exit = realview_flash_exit,
110 .set_vpp = realview_flash_set_vpp,
113 static struct resource realview_flash_resource = {
114 .start = REALVIEW_FLASH_BASE,
115 .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
116 .flags = IORESOURCE_MEM,
119 struct platform_device realview_flash_device = {
123 .platform_data = &realview_flash_data,
126 .resource = &realview_flash_resource,
129 static struct resource realview_i2c_resource = {
130 .start = REALVIEW_I2C_BASE,
131 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
132 .flags = IORESOURCE_MEM,
135 struct platform_device realview_i2c_device = {
136 .name = "versatile-i2c",
139 .resource = &realview_i2c_resource,
142 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
144 static unsigned int realview_mmc_status(struct device *dev)
146 struct amba_device *adev = container_of(dev, struct amba_device, dev);
149 if (adev->res.start == REALVIEW_MMCI0_BASE)
154 return readl(REALVIEW_SYSMCI) & mask;
157 struct mmc_platform_data realview_mmc0_plat_data = {
158 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
159 .status = realview_mmc_status,
162 struct mmc_platform_data realview_mmc1_plat_data = {
163 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
164 .status = realview_mmc_status,
170 static const struct icst307_params realview_oscvco_params = {
179 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
181 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
182 void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
185 val = readl(sys_osc) & ~0x7ffff;
186 val |= vco.v | (vco.r << 9) | (vco.s << 16);
188 writel(0xa05f, sys_lock);
189 writel(val, sys_osc);
193 struct clk realview_clcd_clk = {
195 .params = &realview_oscvco_params,
196 .setvco = realview_oscvco_set,
202 #define SYS_CLCD_NLCDIOON (1 << 2)
203 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
204 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
205 #define SYS_CLCD_ID_MASK (0x1f << 8)
206 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
207 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
208 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
209 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
210 #define SYS_CLCD_ID_VGA (0x1f << 8)
212 static struct clcd_panel vga = {
226 .vmode = FB_VMODE_NONINTERLACED,
230 .tim2 = TIM2_BCD | TIM2_IPC,
231 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
235 static struct clcd_panel sanyo_3_8_in = {
237 .name = "Sanyo QVGA",
249 .vmode = FB_VMODE_NONINTERLACED,
254 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
258 static struct clcd_panel sanyo_2_5_in = {
260 .name = "Sanyo QVGA Portrait",
271 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
272 .vmode = FB_VMODE_NONINTERLACED,
276 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
277 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
281 static struct clcd_panel epson_2_2_in = {
283 .name = "Epson QCIF",
295 .vmode = FB_VMODE_NONINTERLACED,
299 .tim2 = TIM2_BCD | TIM2_IPC,
300 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
305 * Detect which LCD panel is connected, and return the appropriate
306 * clcd_panel structure. Note: we do not have any information on
307 * the required timings for the 8.4in panel, so we presently assume
310 static struct clcd_panel *realview_clcd_panel(void)
312 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
313 struct clcd_panel *panel = &vga;
316 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
317 if (val == SYS_CLCD_ID_SANYO_3_8)
318 panel = &sanyo_3_8_in;
319 else if (val == SYS_CLCD_ID_SANYO_2_5)
320 panel = &sanyo_2_5_in;
321 else if (val == SYS_CLCD_ID_EPSON_2_2)
322 panel = &epson_2_2_in;
323 else if (val == SYS_CLCD_ID_VGA)
326 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
335 * Disable all display connectors on the interface module.
337 static void realview_clcd_disable(struct clcd_fb *fb)
339 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
342 val = readl(sys_clcd);
343 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
344 writel(val, sys_clcd);
348 * Enable the relevant connector on the interface module.
350 static void realview_clcd_enable(struct clcd_fb *fb)
352 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
358 val = readl(sys_clcd);
359 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
360 writel(val, sys_clcd);
363 static unsigned long framesize = SZ_1M;
365 static int realview_clcd_setup(struct clcd_fb *fb)
369 fb->panel = realview_clcd_panel();
371 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
373 if (!fb->fb.screen_base) {
374 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
378 fb->fb.fix.smem_start = dma;
379 fb->fb.fix.smem_len = framesize;
384 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
386 return dma_mmap_writecombine(&fb->dev->dev, vma,
388 fb->fb.fix.smem_start,
389 fb->fb.fix.smem_len);
392 static void realview_clcd_remove(struct clcd_fb *fb)
394 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
395 fb->fb.screen_base, fb->fb.fix.smem_start);
398 struct clcd_board clcd_plat_data = {
400 .check = clcdfb_check,
401 .decode = clcdfb_decode,
402 .disable = realview_clcd_disable,
403 .enable = realview_clcd_enable,
404 .setup = realview_clcd_setup,
405 .mmap = realview_clcd_mmap,
406 .remove = realview_clcd_remove,
410 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
412 void realview_leds_event(led_event_t ledevt)
417 local_irq_save(flags);
418 val = readl(VA_LEDS_BASE);
422 val = val & ~REALVIEW_SYS_LED0;
426 val = val | REALVIEW_SYS_LED0;
430 val = val ^ REALVIEW_SYS_LED1;
441 writel(val, VA_LEDS_BASE);
442 local_irq_restore(flags);
444 #endif /* CONFIG_LEDS */
447 * Where is the timer (VA)?
449 #define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
450 #define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
451 #define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
452 #define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
455 * How long is the timer interval?
457 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
458 #if TIMER_INTERVAL >= 0x100000
459 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
460 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
461 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
462 #elif TIMER_INTERVAL >= 0x10000
463 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
464 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
465 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
467 #define TIMER_RELOAD (TIMER_INTERVAL)
468 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
469 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
472 static void timer_set_mode(enum clock_event_mode mode,
473 struct clock_event_device *clk)
478 case CLOCK_EVT_MODE_PERIODIC:
479 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
481 ctrl = TIMER_CTRL_PERIODIC;
482 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
484 case CLOCK_EVT_MODE_ONESHOT:
485 /* period set, and timer enabled in 'next_event' hook */
486 ctrl = TIMER_CTRL_ONESHOT;
487 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
489 case CLOCK_EVT_MODE_UNUSED:
490 case CLOCK_EVT_MODE_SHUTDOWN:
495 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
498 static int timer_set_next_event(unsigned long evt,
499 struct clock_event_device *unused)
501 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
503 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
504 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
509 static struct clock_event_device timer0_clockevent = {
512 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
513 .set_mode = timer_set_mode,
514 .set_next_event = timer_set_next_event,
516 .irq = IRQ_TIMERINT0_1,
517 .cpumask = CPU_MASK_ALL,
520 static void __init realview_clockevents_init(void)
522 timer0_clockevent.mult =
523 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
524 timer0_clockevent.max_delta_ns =
525 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
526 timer0_clockevent.min_delta_ns =
527 clockevent_delta2ns(0xf, &timer0_clockevent);
529 clockevents_register_device(&timer0_clockevent);
533 * IRQ handler for the timer
535 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
537 struct clock_event_device *evt = &timer0_clockevent;
539 /* clear the interrupt */
540 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
542 evt->event_handler(evt);
547 static struct irqaction realview_timer_irq = {
548 .name = "RealView Timer Tick",
549 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
550 .handler = realview_timer_interrupt,
553 static cycle_t realview_get_cycles(void)
555 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
558 static struct clocksource clocksource_realview = {
561 .read = realview_get_cycles,
562 .mask = CLOCKSOURCE_MASK(32),
564 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
567 static void __init realview_clocksource_init(void)
569 /* setup timer 0 as free-running clocksource */
570 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
571 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
572 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
573 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
574 TIMER3_VA_BASE + TIMER_CTRL);
576 clocksource_realview.mult =
577 clocksource_khz2mult(1000, clocksource_realview.shift);
578 clocksource_register(&clocksource_realview);
582 * Set up the clock source and clock events devices
584 static void __init realview_timer_init(void)
588 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
590 * The dummy clock device has to be registered before the main device
591 * so that the latter will broadcast the clock events
593 local_timer_setup(smp_processor_id());
597 * set clock frequency:
598 * REALVIEW_REFCLK is 32KHz
599 * REALVIEW_TIMCLK is 1MHz
601 val = readl(__io_address(REALVIEW_SCTL_BASE));
602 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
603 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
604 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
605 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
606 __io_address(REALVIEW_SCTL_BASE));
609 * Initialise to a known state (all timers off)
611 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
612 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
613 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
614 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
617 * Make irqs happen for the system timer
619 setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
621 realview_clocksource_init();
622 realview_clockevents_init();
625 struct sys_timer realview_timer = {
626 .init = realview_timer_init,