arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/hardware.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst307.h>
  38
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/flash.h>
  41 #include <asm/mach/irq.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/mmc.h>
  45
  46 #include <asm/hardware/gic.h>
  47
  48 #include "core.h"
  49 #include "clock.h"
  50
  51 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  52
  53 /*
  54  * This is the RealView sched_clock implementation.  This has
  55  * a resolution of 41.7ns, and a maximum value of about 179s.
  56  */
  57 unsigned long long sched_clock(void)
  58 {
  59         unsigned long long v;
  60
  61         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  62         do_div(v, 3);
  63
  64         return v;
  65 }
  66
  67
  68 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  69
  70 static int realview_flash_init(void)
  71 {
  72         u32 val;
  73
  74         val = __raw_readl(REALVIEW_FLASHCTRL);
  75         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  76         __raw_writel(val, REALVIEW_FLASHCTRL);
  77
  78         return 0;
  79 }
  80
  81 static void realview_flash_exit(void)
  82 {
  83         u32 val;
  84
  85         val = __raw_readl(REALVIEW_FLASHCTRL);
  86         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  87         __raw_writel(val, REALVIEW_FLASHCTRL);
  88 }
  89
  90 static void realview_flash_set_vpp(int on)
  91 {
  92         u32 val;
  93
  94         val = __raw_readl(REALVIEW_FLASHCTRL);
  95         if (on)
  96                 val |= REALVIEW_FLASHPROG_FLVPPEN;
  97         else
  98                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  99         __raw_writel(val, REALVIEW_FLASHCTRL);
 100 }
 101
 102 static struct flash_platform_data realview_flash_data = {
 103         .map_name               = "cfi_probe",
 104         .width                  = 4,
 105         .init                   = realview_flash_init,
 106         .exit                   = realview_flash_exit,
 107         .set_vpp                = realview_flash_set_vpp,
 108 };
 109
 110 static struct resource realview_flash_resource = {
 111         .start                  = REALVIEW_FLASH_BASE,
 112         .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
 113         .flags                  = IORESOURCE_MEM,
 114 };
 115
 116 struct platform_device realview_flash_device = {
 117         .name                   = "armflash",
 118         .id                     = 0,
 119         .dev                    = {
 120                 .platform_data  = &realview_flash_data,
 121         },
 122         .num_resources          = 1,
 123         .resource               = &realview_flash_resource,
 124 };
 125
 126 static struct resource realview_i2c_resource = {
 127         .start          = REALVIEW_I2C_BASE,
 128         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 129         .flags          = IORESOURCE_MEM,
 130 };
 131
 132 struct platform_device realview_i2c_device = {
 133         .name           = "versatile-i2c",
 134         .id             = -1,
 135         .num_resources  = 1,
 136         .resource       = &realview_i2c_resource,
 137 };
 138
 139 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 140
 141 static unsigned int realview_mmc_status(struct device *dev)
 142 {
 143         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 144         u32 mask;
 145
 146         if (adev->res.start == REALVIEW_MMCI0_BASE)
 147                 mask = 1;
 148         else
 149                 mask = 2;
 150
 151         return readl(REALVIEW_SYSMCI) & mask;
 152 }
 153
 154 struct mmc_platform_data realview_mmc0_plat_data = {
 155         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 156         .status         = realview_mmc_status,
 157 };
 158
 159 struct mmc_platform_data realview_mmc1_plat_data = {
 160         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 161         .status         = realview_mmc_status,
 162 };
 163
 164 /*
 165  * Clock handling
 166  */
 167 static const struct icst307_params realview_oscvco_params = {
 168         .ref            = 24000,
 169         .vco_max        = 200000,
 170         .vd_min         = 4 + 8,
 171         .vd_max         = 511 + 8,
 172         .rd_min         = 1 + 2,
 173         .rd_max         = 127 + 2,
 174 };
 175
 176 static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
 177 {
 178         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 179         void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 180         u32 val;
 181
 182         val = readl(sys_osc) & ~0x7ffff;
 183         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 184
 185         writel(0xa05f, sys_lock);
 186         writel(val, sys_osc);
 187         writel(0, sys_lock);
 188 }
 189
 190 struct clk realview_clcd_clk = {
 191         .name   = "CLCDCLK",
 192         .params = &realview_oscvco_params,
 193         .setvco = realview_oscvco_set,
 194 };
 195
 196 /*
 197  * CLCD support.
 198  */
 199 #define SYS_CLCD_NLCDIOON       (1 << 2)
 200 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 201 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 202 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 203 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 204 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 205 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 206 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 207 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 208
 209 static struct clcd_panel vga = {
 210         .mode           = {
 211                 .name           = "VGA",
 212                 .refresh        = 60,
 213                 .xres           = 640,
 214                 .yres           = 480,
 215                 .pixclock       = 39721,
 216                 .left_margin    = 40,
 217                 .right_margin   = 24,
 218                 .upper_margin   = 32,
 219                 .lower_margin   = 11,
 220                 .hsync_len      = 96,
 221                 .vsync_len      = 2,
 222                 .sync           = 0,
 223                 .vmode          = FB_VMODE_NONINTERLACED,
 224         },
 225         .width          = -1,
 226         .height         = -1,
 227         .tim2           = TIM2_BCD | TIM2_IPC,
 228         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 229         .bpp            = 16,
 230 };
 231
 232 static struct clcd_panel sanyo_3_8_in = {
 233         .mode           = {
 234                 .name           = "Sanyo QVGA",
 235                 .refresh        = 116,
 236                 .xres           = 320,
 237                 .yres           = 240,
 238                 .pixclock       = 100000,
 239                 .left_margin    = 6,
 240                 .right_margin   = 6,
 241                 .upper_margin   = 5,
 242                 .lower_margin   = 5,
 243                 .hsync_len      = 6,
 244                 .vsync_len      = 6,
 245                 .sync           = 0,
 246                 .vmode          = FB_VMODE_NONINTERLACED,
 247         },
 248         .width          = -1,
 249         .height         = -1,
 250         .tim2           = TIM2_BCD,
 251         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 252         .bpp            = 16,
 253 };
 254
 255 static struct clcd_panel sanyo_2_5_in = {
 256         .mode           = {
 257                 .name           = "Sanyo QVGA Portrait",
 258                 .refresh        = 116,
 259                 .xres           = 240,
 260                 .yres           = 320,
 261                 .pixclock       = 100000,
 262                 .left_margin    = 20,
 263                 .right_margin   = 10,
 264                 .upper_margin   = 2,
 265                 .lower_margin   = 2,
 266                 .hsync_len      = 10,
 267                 .vsync_len      = 2,
 268                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 269                 .vmode          = FB_VMODE_NONINTERLACED,
 270         },
 271         .width          = -1,
 272         .height         = -1,
 273         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 274         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 275         .bpp            = 16,
 276 };
 277
 278 static struct clcd_panel epson_2_2_in = {
 279         .mode           = {
 280                 .name           = "Epson QCIF",
 281                 .refresh        = 390,
 282                 .xres           = 176,
 283                 .yres           = 220,
 284                 .pixclock       = 62500,
 285                 .left_margin    = 3,
 286                 .right_margin   = 2,
 287                 .upper_margin   = 1,
 288                 .lower_margin   = 0,
 289                 .hsync_len      = 3,
 290                 .vsync_len      = 2,
 291                 .sync           = 0,
 292                 .vmode          = FB_VMODE_NONINTERLACED,
 293         },
 294         .width          = -1,
 295         .height         = -1,
 296         .tim2           = TIM2_BCD | TIM2_IPC,
 297         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 298         .bpp            = 16,
 299 };
 300
 301 /*
 302  * Detect which LCD panel is connected, and return the appropriate
 303  * clcd_panel structure.  Note: we do not have any information on
 304  * the required timings for the 8.4in panel, so we presently assume
 305  * VGA timings.
 306  */
 307 static struct clcd_panel *realview_clcd_panel(void)
 308 {
 309         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 310         struct clcd_panel *panel = &vga;
 311         u32 val;
 312
 313         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 314         if (val == SYS_CLCD_ID_SANYO_3_8)
 315                 panel = &sanyo_3_8_in;
 316         else if (val == SYS_CLCD_ID_SANYO_2_5)
 317                 panel = &sanyo_2_5_in;
 318         else if (val == SYS_CLCD_ID_EPSON_2_2)
 319                 panel = &epson_2_2_in;
 320         else if (val == SYS_CLCD_ID_VGA)
 321                 panel = &vga;
 322         else {
 323                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 324                         val);
 325                 panel = &vga;
 326         }
 327
 328         return panel;
 329 }
 330
 331 /*
 332  * Disable all display connectors on the interface module.
 333  */
 334 static void realview_clcd_disable(struct clcd_fb *fb)
 335 {
 336         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 337         u32 val;
 338
 339         val = readl(sys_clcd);
 340         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 341         writel(val, sys_clcd);
 342 }
 343
 344 /*
 345  * Enable the relevant connector on the interface module.
 346  */
 347 static void realview_clcd_enable(struct clcd_fb *fb)
 348 {
 349         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 350         u32 val;
 351
 352         /*
 353          * Enable the PSUs
 354          */
 355         val = readl(sys_clcd);
 356         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 357         writel(val, sys_clcd);
 358 }
 359
 360 static unsigned long framesize = SZ_1M;
 361
 362 static int realview_clcd_setup(struct clcd_fb *fb)
 363 {
 364         dma_addr_t dma;
 365
 366         fb->panel               = realview_clcd_panel();
 367
 368         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 369                                                     &dma, GFP_KERNEL);
 370         if (!fb->fb.screen_base) {
 371                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 372                 return -ENOMEM;
 373         }
 374
 375         fb->fb.fix.smem_start   = dma;
 376         fb->fb.fix.smem_len     = framesize;
 377
 378         return 0;
 379 }
 380
 381 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 382 {
 383         return dma_mmap_writecombine(&fb->dev->dev, vma,
 384                                      fb->fb.screen_base,
 385                                      fb->fb.fix.smem_start,
 386                                      fb->fb.fix.smem_len);
 387 }
 388
 389 static void realview_clcd_remove(struct clcd_fb *fb)
 390 {
 391         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 392                               fb->fb.screen_base, fb->fb.fix.smem_start);
 393 }
 394
 395 struct clcd_board clcd_plat_data = {
 396         .name           = "RealView",
 397         .check          = clcdfb_check,
 398         .decode         = clcdfb_decode,
 399         .disable        = realview_clcd_disable,
 400         .enable         = realview_clcd_enable,
 401         .setup          = realview_clcd_setup,
 402         .mmap           = realview_clcd_mmap,
 403         .remove         = realview_clcd_remove,
 404 };
 405
 406 #ifdef CONFIG_LEDS
 407 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 408
 409 void realview_leds_event(led_event_t ledevt)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         local_irq_save(flags);
 415         val = readl(VA_LEDS_BASE);
 416
 417         switch (ledevt) {
 418         case led_idle_start:
 419                 val = val & ~REALVIEW_SYS_LED0;
 420                 break;
 421
 422         case led_idle_end:
 423                 val = val | REALVIEW_SYS_LED0;
 424                 break;
 425
 426         case led_timer:
 427                 val = val ^ REALVIEW_SYS_LED1;
 428                 break;
 429
 430         case led_halted:
 431                 val = 0;
 432                 break;
 433
 434         default:
 435                 break;
 436         }
 437
 438         writel(val, VA_LEDS_BASE);
 439         local_irq_restore(flags);
 440 }
 441 #endif  /* CONFIG_LEDS */
 442
 443 /*
 444  * Where is the timer (VA)?
 445  */
 446 #define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
 447 #define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
 448 #define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
 449 #define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
 450
 451 /*
 452  * How long is the timer interval?
 453  */
 454 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 455 #if TIMER_INTERVAL >= 0x100000
 456 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 457 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 458 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 459 #elif TIMER_INTERVAL >= 0x10000
 460 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 461 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 462 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 463 #else
 464 #define TIMER_RELOAD    (TIMER_INTERVAL)
 465 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 466 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 467 #endif
 468
 469 static void timer_set_mode(enum clock_event_mode mode,
 470                            struct clock_event_device *clk)
 471 {
 472         unsigned long ctrl;
 473
 474         switch(mode) {
 475         case CLOCK_EVT_MODE_PERIODIC:
 476                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 477
 478                 ctrl = TIMER_CTRL_PERIODIC;
 479                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 480                 break;
 481         case CLOCK_EVT_MODE_ONESHOT:
 482                 /* period set, and timer enabled in 'next_event' hook */
 483                 ctrl = TIMER_CTRL_ONESHOT;
 484                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 485                 break;
 486         case CLOCK_EVT_MODE_UNUSED:
 487         case CLOCK_EVT_MODE_SHUTDOWN:
 488         default:
 489                 ctrl = 0;
 490         }
 491
 492         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 493 }
 494
 495 static int timer_set_next_event(unsigned long evt,
 496                                 struct clock_event_device *unused)
 497 {
 498         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 499
 500         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 501         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 502
 503         return 0;
 504 }
 505
 506 static struct clock_event_device timer0_clockevent =     {
 507         .name           = "timer0",
 508         .shift          = 32,
 509         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 510         .set_mode       = timer_set_mode,
 511         .set_next_event = timer_set_next_event,
 512         .rating         = 300,
 513         .irq            = IRQ_TIMERINT0_1,
 514         .cpumask        = CPU_MASK_ALL,
 515 };
 516
 517 static void __init realview_clockevents_init(void)
 518 {
 519         timer0_clockevent.mult =
 520                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 521         timer0_clockevent.max_delta_ns =
 522                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 523         timer0_clockevent.min_delta_ns =
 524                 clockevent_delta2ns(0xf, &timer0_clockevent);
 525
 526         clockevents_register_device(&timer0_clockevent);
 527 }
 528
 529 /*
 530  * IRQ handler for the timer
 531  */
 532 static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
 533 {
 534         struct clock_event_device *evt = &timer0_clockevent;
 535
 536         /* clear the interrupt */
 537         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 538
 539         evt->event_handler(evt);
 540
 541         return IRQ_HANDLED;
 542 }
 543
 544 static struct irqaction realview_timer_irq = {
 545         .name           = "RealView Timer Tick",
 546         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 547         .handler        = realview_timer_interrupt,
 548 };
 549
 550 static cycle_t realview_get_cycles(void)
 551 {
 552         return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 553 }
 554
 555 static struct clocksource clocksource_realview = {
 556         .name   = "timer3",
 557         .rating = 200,
 558         .read   = realview_get_cycles,
 559         .mask   = CLOCKSOURCE_MASK(32),
 560         .shift  = 20,
 561         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 562 };
 563
 564 static void __init realview_clocksource_init(void)
 565 {
 566         /* setup timer 0 as free-running clocksource */
 567         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 568         writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 569         writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 570         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 571                 TIMER3_VA_BASE + TIMER_CTRL);
 572
 573         clocksource_realview.mult =
 574                 clocksource_khz2mult(1000, clocksource_realview.shift);
 575         clocksource_register(&clocksource_realview);
 576 }
 577
 578 /*
 579  * Set up the clock source and clock events devices
 580  */
 581 static void __init realview_timer_init(void)
 582 {
 583         u32 val;
 584
 585 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 586         /*
 587          * The dummy clock device has to be registered before the main device
 588          * so that the latter will broadcast the clock events
 589          */
 590         local_timer_setup(smp_processor_id());
 591 #endif
 592
 593         /*
 594          * set clock frequency:
 595          *      REALVIEW_REFCLK is 32KHz
 596          *      REALVIEW_TIMCLK is 1MHz
 597          */
 598         val = readl(__io_address(REALVIEW_SCTL_BASE));
 599         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 600                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 601                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 602                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 603                __io_address(REALVIEW_SCTL_BASE));
 604
 605         /*
 606          * Initialise to a known state (all timers off)
 607          */
 608         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 609         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 610         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 611         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 612
 613         /*
 614          * Make irqs happen for the system timer
 615          */
 616         setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
 617
 618         realview_clocksource_init();
 619         realview_clockevents_init();
 620 }
 621
 622 struct sys_timer realview_timer = {
 623         .init           = realview_timer_init,
 624 };