2 * arch/arm/mach-pxa/time.c
4 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/clockchips.h>
20 #include <asm/mach/irq.h>
21 #include <asm/mach/time.h>
22 #include <asm/arch/pxa-regs.h>
25 pxa_ost0_interrupt(int irq, void *dev_id)
28 struct clock_event_device *c = dev_id;
30 if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
31 /* Disarm the compare/match, signal the event. */
34 } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
35 /* Call the event handler as many times as necessary
36 * to recover missed events, if any (if we update
37 * OSMR0 and OSCR0 is still ahead of us, we've missed
38 * the event). As we're dealing with that, re-arm the
39 * compare/match for the next event.
43 * There's a latency between the instruction that
44 * writes to OSMR0 and the actual commit to the
45 * physical hardware, because the CPU doesn't (have
46 * to) run at bus speed, there's a write buffer
47 * between the CPU and the bus, etc. etc. So if the
48 * target OSCR0 is "very close", to the OSMR0 load
49 * value, the update to OSMR0 might not get to the
50 * hardware in time and we'll miss that interrupt.
52 * To be safe, if the new OSMR0 is "very close" to the
53 * target OSCR0 value, we call the event_handler as
54 * though the event actually happened. According to
55 * Nico's comment in the previous version of this
56 * code, experience has shown that 6 OSCR ticks is
57 * "very close" but he went with 8. We will use 16,
58 * based on the results of testing on PXA270.
60 * To be doubly sure, we also tell clkevt via
61 * clockevents_register_device() not to ask for
62 * anything that might put us "very close".
64 #define MIN_OSCR_DELTA 16
67 next_match = (OSMR0 += LATCH);
69 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
70 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
77 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
79 unsigned long irqflags;
81 raw_local_irq_save(irqflags);
85 raw_local_irq_restore(irqflags);
90 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
92 unsigned long irqflags;
95 case CLOCK_EVT_MODE_PERIODIC:
96 raw_local_irq_save(irqflags);
100 raw_local_irq_restore(irqflags);
103 case CLOCK_EVT_MODE_ONESHOT:
104 raw_local_irq_save(irqflags);
106 raw_local_irq_restore(irqflags);
109 case CLOCK_EVT_MODE_UNUSED:
110 case CLOCK_EVT_MODE_SHUTDOWN:
111 /* initializing, released, or preparing for suspend */
112 raw_local_irq_save(irqflags);
114 raw_local_irq_restore(irqflags);
119 static struct clock_event_device ckevt_pxa_osmr0 = {
121 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
124 .cpumask = CPU_MASK_CPU0,
125 .set_next_event = pxa_osmr0_set_next_event,
126 .set_mode = pxa_osmr0_set_mode,
129 static cycle_t pxa_read_oscr(void)
134 static struct clocksource cksrc_pxa_oscr0 = {
137 .read = pxa_read_oscr,
138 .mask = CLOCKSOURCE_MASK(32),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
143 static struct irqaction pxa_ost0_irq = {
145 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
146 .handler = pxa_ost0_interrupt,
147 .dev_id = &ckevt_pxa_osmr0,
150 static void __init pxa_timer_init(void)
153 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
155 ckevt_pxa_osmr0.mult =
156 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
157 ckevt_pxa_osmr0.max_delta_ns =
158 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
159 ckevt_pxa_osmr0.min_delta_ns =
160 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
162 cksrc_pxa_oscr0.mult =
163 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
165 setup_irq(IRQ_OST0, &pxa_ost0_irq);
167 clocksource_register(&cksrc_pxa_oscr0);
168 clockevents_register_device(&ckevt_pxa_osmr0);
172 static unsigned long osmr[4], oier;
174 static void pxa_timer_suspend(void)
183 static void pxa_timer_resume(void)
192 * OSCR0 is the system timer, which has to increase
193 * monotonically until it rolls over in hardware. The value
194 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
195 * which is a handy value to restore to OSCR0.
197 OSCR = OSMR0 - LATCH;
200 #define pxa_timer_suspend NULL
201 #define pxa_timer_resume NULL
204 struct sys_timer pxa_timer = {
205 .init = pxa_timer_init,
206 .suspend = pxa_timer_suspend,
207 .resume = pxa_timer_resume,