arch/arm/mach-pxa/lpd270.c

   1 /*
   2  * linux/arch/arm/mach-pxa/lpd270.c
   3  *
   4  * Support for the LogicPD PXA270 Card Engine.
   5  * Derived from the mainstone code, which carries these notices:
   6  *
   7  * Author:      Nicolas Pitre
   8  * Created:     Nov 05, 2002
   9  * Copyright:   MontaVista Software Inc.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/sched.h>
  21 #include <linux/bitops.h>
  22 #include <linux/fb.h>
  23 #include <linux/ioport.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/pwm_backlight.h>
  27
  28 #include <asm/types.h>
  29 #include <asm/setup.h>
  30 #include <asm/memory.h>
  31 #include <asm/mach-types.h>
  32 #include <asm/hardware.h>
  33 #include <asm/irq.h>
  34 #include <asm/sizes.h>
  35
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/mach/flash.h>
  40
  41 #include <asm/arch/pxa-regs.h>
  42 #include <asm/arch/pxa2xx-regs.h>
  43 #include <asm/arch/pxa2xx-gpio.h>
  44 #include <asm/arch/lpd270.h>
  45 #include <asm/arch/audio.h>
  46 #include <asm/arch/pxafb.h>
  47 #include <asm/arch/mmc.h>
  48 #include <asm/arch/irda.h>
  49 #include <asm/arch/ohci.h>
  50
  51 #include "generic.h"
  52 #include "devices.h"
  53
  54
  55 static unsigned int lpd270_irq_enabled;
  56
  57 static void lpd270_mask_irq(unsigned int irq)
  58 {
  59         int lpd270_irq = irq - LPD270_IRQ(0);
  60
  61         __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  62
  63         lpd270_irq_enabled &= ~(1 << lpd270_irq);
  64         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  65 }
  66
  67 static void lpd270_unmask_irq(unsigned int irq)
  68 {
  69         int lpd270_irq = irq - LPD270_IRQ(0);
  70
  71         lpd270_irq_enabled |= 1 << lpd270_irq;
  72         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  73 }
  74
  75 static struct irq_chip lpd270_irq_chip = {
  76         .name           = "CPLD",
  77         .ack            = lpd270_mask_irq,
  78         .mask           = lpd270_mask_irq,
  79         .unmask         = lpd270_unmask_irq,
  80 };
  81
  82 static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
  83 {
  84         unsigned long pending;
  85
  86         pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  87         do {
  88                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
  89                 if (likely(pending)) {
  90                         irq = LPD270_IRQ(0) + __ffs(pending);
  91                         desc = irq_desc + irq;
  92                         desc_handle_irq(irq, desc);
  93
  94                         pending = __raw_readw(LPD270_INT_STATUS) &
  95                                                 lpd270_irq_enabled;
  96                 }
  97         } while (pending);
  98 }
  99
 100 static void __init lpd270_init_irq(void)
 101 {
 102         int irq;
 103
 104         pxa27x_init_irq();
 105
 106         __raw_writew(0, LPD270_INT_MASK);
 107         __raw_writew(0, LPD270_INT_STATUS);
 108
 109         /* setup extra LogicPD PXA270 irqs */
 110         for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
 111                 set_irq_chip(irq, &lpd270_irq_chip);
 112                 set_irq_handler(irq, handle_level_irq);
 113                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 114         }
 115         set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
 116         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
 117 }
 118
 119
 120 #ifdef CONFIG_PM
 121 static int lpd270_irq_resume(struct sys_device *dev)
 122 {
 123         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
 124         return 0;
 125 }
 126
 127 static struct sysdev_class lpd270_irq_sysclass = {
 128         .name = "cpld_irq",
 129         .resume = lpd270_irq_resume,
 130 };
 131
 132 static struct sys_device lpd270_irq_device = {
 133         .cls = &lpd270_irq_sysclass,
 134 };
 135
 136 static int __init lpd270_irq_device_init(void)
 137 {
 138         int ret = -ENODEV;
 139         if (machine_is_logicpd_pxa270()) {
 140                 ret = sysdev_class_register(&lpd270_irq_sysclass);
 141                 if (ret == 0)
 142                         ret = sysdev_register(&lpd270_irq_device);
 143         }
 144         return ret;
 145 }
 146
 147 device_initcall(lpd270_irq_device_init);
 148 #endif
 149
 150
 151 static struct resource smc91x_resources[] = {
 152         [0] = {
 153                 .start  = LPD270_ETH_PHYS,
 154                 .end    = (LPD270_ETH_PHYS + 0xfffff),
 155                 .flags  = IORESOURCE_MEM,
 156         },
 157         [1] = {
 158                 .start  = LPD270_ETHERNET_IRQ,
 159                 .end    = LPD270_ETHERNET_IRQ,
 160                 .flags  = IORESOURCE_IRQ,
 161         },
 162 };
 163
 164 static struct platform_device smc91x_device = {
 165         .name           = "smc91x",
 166         .id             = 0,
 167         .num_resources  = ARRAY_SIZE(smc91x_resources),
 168         .resource       = smc91x_resources,
 169 };
 170
 171 static struct platform_device lpd270_audio_device = {
 172         .name           = "pxa2xx-ac97",
 173         .id             = -1,
 174 };
 175
 176 static struct resource lpd270_flash_resources[] = {
 177         [0] = {
 178                 .start  = PXA_CS0_PHYS,
 179                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
 180                 .flags  = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start  = PXA_CS1_PHYS,
 184                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187 };
 188
 189 static struct mtd_partition lpd270_flash0_partitions[] = {
 190         {
 191                 .name =         "Bootloader",
 192                 .size =         0x00040000,
 193                 .offset =       0,
 194                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
 195         }, {
 196                 .name =         "Kernel",
 197                 .size =         0x00400000,
 198                 .offset =       0x00040000,
 199         }, {
 200                 .name =         "Filesystem",
 201                 .size =         MTDPART_SIZ_FULL,
 202                 .offset =       0x00440000
 203         },
 204 };
 205
 206 static struct flash_platform_data lpd270_flash_data[2] = {
 207         {
 208                 .name           = "processor-flash",
 209                 .map_name       = "cfi_probe",
 210                 .parts          = lpd270_flash0_partitions,
 211                 .nr_parts       = ARRAY_SIZE(lpd270_flash0_partitions),
 212         }, {
 213                 .name           = "mainboard-flash",
 214                 .map_name       = "cfi_probe",
 215                 .parts          = NULL,
 216                 .nr_parts       = 0,
 217         }
 218 };
 219
 220 static struct platform_device lpd270_flash_device[2] = {
 221         {
 222                 .name           = "pxa2xx-flash",
 223                 .id             = 0,
 224                 .dev = {
 225                         .platform_data  = &lpd270_flash_data[0],
 226                 },
 227                 .resource       = &lpd270_flash_resources[0],
 228                 .num_resources  = 1,
 229         }, {
 230                 .name           = "pxa2xx-flash",
 231                 .id             = 1,
 232                 .dev = {
 233                         .platform_data  = &lpd270_flash_data[1],
 234                 },
 235                 .resource       = &lpd270_flash_resources[1],
 236                 .num_resources  = 1,
 237         },
 238 };
 239
 240 static struct platform_pwm_backlight_data lpd270_backlight_data = {
 241         .pwm_id         = 0,
 242         .max_brightness = 1,
 243         .dft_brightness = 1,
 244         .pwm_period_ns  = 78770,
 245 };
 246
 247 static struct platform_device lpd270_backlight_device = {
 248         .name           = "pwm-backlight",
 249         .dev            = {
 250                 .parent = &pxa27x_device_pwm0.dev,
 251                 .platform_data = &lpd270_backlight_data,
 252         },
 253 };
 254
 255 /* 5.7" TFT QVGA (LoLo display number 1) */
 256 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
 257         .pixclock               = 150000,
 258         .xres                   = 320,
 259         .yres                   = 240,
 260         .bpp                    = 16,
 261         .hsync_len              = 0x14,
 262         .left_margin            = 0x28,
 263         .right_margin           = 0x0a,
 264         .vsync_len              = 0x02,
 265         .upper_margin           = 0x08,
 266         .lower_margin           = 0x14,
 267         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 268 };
 269
 270 static struct pxafb_mach_info sharp_lq057q3dc02 = {
 271         .modes                  = &sharp_lq057q3dc02_mode,
 272         .num_modes              = 1,
 273         .lccr0                  = 0x07800080,
 274         .lccr3                  = 0x00400000,
 275 };
 276
 277 /* 12.1" TFT SVGA (LoLo display number 2) */
 278 static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
 279         .pixclock               = 50000,
 280         .xres                   = 800,
 281         .yres                   = 600,
 282         .bpp                    = 16,
 283         .hsync_len              = 0x05,
 284         .left_margin            = 0x52,
 285         .right_margin           = 0x05,
 286         .vsync_len              = 0x04,
 287         .upper_margin           = 0x14,
 288         .lower_margin           = 0x0a,
 289         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 290 };
 291
 292 static struct pxafb_mach_info sharp_lq121s1dg31 = {
 293         .modes                  = &sharp_lq121s1dg31_mode,
 294         .num_modes              = 1,
 295         .lccr0                  = 0x07800080,
 296         .lccr3                  = 0x00400000,
 297 };
 298
 299 /* 3.6" TFT QVGA (LoLo display number 3) */
 300 static struct pxafb_mode_info sharp_lq036q1da01_mode = {
 301         .pixclock               = 150000,
 302         .xres                   = 320,
 303         .yres                   = 240,
 304         .bpp                    = 16,
 305         .hsync_len              = 0x0e,
 306         .left_margin            = 0x04,
 307         .right_margin           = 0x0a,
 308         .vsync_len              = 0x03,
 309         .upper_margin           = 0x03,
 310         .lower_margin           = 0x03,
 311         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 312 };
 313
 314 static struct pxafb_mach_info sharp_lq036q1da01 = {
 315         .modes                  = &sharp_lq036q1da01_mode,
 316         .num_modes              = 1,
 317         .lccr0                  = 0x07800080,
 318         .lccr3                  = 0x00400000,
 319 };
 320
 321 /* 6.4" TFT VGA (LoLo display number 5) */
 322 static struct pxafb_mode_info sharp_lq64d343_mode = {
 323         .pixclock               = 25000,
 324         .xres                   = 640,
 325         .yres                   = 480,
 326         .bpp                    = 16,
 327         .hsync_len              = 0x31,
 328         .left_margin            = 0x89,
 329         .right_margin           = 0x19,
 330         .vsync_len              = 0x12,
 331         .upper_margin           = 0x22,
 332         .lower_margin           = 0x00,
 333         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 334 };
 335
 336 static struct pxafb_mach_info sharp_lq64d343 = {
 337         .modes                  = &sharp_lq64d343_mode,
 338         .num_modes              = 1,
 339         .lccr0                  = 0x07800080,
 340         .lccr3                  = 0x00400000,
 341 };
 342
 343 /* 10.4" TFT VGA (LoLo display number 7) */
 344 static struct pxafb_mode_info sharp_lq10d368_mode = {
 345         .pixclock               = 25000,
 346         .xres                   = 640,
 347         .yres                   = 480,
 348         .bpp                    = 16,
 349         .hsync_len              = 0x31,
 350         .left_margin            = 0x89,
 351         .right_margin           = 0x19,
 352         .vsync_len              = 0x12,
 353         .upper_margin           = 0x22,
 354         .lower_margin           = 0x00,
 355         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 356 };
 357
 358 static struct pxafb_mach_info sharp_lq10d368 = {
 359         .modes                  = &sharp_lq10d368_mode,
 360         .num_modes              = 1,
 361         .lccr0                  = 0x07800080,
 362         .lccr3                  = 0x00400000,
 363 };
 364
 365 /* 3.5" TFT QVGA (LoLo display number 8) */
 366 static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
 367         .pixclock               = 150000,
 368         .xres                   = 240,
 369         .yres                   = 320,
 370         .bpp                    = 16,
 371         .hsync_len              = 0x0e,
 372         .left_margin            = 0x0a,
 373         .right_margin           = 0x0a,
 374         .vsync_len              = 0x03,
 375         .upper_margin           = 0x05,
 376         .lower_margin           = 0x14,
 377         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 378 };
 379
 380 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
 381         .modes                  = &sharp_lq035q7db02_20_mode,
 382         .num_modes              = 1,
 383         .lccr0                  = 0x07800080,
 384         .lccr3                  = 0x00400000,
 385 };
 386
 387 static struct pxafb_mach_info *lpd270_lcd_to_use;
 388
 389 static int __init lpd270_set_lcd(char *str)
 390 {
 391         if (!strnicmp(str, "lq057q3dc02", 11)) {
 392                 lpd270_lcd_to_use = &sharp_lq057q3dc02;
 393         } else if (!strnicmp(str, "lq121s1dg31", 11)) {
 394                 lpd270_lcd_to_use = &sharp_lq121s1dg31;
 395         } else if (!strnicmp(str, "lq036q1da01", 11)) {
 396                 lpd270_lcd_to_use = &sharp_lq036q1da01;
 397         } else if (!strnicmp(str, "lq64d343", 8)) {
 398                 lpd270_lcd_to_use = &sharp_lq64d343;
 399         } else if (!strnicmp(str, "lq10d368", 8)) {
 400                 lpd270_lcd_to_use = &sharp_lq10d368;
 401         } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
 402                 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
 403         } else {
 404                 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
 405         }
 406
 407         return 1;
 408 }
 409
 410 __setup("lcd=", lpd270_set_lcd);
 411
 412 static struct platform_device *platform_devices[] __initdata = {
 413         &smc91x_device,
 414         &lpd270_backlight_device,
 415         &lpd270_audio_device,
 416         &lpd270_flash_device[0],
 417         &lpd270_flash_device[1],
 418 };
 419
 420 static int lpd270_ohci_init(struct device *dev)
 421 {
 422         /* setup Port1 GPIO pin. */
 423         pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN);   /* USBHPWR1 */
 424         pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT);  /* USBHPEN1 */
 425
 426         /* Set the Power Control Polarity Low and Power Sense
 427            Polarity Low to active low. */
 428         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
 429                 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
 430
 431         return 0;
 432 }
 433
 434 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
 435         .port_mode      = PMM_PERPORT_MODE,
 436         .init           = lpd270_ohci_init,
 437 };
 438
 439 static void __init lpd270_init(void)
 440 {
 441         lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
 442         lpd270_flash_data[1].width = 4;
 443
 444         /*
 445          * System bus arbiter setting:
 446          * - Core_Park
 447          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
 448          */
 449         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 450
 451         /*
 452          * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
 453          */
 454         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
 455         pxa_gpio_mode(GPIO16_PWM0_MD);
 456
 457         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 458
 459         if (lpd270_lcd_to_use != NULL)
 460                 set_pxa_fb_info(lpd270_lcd_to_use);
 461
 462         pxa_set_ohci_info(&lpd270_ohci_platform_data);
 463 }
 464
 465
 466 static struct map_desc lpd270_io_desc[] __initdata = {
 467         {
 468                 .virtual        = LPD270_CPLD_VIRT,
 469                 .pfn            = __phys_to_pfn(LPD270_CPLD_PHYS),
 470                 .length         = LPD270_CPLD_SIZE,
 471                 .type           = MT_DEVICE,
 472         },
 473 };
 474
 475 static void __init lpd270_map_io(void)
 476 {
 477         pxa_map_io();
 478         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
 479
 480         /* initialize sleep mode regs (wake-up sources, etc) */
 481         PGSR0 = 0x00008800;
 482         PGSR1 = 0x00000002;
 483         PGSR2 = 0x0001FC00;
 484         PGSR3 = 0x00001F81;
 485         PWER  = 0xC0000002;
 486         PRER  = 0x00000002;
 487         PFER  = 0x00000002;
 488
 489         /* for use I SRAM as framebuffer.  */
 490         PSLR |= 0x00000F04;
 491         PCFR  = 0x00000066;
 492 }
 493
 494 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
 495         /* Maintainer: Peter Barada */
 496         .phys_io        = 0x40000000,
 497         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
 498         .boot_params    = 0xa0000100,
 499         .map_io         = lpd270_map_io,
 500         .init_irq       = lpd270_init_irq,
 501         .timer          = &pxa_timer,
 502         .init_machine   = lpd270_init,
 503 MACHINE_END