2 * linux/arch/arm/mach-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/sysdev.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/pxa-regs.h>
28 struct pxa_gpio_chip {
29 struct gpio_chip chip;
30 void __iomem *regbase;
36 * Configure pins for GPIO or other functions
38 int pxa_gpio_mode(int gpio_mode)
41 int gpio = gpio_mode & GPIO_MD_MASK_NR;
42 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
45 if (gpio > pxa_last_gpio)
48 local_irq_save(flags);
49 if (gpio_mode & GPIO_DFLT_LOW)
50 GPCR(gpio) = GPIO_bit(gpio);
51 else if (gpio_mode & GPIO_DFLT_HIGH)
52 GPSR(gpio) = GPIO_bit(gpio);
53 if (gpio_mode & GPIO_MD_MASK_DIR)
54 GPDR(gpio) |= GPIO_bit(gpio);
56 GPDR(gpio) &= ~GPIO_bit(gpio);
57 gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
58 GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
59 local_irq_restore(flags);
63 EXPORT_SYMBOL(pxa_gpio_mode);
65 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
68 u32 mask = 1 << offset;
70 struct pxa_gpio_chip *pxa;
73 pxa = container_of(chip, struct pxa_gpio_chip, chip);
74 gpdr = pxa->regbase + GPDR_OFFSET;
75 local_irq_save(flags);
76 value = __raw_readl(gpdr);
78 __raw_writel(value, gpdr);
79 local_irq_restore(flags);
84 static int pxa_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
88 u32 mask = 1 << offset;
90 struct pxa_gpio_chip *pxa;
93 pxa = container_of(chip, struct pxa_gpio_chip, chip);
95 pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
96 gpdr = pxa->regbase + GPDR_OFFSET;
97 local_irq_save(flags);
98 tmp = __raw_readl(gpdr);
100 __raw_writel(tmp, gpdr);
101 local_irq_restore(flags);
109 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
111 u32 mask = 1 << offset;
112 struct pxa_gpio_chip *pxa;
114 pxa = container_of(chip, struct pxa_gpio_chip, chip);
115 return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
119 * Set output GPIO level
121 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
123 u32 mask = 1 << offset;
124 struct pxa_gpio_chip *pxa;
126 pxa = container_of(chip, struct pxa_gpio_chip, chip);
129 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
131 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
134 #define GPIO_CHIP(_n) \
136 .regbase = GPIO##_n##_BASE, \
138 .label = "gpio-" #_n, \
139 .direction_input = pxa_gpio_direction_input, \
140 .direction_output = pxa_gpio_direction_output, \
141 .get = pxa_gpio_get, \
142 .set = pxa_gpio_set, \
148 static struct pxa_gpio_chip pxa_gpio_chip[] = {
152 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
158 * PXA GPIO edge detection for IRQs:
159 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
160 * Use this instead of directly setting GRER/GFER.
163 static long GPIO_IRQ_rising_edge[4];
164 static long GPIO_IRQ_falling_edge[4];
165 static long GPIO_IRQ_mask[4];
167 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
171 gpio = IRQ_TO_GPIO(irq);
174 if (type == IRQ_TYPE_PROBE) {
175 /* Don't mess with enabled GPIOs using preconfigured edges or
176 * GPIOs set to alternate function or to output during probe
178 if ((GPIO_IRQ_rising_edge[idx] |
179 GPIO_IRQ_falling_edge[idx] |
180 GPDR(gpio)) & GPIO_bit(gpio))
182 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
184 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
187 pxa_gpio_mode(gpio | GPIO_IN);
189 if (type & IRQ_TYPE_EDGE_RISING)
190 __set_bit(gpio, GPIO_IRQ_rising_edge);
192 __clear_bit(gpio, GPIO_IRQ_rising_edge);
194 if (type & IRQ_TYPE_EDGE_FALLING)
195 __set_bit(gpio, GPIO_IRQ_falling_edge);
197 __clear_bit(gpio, GPIO_IRQ_falling_edge);
199 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
200 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
202 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
203 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
204 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
209 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
212 static void pxa_ack_low_gpio(unsigned int irq)
214 GEDR0 = (1 << (irq - IRQ_GPIO0));
217 static void pxa_mask_low_gpio(unsigned int irq)
219 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
222 static void pxa_unmask_low_gpio(unsigned int irq)
224 ICMR |= 1 << (irq - PXA_IRQ(0));
227 static struct irq_chip pxa_low_gpio_chip = {
229 .ack = pxa_ack_low_gpio,
230 .mask = pxa_mask_low_gpio,
231 .unmask = pxa_unmask_low_gpio,
232 .set_type = pxa_gpio_irq_type,
236 * Demux handler for GPIO>=2 edge detect interrupts
239 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
241 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
244 unsigned long gedr[4];
247 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
248 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
249 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
250 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
252 GEDR0 = gedr[0]; GEDR1 = gedr[1];
253 GEDR2 = gedr[2]; GEDR3 = gedr[3];
256 bit = find_first_bit(gedr, GEDR_BITS);
257 while (bit < GEDR_BITS) {
260 n = PXA_GPIO_IRQ_BASE + bit;
261 desc_handle_irq(n, irq_desc + n);
263 bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
268 static void pxa_ack_muxed_gpio(unsigned int irq)
270 int gpio = irq - IRQ_GPIO(2) + 2;
271 GEDR(gpio) = GPIO_bit(gpio);
274 static void pxa_mask_muxed_gpio(unsigned int irq)
276 int gpio = irq - IRQ_GPIO(2) + 2;
277 __clear_bit(gpio, GPIO_IRQ_mask);
278 GRER(gpio) &= ~GPIO_bit(gpio);
279 GFER(gpio) &= ~GPIO_bit(gpio);
282 static void pxa_unmask_muxed_gpio(unsigned int irq)
284 int gpio = irq - IRQ_GPIO(2) + 2;
286 __set_bit(gpio, GPIO_IRQ_mask);
287 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
288 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
291 static struct irq_chip pxa_muxed_gpio_chip = {
293 .ack = pxa_ack_muxed_gpio,
294 .mask = pxa_mask_muxed_gpio,
295 .unmask = pxa_unmask_muxed_gpio,
296 .set_type = pxa_gpio_irq_type,
299 void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
303 pxa_last_gpio = gpio_nr - 1;
305 /* clear all GPIO edge detects */
306 for (i = 0; i < gpio_nr; i += 32) {
312 /* GPIO 0 and 1 must have their mask bit always set */
313 GPIO_IRQ_mask[0] = 3;
315 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
316 set_irq_chip(irq, &pxa_low_gpio_chip);
317 set_irq_handler(irq, handle_edge_irq);
318 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
321 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
322 set_irq_chip(irq, &pxa_muxed_gpio_chip);
323 set_irq_handler(irq, handle_edge_irq);
324 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
327 /* Install handler for GPIO>=2 edge detect interrupts */
328 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
330 pxa_low_gpio_chip.set_wake = fn;
331 pxa_muxed_gpio_chip.set_wake = fn;
333 /* add a GPIO chip for each register bank.
334 * the last PXA25x register only contains 21 GPIOs
336 for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
337 if (gpio + 32 > gpio_nr)
338 pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
339 gpiochip_add(&pxa_gpio_chip[i].chip);
345 static unsigned long saved_gplr[4];
346 static unsigned long saved_gpdr[4];
347 static unsigned long saved_grer[4];
348 static unsigned long saved_gfer[4];
350 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
354 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
355 saved_gplr[i] = GPLR(gpio);
356 saved_gpdr[i] = GPDR(gpio);
357 saved_grer[i] = GRER(gpio);
358 saved_gfer[i] = GFER(gpio);
360 /* Clear GPIO transition detect bits */
361 GEDR(gpio) = GEDR(gpio);
366 static int pxa_gpio_resume(struct sys_device *dev)
370 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
371 /* restore level with set/clear */
372 GPSR(gpio) = saved_gplr[i];
373 GPCR(gpio) = ~saved_gplr[i];
375 GRER(gpio) = saved_grer[i];
376 GFER(gpio) = saved_gfer[i];
377 GPDR(gpio) = saved_gpdr[i];
382 #define pxa_gpio_suspend NULL
383 #define pxa_gpio_resume NULL
386 struct sysdev_class pxa_gpio_sysclass = {
388 .suspend = pxa_gpio_suspend,
389 .resume = pxa_gpio_resume,
392 static int __init pxa_gpio_init(void)
394 return sysdev_class_register(&pxa_gpio_sysclass);
397 core_initcall(pxa_gpio_init);