2 * linux/arch/arm/mach-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/sysdev.h>
21 #include <mach/gpio.h>
23 #define GPIO0_BASE (GPIO_REGS_VIRT + 0x0000)
24 #define GPIO1_BASE (GPIO_REGS_VIRT + 0x0004)
25 #define GPIO2_BASE (GPIO_REGS_VIRT + 0x0008)
26 #define GPIO3_BASE (GPIO_REGS_VIRT + 0x0100)
28 #define GPLR_OFFSET 0x00
29 #define GPDR_OFFSET 0x0C
30 #define GPSR_OFFSET 0x18
31 #define GPCR_OFFSET 0x24
32 #define GRER_OFFSET 0x30
33 #define GFER_OFFSET 0x3C
34 #define GEDR_OFFSET 0x48
36 struct pxa_gpio_chip {
37 struct gpio_chip chip;
38 void __iomem *regbase;
43 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
46 u32 mask = 1 << offset;
48 struct pxa_gpio_chip *pxa;
51 pxa = container_of(chip, struct pxa_gpio_chip, chip);
52 gpdr = pxa->regbase + GPDR_OFFSET;
53 local_irq_save(flags);
54 value = __raw_readl(gpdr);
55 if (__gpio_is_inverted(chip->base + offset))
59 __raw_writel(value, gpdr);
60 local_irq_restore(flags);
65 static int pxa_gpio_direction_output(struct gpio_chip *chip,
66 unsigned offset, int value)
69 u32 mask = 1 << offset;
71 struct pxa_gpio_chip *pxa;
74 pxa = container_of(chip, struct pxa_gpio_chip, chip);
76 pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
77 gpdr = pxa->regbase + GPDR_OFFSET;
78 local_irq_save(flags);
79 tmp = __raw_readl(gpdr);
80 if (__gpio_is_inverted(chip->base + offset))
84 __raw_writel(tmp, gpdr);
85 local_irq_restore(flags);
93 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
95 u32 mask = 1 << offset;
96 struct pxa_gpio_chip *pxa;
98 pxa = container_of(chip, struct pxa_gpio_chip, chip);
99 return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
103 * Set output GPIO level
105 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
107 u32 mask = 1 << offset;
108 struct pxa_gpio_chip *pxa;
110 pxa = container_of(chip, struct pxa_gpio_chip, chip);
113 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
115 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
118 #define GPIO_CHIP(_n) \
120 .regbase = GPIO##_n##_BASE, \
122 .label = "gpio-" #_n, \
123 .direction_input = pxa_gpio_direction_input, \
124 .direction_output = pxa_gpio_direction_output, \
125 .get = pxa_gpio_get, \
126 .set = pxa_gpio_set, \
132 static struct pxa_gpio_chip pxa_gpio_chip[] = {
136 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
141 static void __init pxa_init_gpio_chip(int gpio_nr)
145 /* add a GPIO chip for each register bank.
146 * the last PXA25x register only contains 21 GPIOs
148 for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
149 if (gpio + 32 > gpio_nr)
150 pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
151 gpiochip_add(&pxa_gpio_chip[i].chip);
156 * PXA GPIO edge detection for IRQs:
157 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
158 * Use this instead of directly setting GRER/GFER.
161 static unsigned long GPIO_IRQ_rising_edge[4];
162 static unsigned long GPIO_IRQ_falling_edge[4];
163 static unsigned long GPIO_IRQ_mask[4];
165 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
169 gpio = IRQ_TO_GPIO(irq);
172 if (type == IRQ_TYPE_PROBE) {
173 /* Don't mess with enabled GPIOs using preconfigured edges or
174 * GPIOs set to alternate function or to output during probe
176 if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) ||
177 (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio)))
180 if (__gpio_is_occupied(gpio))
183 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
186 if (__gpio_is_inverted(gpio))
187 GPDR(gpio) |= GPIO_bit(gpio);
189 GPDR(gpio) &= ~GPIO_bit(gpio);
191 if (type & IRQ_TYPE_EDGE_RISING)
192 __set_bit(gpio, GPIO_IRQ_rising_edge);
194 __clear_bit(gpio, GPIO_IRQ_rising_edge);
196 if (type & IRQ_TYPE_EDGE_FALLING)
197 __set_bit(gpio, GPIO_IRQ_falling_edge);
199 __clear_bit(gpio, GPIO_IRQ_falling_edge);
201 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
202 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
204 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
205 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
206 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
211 * Demux handler for GPIO>=2 edge detect interrupts
214 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
216 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
219 unsigned long gedr[4];
222 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
223 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
224 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
225 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
227 GEDR0 = gedr[0]; GEDR1 = gedr[1];
228 GEDR2 = gedr[2]; GEDR3 = gedr[3];
231 bit = find_first_bit(gedr, GEDR_BITS);
232 while (bit < GEDR_BITS) {
235 n = PXA_GPIO_IRQ_BASE + bit;
236 generic_handle_irq(n);
238 bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
243 static void pxa_ack_muxed_gpio(unsigned int irq)
245 int gpio = irq - IRQ_GPIO(2) + 2;
246 GEDR(gpio) = GPIO_bit(gpio);
249 static void pxa_mask_muxed_gpio(unsigned int irq)
251 int gpio = irq - IRQ_GPIO(2) + 2;
252 __clear_bit(gpio, GPIO_IRQ_mask);
253 GRER(gpio) &= ~GPIO_bit(gpio);
254 GFER(gpio) &= ~GPIO_bit(gpio);
257 static void pxa_unmask_muxed_gpio(unsigned int irq)
259 int gpio = irq - IRQ_GPIO(2) + 2;
261 __set_bit(gpio, GPIO_IRQ_mask);
262 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
263 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
266 static struct irq_chip pxa_muxed_gpio_chip = {
268 .ack = pxa_ack_muxed_gpio,
269 .mask = pxa_mask_muxed_gpio,
270 .unmask = pxa_unmask_muxed_gpio,
271 .set_type = pxa_gpio_irq_type,
274 void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
280 /* clear all GPIO edge detects */
281 for (i = start; i <= end; i += 32) {
282 GFER(i) &= ~GPIO_IRQ_mask[i];
283 GRER(i) &= ~GPIO_IRQ_mask[i];
284 GEDR(i) = GPIO_IRQ_mask[i];
287 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
288 set_irq_chip(irq, &pxa_muxed_gpio_chip);
289 set_irq_handler(irq, handle_edge_irq);
290 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
293 /* Install handler for GPIO>=2 edge detect interrupts */
294 set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
295 pxa_muxed_gpio_chip.set_wake = fn;
297 /* Initialize GPIO chips */
298 pxa_init_gpio_chip(end + 1);
303 static unsigned long saved_gplr[4];
304 static unsigned long saved_gpdr[4];
305 static unsigned long saved_grer[4];
306 static unsigned long saved_gfer[4];
308 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
312 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
313 saved_gplr[i] = GPLR(gpio);
314 saved_gpdr[i] = GPDR(gpio);
315 saved_grer[i] = GRER(gpio);
316 saved_gfer[i] = GFER(gpio);
318 /* Clear GPIO transition detect bits */
319 GEDR(gpio) = GEDR(gpio);
324 static int pxa_gpio_resume(struct sys_device *dev)
328 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
329 /* restore level with set/clear */
330 GPSR(gpio) = saved_gplr[i];
331 GPCR(gpio) = ~saved_gplr[i];
333 GRER(gpio) = saved_grer[i];
334 GFER(gpio) = saved_gfer[i];
335 GPDR(gpio) = saved_gpdr[i];
340 #define pxa_gpio_suspend NULL
341 #define pxa_gpio_resume NULL
344 struct sysdev_class pxa_gpio_sysclass = {
346 .suspend = pxa_gpio_suspend,
347 .resume = pxa_gpio_resume,
350 static int __init pxa_gpio_init(void)
352 return sysdev_class_register(&pxa_gpio_sysclass);
355 core_initcall(pxa_gpio_init);