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1 /*
2  * linux/arch/arm/mach-omap2/usb-ehci.c
3  *
4  * This file will contain the board specific details for the
5  * Synopsys EHCI host controller on OMAP3430
6  *
7  * Copyright (C) 2008 Nokia Corporation
8  * Author: Felipe Balbi <felipe.balbi@nokia.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <asm/io.h>
21 #include <asm/arch/mux.h>
22 #include <linux/usb/musb.h>
23
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/pm.h>
26 #include <asm/arch/usb.h>
27
28 #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
29 static struct resource ehci_resources[] = {
30         [0] = {
31                 .start   = OMAP34XX_HSUSB_HOST_BASE + 0x800,
32                 .end     = OMAP34XX_HSUSB_HOST_BASE + 0x800 + SZ_1K - 1,
33                 .flags   = IORESOURCE_MEM,
34         },
35         [1] = {         /* general IRQ */
36                 .start   = INT_34XX_EHCI_IRQ,
37                 .flags   = IORESOURCE_IRQ,
38         }
39 };
40
41 static u64 ehci_dmamask = ~(u32)0;
42 static struct platform_device ehci_device = {
43         .name           = "ehci-omap",
44         .id             = 0,
45         .dev = {
46                 .dma_mask               = &ehci_dmamask,
47                 .coherent_dma_mask      = 0xffffffff,
48                 .platform_data          = 0x0,
49         },
50         .num_resources  = ARRAY_SIZE(ehci_resources),
51         .resource       = ehci_resources,
52 };
53
54
55 /* MUX settings for EHCI pins */
56 /*
57  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
58  */
59 static void setup_ehci_io_mux(void)
60 {
61 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
62         /* PHY mode of operation for board: 750-2083-001
63          * ISP1504 connected to Port1 and Port2
64          * Do Func Mux setting for 12-pin ULPI PHY mode
65          */
66
67         /* Port1 */
68         omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
69         omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
70         omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
71         omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
72         omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
73         omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
74         omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
75         omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
76         omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
77         omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
78         omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
79         omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
80
81         /* Port2 */
82         omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
83         omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
84         omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
85         omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
86         omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
87         omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
88         omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
89         omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
90         omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
91         omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
92         omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
93         omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
94
95 #else
96         /* Set Func mux for :
97          * TLL mode of operation
98          * 12-pin ULPI SDR TLL mode for Port1/2/3
99          */
100
101         /* Port1 */
102         omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
103         omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
104         omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
105         omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
106         omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
107         omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
108         omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
109         omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
110         omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
111         omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
112         omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
113         omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
114
115         /* Port2 */
116         omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
117         omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
118         omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
119         omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
120         omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
121         omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
122         omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
123         omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
124         omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
125         omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
126         omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
127         omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
128
129         /* Port3 */
130         omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
131         omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
132         omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
133         omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
134         omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
135         omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
136         omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
137         omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
138         omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
139         omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
140         omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
141         omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
142 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
143
144         return;
145 }
146
147 #endif /* EHCI specific data */
148
149 void __init usb_ehci_init(void)
150 {
151 #if     defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
152         /* Setup Pin IO MUX for EHCI */
153         if (cpu_is_omap34xx())
154                 setup_ehci_io_mux();
155
156         if (platform_device_register(&ehci_device) < 0) {
157                 printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
158                 return;
159         }
160 #endif
161 }
162