2 * linux/arch/arm/mach-omap2/sram-fn.S
4 * Omap2 specific functions that need to be run in internal SRAM
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/linkage.h>
26 #include <asm/assembler.h>
27 #include <asm/arch/io.h>
28 #include <asm/hardware.h>
29 #include <linux/poison.h>
33 ENTRY(omap24xx_sram_ddr_init)
34 stmfd sp!, {r0 - r12, lr} @ save registers on stack
36 mov r12, r2 @ capture CS1 vs CS0
37 mov r8, r3 @ capture force parameter
39 /* frequency shift down */
40 ldr r2, omap24xx_sdi_cm_clksel2_pll @ get address of dpllout reg
41 mov r3, #0x1 @ value for 1x operation
42 str r3, [r2] @ go to L1-freq operation
44 /* voltage shift down */
45 mov r9, #0x1 @ set up for L1 voltage call
46 bl voltage_shift @ go drop voltage
49 ldr r11, omap24xx_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
50 ldr r10, [r11] @ get current val
51 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
52 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
53 mvn r9, #0x4 @ mask to get clear bit2
54 and r10, r10, r9 @ clear bit2 for lock mode.
55 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
56 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
57 str r10, [r11] @ commit to DLLA_CTRL
58 bl i_dll_wait @ wait for dll to lock
61 add r11, r11, #0x4 @ get addr of status reg
62 ldr r10, [r11] @ get locked value
64 /* voltage shift up */
65 mov r9, #0x0 @ shift back to L0-voltage
66 bl voltage_shift @ go raise voltage
68 /* frequency shift up */
69 mov r3, #0x2 @ value for 2x operation
70 str r3, [r2] @ go to L0-freq operation
72 /* reset entry mode for dllctrl */
73 sub r11, r11, #0x4 @ move from status to ctrl
74 cmp r12, #0x1 @ normalize if cs1 based
75 subeq r11, r11, #0x8 @ possibly back to DLLA
76 cmp r8, #0x1 @ if forced unlock exit
77 orreq r1, r1, #0x4 @ make sure exit with unlocked value
78 str r1, [r11] @ restore DLLA_CTRL high value
79 add r11, r11, #0x8 @ move to DLLB_CTRL addr
80 str r1, [r11] @ set value DLLB_CTRL
81 bl i_dll_wait @ wait for possible lock
83 /* set up for return, DDR should be good */
84 str r10, [r0] @ write dll_status and return counter
85 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
87 /* ensure the DLL has relocked */
89 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
96 * shift up or down voltage, use R9 as input to tell level.
97 * wait for it to finish, use 32k sync counter, 1tick=31uS.
100 ldr r4, omap24xx_sdi_prcm_voltctrl @ get addr of volt ctrl.
101 ldr r5, [r4] @ get value.
102 ldr r6, prcm_mask_val @ get value of mask
103 and r5, r5, r6 @ apply mask to clear bits
104 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ set up for change.
106 mov r3, #0x4000 @ get val for force
107 orr r5, r5, r3 @ build value for force
108 str r5, [r4] @ Force transition to L1
110 ldr r3, omap24xx_sdi_timer_32ksynct_cr @ get addr of counter
111 ldr r5, [r3] @ get value
112 add r5, r5, #0x3 @ give it at most 93uS
114 ldr r7, [r3] @ get timer value
115 cmp r5, r7 @ time up?
116 bhi volt_delay @ not yet->branch
117 mov pc, lr @ back to caller.
119 /* relative load constants */
120 .globl omap24xx_sdi_cm_clksel2_pll
121 .globl omap24xx_sdi_sdrc_dlla_ctrl
122 .globl omap24xx_sdi_prcm_voltctrl
123 .globl omap24xx_sdi_timer_32ksynct_cr
125 omap24xx_sdi_cm_clksel2_pll:
127 omap24xx_sdi_sdrc_dlla_ctrl:
129 omap24xx_sdi_prcm_voltctrl:
133 omap24xx_sdi_timer_32ksynct_cr:
135 ENTRY(omap24xx_sram_ddr_init_sz)
136 .word . - omap24xx_sram_ddr_init
139 * Reprograms memory timings.
140 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
141 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
143 ENTRY(omap24xx_sram_reprogram_sdrc)
144 stmfd sp!, {r0 - r10, lr} @ save registers on stack
145 mov r3, #0x0 @ clear for mrc call
146 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
149 ldr r6, omap24xx_srs_sdrc_rfr_ctrl @ get addr of refresh reg
150 ldr r5, [r6] @ get value
151 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
153 cmp r0, #0x1 @ going to half speed?
154 movne r9, #0x0 @ if up set flag up for pre up, hi volt
156 blne voltage_shift_c @ adjust voltage
158 cmp r0, #0x1 @ going to half speed (post branch link)
159 moveq r5, r5, lsr #1 @ divide by 2 if to half
160 movne r5, r5, lsl #1 @ mult by 2 if to full
161 mov r5, r5, lsl #8 @ put rfr field back into place
162 add r5, r5, #0x1 @ turn on burst of 1
163 ldr r4, omap24xx_srs_cm_clksel2_pll @ get address of out reg
164 ldr r3, [r4] @ get curr value
166 bic r3, r3, #0x3 @ clear lower bits
167 orr r3, r3, r0 @ new state value
168 str r3, [r4] @ set new state (pll/x, x=1 or 2)
172 moveq r9, #0x1 @ if speed down, post down, drop volt
175 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
176 str r5, [r6] @ set new RFR_1 value
177 add r6, r6, #0x30 @ get RFR_2 addr
178 str r5, [r6] @ set RFR_2
180 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
181 bne freq_out @ leave if SDR, no DLL function
183 /* With DDR, we need to take care of the DLL for the frequency change */
184 ldr r2, omap24xx_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
185 str r1, [r2] @ write out new SDRC_DLLA_CTRL
186 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
187 str r1, [r2] @ commit to SDRC_DLLB_CTRL
188 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
193 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
196 * shift up or down voltage, use R9 as input to tell level.
197 * wait for it to finish, use 32k sync counter, 1tick=31uS.
200 ldr r10, omap24xx_srs_prcm_voltctrl @ get addr of volt ctrl
201 ldr r8, [r10] @ get value
202 ldr r7, ddr_prcm_mask_val @ get value of mask
203 and r8, r8, r7 @ apply mask to clear bits
204 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
205 str r8, [r10] @ set up for change.
206 mov r7, #0x4000 @ get val for force
207 orr r8, r8, r7 @ build value for force
208 str r8, [r10] @ Force transition to L1
210 ldr r10, omap24xx_srs_timer_32ksynct @ get addr of counter
211 ldr r8, [r10] @ get value
212 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
214 ldr r7, [r10] @ get timer value
215 cmp r8, r7 @ time up?
216 bhi volt_delay_c @ not yet->branch
217 mov pc, lr @ back to caller
219 .globl omap24xx_srs_cm_clksel2_pll
220 .globl omap24xx_srs_sdrc_dlla_ctrl
221 .globl omap24xx_srs_sdrc_rfr_ctrl
222 .globl omap24xx_srs_prcm_voltctrl
223 .globl omap24xx_srs_timer_32ksynct
225 omap24xx_srs_cm_clksel2_pll:
227 omap24xx_srs_sdrc_dlla_ctrl:
229 omap24xx_srs_sdrc_rfr_ctrl:
231 omap24xx_srs_prcm_voltctrl:
235 omap24xx_srs_timer_32ksynct:
238 ENTRY(omap24xx_sram_reprogram_sdrc_sz)
239 .word . - omap24xx_sram_reprogram_sdrc
242 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
244 ENTRY(omap24xx_sram_set_prcm)
245 stmfd sp!, {r0-r12, lr} @ regs to stack
246 adr r4, pbegin @ addr of preload start
247 adr r8, pend @ addr of preload end
248 mcrr p15, 1, r8, r4, c12 @ preload into icache
250 /* move into fast relock bypass */
251 ldr r8, omap24xx_ssp_pll_ctl @ get addr
252 ldr r5, [r8] @ get val
253 mvn r6, #0x3 @ clear mask
254 and r5, r5, r6 @ clear field
255 orr r7, r5, #0x2 @ fast relock val
256 str r7, [r8] @ go to fast relock
257 ldr r4, omap24xx_ssp_pll_stat @ addr of stat
259 /* wait for bypass */
260 ldr r8, [r4] @ stat value
261 and r8, r8, #0x3 @ mask for stat
262 cmp r8, #0x1 @ there yet
263 bne block @ loop if not
265 /* set new dpll dividers _after_ in bypass */
266 ldr r4, omap24xx_ssp_pll_div @ get addr
267 str r0, [r4] @ set dpll ctrl val
269 ldr r4, omap24xx_ssp_set_config @ get addr
270 mov r8, #1 @ valid cfg msk
271 str r8, [r4] @ make dividers take
273 mov r4, #100 @ dead spin a bit
275 subs r4, r4, #1 @ dec loop
276 bne wait_a_bit @ delay done?
278 /* check if staying in bypass */
279 cmp r2, #0x1 @ stay in bypass?
280 beq pend @ jump over dpll relock
282 /* relock DPLL with new vals */
283 ldr r5, omap24xx_ssp_pll_stat @ get addr
284 ldr r4, omap24xx_ssp_pll_ctl @ get addr
285 orr r8, r7, #0x3 @ val for lock dpll
286 str r8, [r4] @ set val
287 mov r0, #1000 @ dead spin a bit
289 subs r0, r0, #1 @ dec loop
290 bne wait_more @ delay done?
292 ldr r8, [r5] @ get lock val
293 and r8, r8, #3 @ isolate field
295 bne wait_lock @ wait if not
297 /* update memory timings & briefly lock dll */
298 ldr r4, omap24xx_ssp_sdrc_rfr @ get addr
299 str r1, [r4] @ update refresh timing
300 ldr r11, omap24xx_ssp_dlla_ctrl @ get addr of DLLA ctrl
301 ldr r10, [r11] @ get current val
302 mvn r9, #0x4 @ mask to get clear bit2
303 and r10, r10, r9 @ clear bit2 for lock mode
304 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
305 str r10, [r11] @ commit to DLLA_CTRL
306 add r11, r11, #0x8 @ move to dllb
307 str r10, [r11] @ hit DLLB also
309 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
314 ldmfd sp!, {r0-r12, pc} @ restore regs and return
316 .globl omap24xx_ssp_set_config
317 .globl omap24xx_ssp_pll_ctl
318 .globl omap24xx_ssp_pll_stat
319 .globl omap24xx_ssp_pll_div
320 .globl omap24xx_ssp_sdrc_rfr
321 .globl omap24xx_ssp_dlla_ctrl
323 omap24xx_ssp_set_config:
325 omap24xx_ssp_pll_ctl:
327 omap24xx_ssp_pll_stat:
329 omap24xx_ssp_pll_div:
331 omap24xx_ssp_sdrc_rfr:
333 omap24xx_ssp_dlla_ctrl:
336 ENTRY(omap24xx_sram_set_prcm_sz)
337 .word . - omap24xx_sram_set_prcm