2 * linux/arch/arm/mach-omap2/sram243x.S
4 * Omap2 specific functions that need to be run in internal SRAM
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/linkage.h>
26 #include <asm/assembler.h>
28 #include <mach/hardware.h>
34 #define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
35 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
36 #define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
37 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
41 ENTRY(omap243x_sram_ddr_init)
42 stmfd sp!, {r0 - r12, lr} @ save registers on stack
44 mov r12, r2 @ capture CS1 vs CS0
45 mov r8, r3 @ capture force parameter
47 /* frequency shift down */
48 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
49 mov r3, #0x1 @ value for 1x operation
50 str r3, [r2] @ go to L1-freq operation
52 /* voltage shift down */
53 mov r9, #0x1 @ set up for L1 voltage call
54 bl voltage_shift @ go drop voltage
57 ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
58 ldr r10, [r11] @ get current val
59 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
60 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
61 mvn r9, #0x4 @ mask to get clear bit2
62 and r10, r10, r9 @ clear bit2 for lock mode.
63 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
64 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
65 str r10, [r11] @ commit to DLLA_CTRL
66 bl i_dll_wait @ wait for dll to lock
69 add r11, r11, #0x4 @ get addr of status reg
70 ldr r10, [r11] @ get locked value
72 /* voltage shift up */
73 mov r9, #0x0 @ shift back to L0-voltage
74 bl voltage_shift @ go raise voltage
76 /* frequency shift up */
77 mov r3, #0x2 @ value for 2x operation
78 str r3, [r2] @ go to L0-freq operation
80 /* reset entry mode for dllctrl */
81 sub r11, r11, #0x4 @ move from status to ctrl
82 cmp r12, #0x1 @ normalize if cs1 based
83 subeq r11, r11, #0x8 @ possibly back to DLLA
84 cmp r8, #0x1 @ if forced unlock exit
85 orreq r1, r1, #0x4 @ make sure exit with unlocked value
86 str r1, [r11] @ restore DLLA_CTRL high value
87 add r11, r11, #0x8 @ move to DLLB_CTRL addr
88 str r1, [r11] @ set value DLLB_CTRL
89 bl i_dll_wait @ wait for possible lock
91 /* set up for return, DDR should be good */
92 str r10, [r0] @ write dll_status and return counter
93 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
95 /* ensure the DLL has relocked */
97 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
104 * shift up or down voltage, use R9 as input to tell level.
105 * wait for it to finish, use 32k sync counter, 1tick=31uS.
108 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
109 ldr r5, [r4] @ get value.
110 ldr r6, prcm_mask_val @ get value of mask
111 and r5, r5, r6 @ apply mask to clear bits
112 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
113 str r5, [r4] @ set up for change.
114 mov r3, #0x4000 @ get val for force
115 orr r5, r5, r3 @ build value for force
116 str r5, [r4] @ Force transition to L1
118 ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
119 ldr r5, [r3] @ get value
120 add r5, r5, #0x3 @ give it at most 93uS
122 ldr r7, [r3] @ get timer value
123 cmp r5, r7 @ time up?
124 bhi volt_delay @ not yet->branch
125 mov pc, lr @ back to caller.
127 omap243x_sdi_cm_clksel2_pll:
128 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
129 omap243x_sdi_sdrc_dlla_ctrl:
130 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
131 omap243x_sdi_prcm_voltctrl:
132 .word OMAP243X_PRCM_VOLTCTRL
135 omap243x_sdi_timer_32ksynct_cr:
136 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
137 ENTRY(omap243x_sram_ddr_init_sz)
138 .word . - omap243x_sram_ddr_init
141 * Reprograms memory timings.
142 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
143 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
145 ENTRY(omap243x_sram_reprogram_sdrc)
146 stmfd sp!, {r0 - r10, lr} @ save registers on stack
147 mov r3, #0x0 @ clear for mrc call
148 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
151 ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
152 ldr r5, [r6] @ get value
153 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
155 cmp r0, #0x1 @ going to half speed?
156 movne r9, #0x0 @ if up set flag up for pre up, hi volt
158 blne voltage_shift_c @ adjust voltage
160 cmp r0, #0x1 @ going to half speed (post branch link)
161 moveq r5, r5, lsr #1 @ divide by 2 if to half
162 movne r5, r5, lsl #1 @ mult by 2 if to full
163 mov r5, r5, lsl #8 @ put rfr field back into place
164 add r5, r5, #0x1 @ turn on burst of 1
165 ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
166 ldr r3, [r4] @ get curr value
168 bic r3, r3, #0x3 @ clear lower bits
169 orr r3, r3, r0 @ new state value
170 str r3, [r4] @ set new state (pll/x, x=1 or 2)
174 moveq r9, #0x1 @ if speed down, post down, drop volt
177 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
178 str r5, [r6] @ set new RFR_1 value
179 add r6, r6, #0x30 @ get RFR_2 addr
180 str r5, [r6] @ set RFR_2
182 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
183 bne freq_out @ leave if SDR, no DLL function
185 /* With DDR, we need to take care of the DLL for the frequency change */
186 ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
187 str r1, [r2] @ write out new SDRC_DLLA_CTRL
188 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
189 str r1, [r2] @ commit to SDRC_DLLB_CTRL
190 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
195 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
198 * shift up or down voltage, use R9 as input to tell level.
199 * wait for it to finish, use 32k sync counter, 1tick=31uS.
202 ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
203 ldr r8, [r10] @ get value
204 ldr r7, ddr_prcm_mask_val @ get value of mask
205 and r8, r8, r7 @ apply mask to clear bits
206 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
207 str r8, [r10] @ set up for change.
208 mov r7, #0x4000 @ get val for force
209 orr r8, r8, r7 @ build value for force
210 str r8, [r10] @ Force transition to L1
212 ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
213 ldr r8, [r10] @ get value
214 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
216 ldr r7, [r10] @ get timer value
217 cmp r8, r7 @ time up?
218 bhi volt_delay_c @ not yet->branch
219 mov pc, lr @ back to caller
221 omap243x_srs_cm_clksel2_pll:
222 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
223 omap243x_srs_sdrc_dlla_ctrl:
224 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
225 omap243x_srs_sdrc_rfr_ctrl:
226 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
227 omap243x_srs_prcm_voltctrl:
228 .word OMAP243X_PRCM_VOLTCTRL
231 omap243x_srs_timer_32ksynct:
232 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
234 ENTRY(omap243x_sram_reprogram_sdrc_sz)
235 .word . - omap243x_sram_reprogram_sdrc
238 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
240 ENTRY(omap243x_sram_set_prcm)
241 stmfd sp!, {r0-r12, lr} @ regs to stack
242 adr r4, pbegin @ addr of preload start
243 adr r8, pend @ addr of preload end
244 mcrr p15, 1, r8, r4, c12 @ preload into icache
246 /* move into fast relock bypass */
247 ldr r8, omap243x_ssp_pll_ctl @ get addr
248 ldr r5, [r8] @ get val
249 mvn r6, #0x3 @ clear mask
250 and r5, r5, r6 @ clear field
251 orr r7, r5, #0x2 @ fast relock val
252 str r7, [r8] @ go to fast relock
253 ldr r4, omap243x_ssp_pll_stat @ addr of stat
255 /* wait for bypass */
256 ldr r8, [r4] @ stat value
257 and r8, r8, #0x3 @ mask for stat
258 cmp r8, #0x1 @ there yet
259 bne block @ loop if not
261 /* set new dpll dividers _after_ in bypass */
262 ldr r4, omap243x_ssp_pll_div @ get addr
263 str r0, [r4] @ set dpll ctrl val
265 ldr r4, omap243x_ssp_set_config @ get addr
266 mov r8, #1 @ valid cfg msk
267 str r8, [r4] @ make dividers take
269 mov r4, #100 @ dead spin a bit
271 subs r4, r4, #1 @ dec loop
272 bne wait_a_bit @ delay done?
274 /* check if staying in bypass */
275 cmp r2, #0x1 @ stay in bypass?
276 beq pend @ jump over dpll relock
278 /* relock DPLL with new vals */
279 ldr r5, omap243x_ssp_pll_stat @ get addr
280 ldr r4, omap243x_ssp_pll_ctl @ get addr
281 orr r8, r7, #0x3 @ val for lock dpll
282 str r8, [r4] @ set val
283 mov r0, #1000 @ dead spin a bit
285 subs r0, r0, #1 @ dec loop
286 bne wait_more @ delay done?
288 ldr r8, [r5] @ get lock val
289 and r8, r8, #3 @ isolate field
291 bne wait_lock @ wait if not
293 /* update memory timings & briefly lock dll */
294 ldr r4, omap243x_ssp_sdrc_rfr @ get addr
295 str r1, [r4] @ update refresh timing
296 ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
297 ldr r10, [r11] @ get current val
298 mvn r9, #0x4 @ mask to get clear bit2
299 and r10, r10, r9 @ clear bit2 for lock mode
300 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
301 str r10, [r11] @ commit to DLLA_CTRL
302 add r11, r11, #0x8 @ move to dllb
303 str r10, [r11] @ hit DLLB also
305 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
310 ldmfd sp!, {r0-r12, pc} @ restore regs and return
312 omap243x_ssp_set_config:
313 .word OMAP243X_PRCM_CLKCFG_CTRL
314 omap243x_ssp_pll_ctl:
315 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
316 omap243x_ssp_pll_stat:
317 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
318 omap243x_ssp_pll_div:
319 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
320 omap243x_ssp_sdrc_rfr:
321 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
322 omap243x_ssp_dlla_ctrl:
323 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
325 ENTRY(omap243x_sram_set_prcm_sz)
326 .word . - omap243x_sram_set_prcm