2 * linux/arch/arm/mach-omap2/sram-fn.S
4 * Omap2 specific functions that need to be run in internal SRAM
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/linkage.h>
26 #include <asm/assembler.h>
27 #include <asm/arch/io.h>
28 #include <asm/hardware.h>
29 #include <linux/poison.h>
31 #define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP2_PRM_BASE + 0x080)
32 #define CM_CLKEN_PLL_V IO_ADDRESS(OMAP2_CM_BASE + 0x500)
33 #define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP2_CM_BASE + 0x520)
34 #define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP2_CM_BASE + 0x540)
36 #define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP2_SDRC_BASE + 0x060)
37 #define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP2_SDRC_BASE + 0x0a4)
42 stmfd sp!, {r0 - r12, lr} @ save registers on stack
44 mov r12, r2 @ capture CS1 vs CS0
45 mov r8, r3 @ capture force parameter
47 /* frequency shift down */
48 ldr r2, omap2_sdi_cm_clksel2_pll @ get address of dpllout reg
49 mov r3, #0x1 @ value for 1x operation
50 str r3, [r2] @ go to L1-freq operation
52 /* voltage shift down */
53 mov r9, #0x1 @ set up for L1 voltage call
54 bl voltage_shift @ go drop voltage
57 ldr r11, omap2_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
58 ldr r10, [r11] @ get current val
59 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
60 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
61 mvn r9, #0x4 @ mask to get clear bit2
62 and r10, r10, r9 @ clear bit2 for lock mode.
63 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
64 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
65 str r10, [r11] @ commit to DLLA_CTRL
66 bl i_dll_wait @ wait for dll to lock
69 add r11, r11, #0x4 @ get addr of status reg
70 ldr r10, [r11] @ get locked value
72 /* voltage shift up */
73 mov r9, #0x0 @ shift back to L0-voltage
74 bl voltage_shift @ go raise voltage
76 /* frequency shift up */
77 mov r3, #0x2 @ value for 2x operation
78 str r3, [r2] @ go to L0-freq operation
80 /* reset entry mode for dllctrl */
81 sub r11, r11, #0x4 @ move from status to ctrl
82 cmp r12, #0x1 @ normalize if cs1 based
83 subeq r11, r11, #0x8 @ possibly back to DLLA
84 cmp r8, #0x1 @ if forced unlock exit
85 orreq r1, r1, #0x4 @ make sure exit with unlocked value
86 str r1, [r11] @ restore DLLA_CTRL high value
87 add r11, r11, #0x8 @ move to DLLB_CTRL addr
88 str r1, [r11] @ set value DLLB_CTRL
89 bl i_dll_wait @ wait for possible lock
91 /* set up for return, DDR should be good */
92 str r10, [r0] @ write dll_status and return counter
93 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
95 /* ensure the DLL has relocked */
97 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
104 * shift up or down voltage, use R9 as input to tell level.
105 * wait for it to finish, use 32k sync counter, 1tick=31uS.
108 ldr r4, omap2_sdi_prcm_voltctrl @ get addr of volt ctrl.
109 ldr r5, [r4] @ get value.
110 ldr r6, prcm_mask_val @ get value of mask
111 and r5, r5, r6 @ apply mask to clear bits
112 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
113 str r5, [r4] @ set up for change.
114 mov r3, #0x4000 @ get val for force
115 orr r5, r5, r3 @ build value for force
116 str r5, [r4] @ Force transition to L1
118 ldr r3, omap2_sdi_timer_32ksynct_cr @ get addr of counter
119 ldr r5, [r3] @ get value
120 add r5, r5, #0x3 @ give it at most 93uS
122 ldr r7, [r3] @ get timer value
123 cmp r5, r7 @ time up?
124 bhi volt_delay @ not yet->branch
125 mov pc, lr @ back to caller.
127 /* relative load constants */
128 .globl omap2_sdi_cm_clksel2_pll
129 .globl omap2_sdi_sdrc_dlla_ctrl
130 .globl omap2_sdi_prcm_voltctrl
131 .globl omap2_sdi_timer_32ksynct_cr
133 omap2_sdi_cm_clksel2_pll:
135 omap2_sdi_sdrc_dlla_ctrl:
137 omap2_sdi_prcm_voltctrl:
141 omap2_sdi_timer_32ksynct_cr:
143 ENTRY(sram_ddr_init_sz)
144 .word . - sram_ddr_init
147 * Reprograms memory timings.
148 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
149 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
151 ENTRY(sram_reprogram_sdrc)
152 stmfd sp!, {r0 - r10, lr} @ save registers on stack
153 mov r3, #0x0 @ clear for mrc call
154 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
157 ldr r6, omap2_srs_sdrc_rfr_ctrl @ get addr of refresh reg
158 ldr r5, [r6] @ get value
159 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
161 cmp r0, #0x1 @ going to half speed?
162 movne r9, #0x0 @ if up set flag up for pre up, hi volt
164 blne voltage_shift_c @ adjust voltage
166 cmp r0, #0x1 @ going to half speed (post branch link)
167 moveq r5, r5, lsr #1 @ divide by 2 if to half
168 movne r5, r5, lsl #1 @ mult by 2 if to full
169 mov r5, r5, lsl #8 @ put rfr field back into place
170 add r5, r5, #0x1 @ turn on burst of 1
171 ldr r4, omap2_srs_cm_clksel2_pll @ get address of out reg
172 ldr r3, [r4] @ get curr value
174 bic r3, r3, #0x3 @ clear lower bits
175 orr r3, r3, r0 @ new state value
176 str r3, [r4] @ set new state (pll/x, x=1 or 2)
180 moveq r9, #0x1 @ if speed down, post down, drop volt
183 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
184 str r5, [r6] @ set new RFR_1 value
185 add r6, r6, #0x30 @ get RFR_2 addr
186 str r5, [r6] @ set RFR_2
188 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
189 bne freq_out @ leave if SDR, no DLL function
191 /* With DDR, we need to take care of the DLL for the frequency change */
192 ldr r2, omap2_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
193 str r1, [r2] @ write out new SDRC_DLLA_CTRL
194 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
195 str r1, [r2] @ commit to SDRC_DLLB_CTRL
196 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
201 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
204 * shift up or down voltage, use R9 as input to tell level.
205 * wait for it to finish, use 32k sync counter, 1tick=31uS.
208 ldr r10, omap2_srs_prcm_voltctrl @ get addr of volt ctrl
209 ldr r8, [r10] @ get value
210 ldr r7, ddr_prcm_mask_val @ get value of mask
211 and r8, r8, r7 @ apply mask to clear bits
212 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
213 str r8, [r10] @ set up for change.
214 mov r7, #0x4000 @ get val for force
215 orr r8, r8, r7 @ build value for force
216 str r8, [r10] @ Force transition to L1
218 ldr r10, omap2_srs_timer_32ksynct @ get addr of counter
219 ldr r8, [r10] @ get value
220 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
222 ldr r7, [r10] @ get timer value
223 cmp r8, r7 @ time up?
224 bhi volt_delay_c @ not yet->branch
225 mov pc, lr @ back to caller
227 .globl omap2_srs_cm_clksel2_pll
228 .globl omap2_srs_sdrc_dlla_ctrl
229 .globl omap2_srs_sdrc_rfr_ctrl
230 .globl omap2_srs_prcm_voltctrl
231 .globl omap2_srs_timer_32ksynct
233 omap2_srs_cm_clksel2_pll:
235 omap2_srs_sdrc_dlla_ctrl:
237 omap2_srs_sdrc_rfr_ctrl:
239 omap2_srs_prcm_voltctrl:
243 omap2_srs_timer_32ksynct:
246 ENTRY(sram_reprogram_sdrc_sz)
247 .word . - sram_reprogram_sdrc
250 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
253 stmfd sp!, {r0-r12, lr} @ regs to stack
254 adr r4, pbegin @ addr of preload start
255 adr r8, pend @ addr of preload end
256 mcrr p15, 1, r8, r4, c12 @ preload into icache
258 /* move into fast relock bypass */
259 ldr r8, pll_ctl @ get addr
260 ldr r5, [r8] @ get val
261 mvn r6, #0x3 @ clear mask
262 and r5, r5, r6 @ clear field
263 orr r7, r5, #0x2 @ fast relock val
264 str r7, [r8] @ go to fast relock
265 ldr r4, pll_stat @ addr of stat
267 /* wait for bypass */
268 ldr r8, [r4] @ stat value
269 and r8, r8, #0x3 @ mask for stat
270 cmp r8, #0x1 @ there yet
271 bne block @ loop if not
273 /* set new dpll dividers _after_ in bypass */
274 ldr r4, pll_div @ get addr
275 str r0, [r4] @ set dpll ctrl val
277 ldr r4, set_config @ get addr
278 mov r8, #1 @ valid cfg msk
279 str r8, [r4] @ make dividers take
281 mov r4, #100 @ dead spin a bit
283 subs r4, r4, #1 @ dec loop
284 bne wait_a_bit @ delay done?
286 /* check if staying in bypass */
287 cmp r2, #0x1 @ stay in bypass?
288 beq pend @ jump over dpll relock
290 /* relock DPLL with new vals */
291 ldr r5, pll_stat @ get addr
292 ldr r4, pll_ctl @ get addr
293 orr r8, r7, #0x3 @ val for lock dpll
294 str r8, [r4] @ set val
295 mov r0, #1000 @ dead spin a bit
297 subs r0, r0, #1 @ dec loop
298 bne wait_more @ delay done?
300 ldr r8, [r5] @ get lock val
301 and r8, r8, #3 @ isolate field
303 bne wait_lock @ wait if not
305 /* update memory timings & briefly lock dll */
306 ldr r4, sdrc_rfr @ get addr
307 str r1, [r4] @ update refresh timing
308 ldr r11, dlla_ctrl @ get addr of DLLA ctrl
309 ldr r10, [r11] @ get current val
310 mvn r9, #0x4 @ mask to get clear bit2
311 and r10, r10, r9 @ clear bit2 for lock mode
312 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
313 str r10, [r11] @ commit to DLLA_CTRL
314 add r11, r11, #0x8 @ move to dllb
315 str r10, [r11] @ hit DLLB also
317 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
322 ldmfd sp!, {r0-r12, pc} @ restore regs and return
325 .word PRCM_CLKCFG_CTRL_V
329 .word CM_IDLEST_CKGEN_V
331 .word CM_CLKSEL1_PLL_V
333 .word SDRC_RFR_CTRL_V
335 .word SDRC_DLLA_CTRL_V
337 ENTRY(sram_set_prcm_sz)
338 .word . - sram_set_prcm