arch/arm/mach-omap2/prm_regbits_34xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
   3
   4 /*
   5  * OMAP3430 Power/Reset Management register bits
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prm.h"
  18
  19 /* Shared register bits */
  20
  21 /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
  22 #define OMAP3430_ON_SHIFT                               24
  23 #define OMAP3430_ON_MASK                                (0xff << 24)
  24 #define OMAP3430_ONLP_SHIFT                             16
  25 #define OMAP3430_ONLP_MASK                              (0xff << 16)
  26 #define OMAP3430_RET_SHIFT                              8
  27 #define OMAP3430_RET_MASK                               (0xff << 8)
  28 #define OMAP3430_OFF_SHIFT                              0
  29 #define OMAP3430_OFF_MASK                               (0xff << 0)
  30
  31 /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
  32 #define OMAP3430_ERROROFFSET_SHIFT                      24
  33 #define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
  34 #define OMAP3430_ERRORGAIN_SHIFT                        16
  35 #define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
  36 #define OMAP3430_INITVOLTAGE_SHIFT                      8
  37 #define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
  38 #define OMAP3430_TIMEOUTEN                              (1 << 3)
  39 #define OMAP3430_INITVDD                                (1 << 2)
  40 #define OMAP3430_FORCEUPDATE                            (1 << 1)
  41 #define OMAP3430_VPENABLE                               (1 << 0)
  42
  43 /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
  44 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
  45 #define OMAP3430_SMPSWAITTIMEMIN_MASK                   (0xffff << 8)
  46 #define OMAP3430_VSTEPMIN_SHIFT                         0
  47 #define OMAP3430_VSTEPMIN_MASK                          (0xff << 0)
  48
  49 /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
  50 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
  51 #define OMAP3430_SMPSWAITTIMEMAX_MASK                   (0xffff << 8)
  52 #define OMAP3430_VSTEPMAX_SHIFT                         0
  53 #define OMAP3430_VSTEPMAX_MASK                          (0xff << 0)
  54
  55 /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
  56 #define OMAP3430_VDDMAX_SHIFT                           24
  57 #define OMAP3430_VDDMAX_MASK                            (0xff << 24)
  58 #define OMAP3430_VDDMIN_SHIFT                           16
  59 #define OMAP3430_VDDMIN_MASK                            (0xff << 16)
  60 #define OMAP3430_TIMEOUT_SHIFT                          0
  61 #define OMAP3430_TIMEOUT_MASK                           (0xffff << 0)
  62
  63 /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
  64 #define OMAP3430_VPVOLTAGE_SHIFT                        0
  65 #define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
  66
  67 /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
  68 #define OMAP3430_VPINIDLE                               (1 << 0)
  69
  70 /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
  71 #define OMAP3430_EN_PER                                 (1 << 7)
  72
  73 /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
  74 #define OMAP3430_MEMORYCHANGE                           (1 << 3)
  75
  76 /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
  77 #define OMAP3430_LOGICSTATEST                           (1 << 2)
  78
  79 /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
  80 #define OMAP3430_LASTLOGICSTATEENTERED                          (1 << 2)
  81
  82 /*
  83  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
  84  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
  85  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
  86  */
  87 #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT                    0
  88 #define OMAP3430_LASTPOWERSTATEENTERED_MASK                     (0x3 << 0)
  89
  90 /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
  91 #define OMAP3430_WKUP_ST                                (1 << 0)
  92
  93 /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
  94 #define OMAP3430_WKUP_EN                                        (1 << 0)
  95
  96 /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
  97 #define OMAP3430_GRPSEL_MMC2                            (1 << 25)
  98 #define OMAP3430_GRPSEL_MMC1                            (1 << 24)
  99 #define OMAP3430_GRPSEL_MCSPI4                          (1 << 21)
 100 #define OMAP3430_GRPSEL_MCSPI3                          (1 << 20)
 101 #define OMAP3430_GRPSEL_MCSPI2                          (1 << 19)
 102 #define OMAP3430_GRPSEL_MCSPI1                          (1 << 18)
 103 #define OMAP3430_GRPSEL_I2C3                            (1 << 17)
 104 #define OMAP3430_GRPSEL_I2C2                            (1 << 16)
 105 #define OMAP3430_GRPSEL_I2C1                            (1 << 15)
 106 #define OMAP3430_GRPSEL_UART2                           (1 << 14)
 107 #define OMAP3430_GRPSEL_UART1                           (1 << 13)
 108 #define OMAP3430_GRPSEL_GPT11                           (1 << 12)
 109 #define OMAP3430_GRPSEL_GPT10                           (1 << 11)
 110 #define OMAP3430_GRPSEL_MCBSP5                          (1 << 10)
 111 #define OMAP3430_GRPSEL_MCBSP1                          (1 << 9)
 112 #define OMAP3430_GRPSEL_HSOTGUSB                        (1 << 4)
 113 #define OMAP3430_GRPSEL_D2D                             (1 << 3)
 114
 115 /*
 116  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
 117  * PM_PWSTCTRL_PER shared bits
 118  */
 119 #define OMAP3430_MEMONSTATE_SHIFT                       16
 120 #define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
 121 #define OMAP3430_MEMRETSTATE                            (1 << 8)
 122
 123 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
 124 #define OMAP3430_GRPSEL_GPIO6                           (1 << 17)
 125 #define OMAP3430_GRPSEL_GPIO5                           (1 << 16)
 126 #define OMAP3430_GRPSEL_GPIO4                           (1 << 15)
 127 #define OMAP3430_GRPSEL_GPIO3                           (1 << 14)
 128 #define OMAP3430_GRPSEL_GPIO2                           (1 << 13)
 129 #define OMAP3430_GRPSEL_UART3                           (1 << 11)
 130 #define OMAP3430_GRPSEL_GPT9                            (1 << 10)
 131 #define OMAP3430_GRPSEL_GPT8                            (1 << 9)
 132 #define OMAP3430_GRPSEL_GPT7                            (1 << 8)
 133 #define OMAP3430_GRPSEL_GPT6                            (1 << 7)
 134 #define OMAP3430_GRPSEL_GPT5                            (1 << 6)
 135 #define OMAP3430_GRPSEL_GPT4                            (1 << 5)
 136 #define OMAP3430_GRPSEL_GPT3                            (1 << 4)
 137 #define OMAP3430_GRPSEL_GPT2                            (1 << 3)
 138 #define OMAP3430_GRPSEL_MCBSP4                          (1 << 2)
 139 #define OMAP3430_GRPSEL_MCBSP3                          (1 << 1)
 140 #define OMAP3430_GRPSEL_MCBSP2                          (1 << 0)
 141
 142 /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
 143 #define OMAP3430_GRPSEL_IO                              (1 << 8)
 144 #define OMAP3430_GRPSEL_SR2                             (1 << 7)
 145 #define OMAP3430_GRPSEL_SR1                             (1 << 6)
 146 #define OMAP3430_GRPSEL_GPIO1                           (1 << 3)
 147 #define OMAP3430_GRPSEL_GPT12                           (1 << 1)
 148 #define OMAP3430_GRPSEL_GPT1                            (1 << 0)
 149
 150 /* Bits specific to each register */
 151
 152 /* RM_RSTCTRL_IVA2 */
 153 #define OMAP3430_RST3_IVA2                              (1 << 2)
 154 #define OMAP3430_RST2_IVA2                              (1 << 1)
 155 #define OMAP3430_RST1_IVA2                              (1 << 0)
 156
 157 /* RM_RSTST_IVA2 specific bits */
 158 #define OMAP3430_EMULATION_VSEQ_RST                     (1 << 13)
 159 #define OMAP3430_EMULATION_VHWA_RST                     (1 << 12)
 160 #define OMAP3430_EMULATION_IVA2_RST                     (1 << 11)
 161 #define OMAP3430_IVA2_SW_RST3                           (1 << 10)
 162 #define OMAP3430_IVA2_SW_RST2                           (1 << 9)
 163 #define OMAP3430_IVA2_SW_RST1                           (1 << 8)
 164
 165 /* PM_WKDEP_IVA2 specific bits */
 166
 167 /* PM_PWSTCTRL_IVA2 specific bits */
 168 #define OMAP3430_L2FLATMEMONSTATE_SHIFT                 22
 169 #define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
 170 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT         20
 171 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
 172 #define OMAP3430_L1FLATMEMONSTATE_SHIFT                 18
 173 #define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
 174 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
 175 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
 176 #define OMAP3430_L2FLATMEMRETSTATE                      (1 << 11)
 177 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE              (1 << 10)
 178 #define OMAP3430_L1FLATMEMRETSTATE                      (1 << 9)
 179 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE              (1 << 8)
 180
 181 /* PM_PWSTST_IVA2 specific bits */
 182 #define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
 183 #define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
 184 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT         8
 185 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
 186 #define OMAP3430_L1FLATMEMSTATEST_SHIFT                 6
 187 #define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
 188 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT         4
 189 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
 190
 191 /* PM_PREPWSTST_IVA2 specific bits */
 192 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT                10
 193 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
 194 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT        8
 195 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
 196 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT                6
 197 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK                 (0x3 << 6)
 198 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT        4
 199 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
 200
 201 /* PRM_IRQSTATUS_IVA2 specific bits */
 202 #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST        (1 << 2)
 203 #define OMAP3430_FORCEWKUP_ST                           (1 << 1)
 204
 205 /* PRM_IRQENABLE_IVA2 specific bits */
 206 #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN          (1 << 2)
 207 #define OMAP3430_FORCEWKUP_EN                                   (1 << 1)
 208
 209 /* PRM_REVISION specific bits */
 210
 211 /* PRM_SYSCONFIG specific bits */
 212
 213 /* PRM_IRQSTATUS_MPU specific bits */
 214 #define OMAP3430_VC_TIMEOUTERR_ST                       (1 << 24)
 215 #define OMAP3430_VC_RAERR_ST                            (1 << 23)
 216 #define OMAP3430_VC_SAERR_ST                            (1 << 22)
 217 #define OMAP3430_VP2_TRANXDONE_ST                       (1 << 21)
 218 #define OMAP3430_VP2_EQVALUE_ST                         (1 << 20)
 219 #define OMAP3430_VP2_NOSMPSACK_ST                       (1 << 19)
 220 #define OMAP3430_VP2_MAXVDD_ST                          (1 << 18)
 221 #define OMAP3430_VP2_MINVDD_ST                          (1 << 17)
 222 #define OMAP3430_VP2_OPPCHANGEDONE_ST                   (1 << 16)
 223 #define OMAP3430_VP1_TRANXDONE_ST                       (1 << 15)
 224 #define OMAP3430_VP1_EQVALUE_ST                         (1 << 14)
 225 #define OMAP3430_VP1_NOSMPSACK_ST                       (1 << 13)
 226 #define OMAP3430_VP1_MAXVDD_ST                          (1 << 12)
 227 #define OMAP3430_VP1_MINVDD_ST                          (1 << 11)
 228 #define OMAP3430_VP1_OPPCHANGEDONE_ST                   (1 << 10)
 229 #define OMAP3430_IO_ST                                  (1 << 9)
 230 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST         (1 << 8)
 231 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
 232 #define OMAP3430_MPU_DPLL_ST                            (1 << 7)
 233 #define OMAP3430_MPU_DPLL_ST_SHIFT                      7
 234 #define OMAP3430_PERIPH_DPLL_ST                         (1 << 6)
 235 #define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
 236 #define OMAP3430_CORE_DPLL_ST                           (1 << 5)
 237 #define OMAP3430_CORE_DPLL_ST_SHIFT                     5
 238 #define OMAP3430_TRANSITION_ST                          (1 << 4)
 239 #define OMAP3430_EVGENOFF_ST                            (1 << 3)
 240 #define OMAP3430_EVGENON_ST                             (1 << 2)
 241 #define OMAP3430_FS_USB_WKUP_ST                         (1 << 1)
 242
 243 /* PRM_IRQENABLE_MPU specific bits */
 244 #define OMAP3430_VC_TIMEOUTERR_EN                               (1 << 24)
 245 #define OMAP3430_VC_RAERR_EN                                    (1 << 23)
 246 #define OMAP3430_VC_SAERR_EN                                    (1 << 22)
 247 #define OMAP3430_VP2_TRANXDONE_EN                               (1 << 21)
 248 #define OMAP3430_VP2_EQVALUE_EN                                 (1 << 20)
 249 #define OMAP3430_VP2_NOSMPSACK_EN                               (1 << 19)
 250 #define OMAP3430_VP2_MAXVDD_EN                                  (1 << 18)
 251 #define OMAP3430_VP2_MINVDD_EN                                  (1 << 17)
 252 #define OMAP3430_VP2_OPPCHANGEDONE_EN                           (1 << 16)
 253 #define OMAP3430_VP1_TRANXDONE_EN                               (1 << 15)
 254 #define OMAP3430_VP1_EQVALUE_EN                                 (1 << 14)
 255 #define OMAP3430_VP1_NOSMPSACK_EN                               (1 << 13)
 256 #define OMAP3430_VP1_MAXVDD_EN                                  (1 << 12)
 257 #define OMAP3430_VP1_MINVDD_EN                                  (1 << 11)
 258 #define OMAP3430_VP1_OPPCHANGEDONE_EN                           (1 << 10)
 259 #define OMAP3430_IO_EN                                          (1 << 9)
 260 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN           (1 << 8)
 261 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
 262 #define OMAP3430_MPU_DPLL_RECAL_EN                              (1 << 7)
 263 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
 264 #define OMAP3430_PERIPH_DPLL_RECAL_EN                           (1 << 6)
 265 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
 266 #define OMAP3430_CORE_DPLL_RECAL_EN                             (1 << 5)
 267 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
 268 #define OMAP3430_TRANSITION_EN                                  (1 << 4)
 269 #define OMAP3430_EVGENOFF_EN                                    (1 << 3)
 270 #define OMAP3430_EVGENON_EN                                     (1 << 2)
 271 #define OMAP3430_FS_USB_WKUP_EN                                 (1 << 1)
 272
 273 /* RM_RSTST_MPU specific bits */
 274 #define OMAP3430_EMULATION_MPU_RST                      (1 << 11)
 275
 276 /* PM_WKDEP_MPU specific bits */
 277 #define OMAP3430_PM_WKDEP_MPU_EN_DSS                    (1 << 5)
 278 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2                   (1 << 2)
 279
 280 /* PM_EVGENCTRL_MPU */
 281 #define OMAP3430_OFFLOADMODE_SHIFT                      3
 282 #define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
 283 #define OMAP3430_ONLOADMODE_SHIFT                       1
 284 #define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
 285 #define OMAP3430_ENABLE                                 (1 << 0)
 286
 287 /* PM_EVGENONTIM_MPU */
 288 #define OMAP3430_ONTIMEVAL_SHIFT                        0
 289 #define OMAP3430_ONTIMEVAL_MASK                         (0xffffffff << 0)
 290
 291 /* PM_EVGENOFFTIM_MPU */
 292 #define OMAP3430_OFFTIMEVAL_SHIFT                       0
 293 #define OMAP3430_OFFTIMEVAL_MASK                        (0xffffffff << 0)
 294
 295 /* PM_PWSTCTRL_MPU specific bits */
 296 #define OMAP3430_L2CACHEONSTATE_SHIFT                   16
 297 #define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
 298 #define OMAP3430_L2CACHERETSTATE                        (1 << 8)
 299 #define OMAP3430_LOGICL1CACHERETSTATE                   (1 << 2)
 300
 301 /* PM_PWSTST_MPU specific bits */
 302 #define OMAP3430_L2CACHESTATEST_SHIFT                   6
 303 #define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
 304 #define OMAP3430_LOGICL1CACHESTATEST                    (1 << 2)
 305
 306 /* PM_PREPWSTST_MPU specific bits */
 307 #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
 308 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
 309 #define OMAP3430_LASTLOGICL1CACHESTATEENTERED           (1 << 2)
 310
 311 /* RM_RSTCTRL_CORE */
 312 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON              (1 << 1)
 313 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST                   (1 << 0)
 314
 315 /* RM_RSTST_CORE specific bits */
 316 #define OMAP3430_MODEM_SECURITY_VIOL_RST                (1 << 10)
 317 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON        (1 << 9)
 318 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST             (1 << 8)
 319
 320 /* PM_WKEN1_CORE specific bits */
 321
 322 /* PM_MPUGRPSEL1_CORE specific bits */
 323 #define OMAP3430_GRPSEL_FSHOSTUSB                       (1 << 5)
 324
 325 /* PM_IVA2GRPSEL1_CORE specific bits */
 326
 327 /* PM_WKST1_CORE specific bits */
 328
 329 /* PM_PWSTCTRL_CORE specific bits */
 330 #define OMAP3430_MEM2ONSTATE_SHIFT                      18
 331 #define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
 332 #define OMAP3430_MEM1ONSTATE_SHIFT                      16
 333 #define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
 334 #define OMAP3430_MEM2RETSTATE                           (1 << 9)
 335 #define OMAP3430_MEM1RETSTATE                           (1 << 8)
 336
 337 /* PM_PWSTST_CORE specific bits */
 338 #define OMAP3430_MEM2STATEST_SHIFT                      6
 339 #define OMAP3430_MEM2STATEST_MASK                       (0x3 << 6)
 340 #define OMAP3430_MEM1STATEST_SHIFT                      4
 341 #define OMAP3430_MEM1STATEST_MASK                       (0x3 << 4)
 342
 343 /* PM_PREPWSTST_CORE specific bits */
 344 #define OMAP3430_LASTMEM2STATEENTERED_SHIFT             6
 345 #define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
 346 #define OMAP3430_LASTMEM1STATEENTERED_SHIFT             4
 347 #define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
 348
 349 /* RM_RSTST_GFX specific bits */
 350
 351 /* PM_WKDEP_GFX specific bits */
 352 #define OMAP3430_PM_WKDEP_GFX_EN_IVA2                   (1 << 2)
 353
 354 /* PM_PWSTCTRL_GFX specific bits */
 355
 356 /* PM_PWSTST_GFX specific bits */
 357
 358 /* PM_PREPWSTST_GFX specific bits */
 359
 360 /* PM_WKEN_WKUP specific bits */
 361 #define OMAP3430_EN_IO                                  (1 << 8)
 362
 363 /* PM_MPUGRPSEL_WKUP specific bits */
 364
 365 /* PM_IVA2GRPSEL_WKUP specific bits */
 366
 367 /* PM_WKST_WKUP specific bits */
 368 #define OMAP3430_ST_IO                                  (1 << 8)
 369
 370 /* PRM_CLKSEL */
 371 #define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
 372 #define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
 373
 374 /* PRM_CLKOUT_CTRL */
 375 #define OMAP3430_CLKOUT_EN                              (1 << 7)
 376 #define OMAP3430_CLKOUT_EN_SHIFT                        7
 377
 378 /* RM_RSTST_DSS specific bits */
 379
 380 /* PM_WKEN_DSS */
 381 #define OMAP3430_PM_WKEN_DSS_EN_DSS                     (1 << 0)
 382
 383 /* PM_WKDEP_DSS specific bits */
 384 #define OMAP3430_PM_WKDEP_DSS_EN_IVA2                   (1 << 2)
 385
 386 /* PM_PWSTCTRL_DSS specific bits */
 387
 388 /* PM_PWSTST_DSS specific bits */
 389
 390 /* PM_PREPWSTST_DSS specific bits */
 391
 392 /* RM_RSTST_CAM specific bits */
 393
 394 /* PM_WKDEP_CAM specific bits */
 395 #define OMAP3430_PM_WKDEP_CAM_EN_IVA2                   (1 << 2)
 396
 397 /* PM_PWSTCTRL_CAM specific bits */
 398
 399 /* PM_PWSTST_CAM specific bits */
 400
 401 /* PM_PREPWSTST_CAM specific bits */
 402
 403 /* RM_RSTST_PER specific bits */
 404
 405 /* PM_WKEN_PER specific bits */
 406
 407 /* PM_MPUGRPSEL_PER specific bits */
 408
 409 /* PM_IVA2GRPSEL_PER specific bits */
 410
 411 /* PM_WKST_PER specific bits */
 412
 413 /* PM_WKDEP_PER specific bits */
 414 #define OMAP3430_PM_WKDEP_PER_EN_IVA2                   (1 << 2)
 415
 416 /* PM_PWSTCTRL_PER specific bits */
 417
 418 /* PM_PWSTST_PER specific bits */
 419
 420 /* PM_PREPWSTST_PER specific bits */
 421
 422 /* RM_RSTST_EMU specific bits */
 423
 424 /* PM_PWSTST_EMU specific bits */
 425
 426 /* PRM_VC_SMPS_SA */
 427 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
 428 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
 429 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
 430 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
 431
 432 /* PRM_VC_SMPS_VOL_RA */
 433 #define OMAP3430_VOLRA1_SHIFT                           16
 434 #define OMAP3430_VOLRA1_MASK                            (0xff << 16)
 435 #define OMAP3430_VOLRA0_SHIFT                           0
 436 #define OMAP3430_VOLRA0_MASK                            (0xff << 0)
 437
 438 /* PRM_VC_SMPS_CMD_RA */
 439 #define OMAP3430_CMDRA1_SHIFT                           16
 440 #define OMAP3430_CMDRA1_MASK                            (0xff << 16)
 441 #define OMAP3430_CMDRA0_SHIFT                           0
 442 #define OMAP3430_CMDRA0_MASK                            (0xff << 0)
 443
 444 /* PRM_VC_CMD_VAL_0 specific bits */
 445
 446 /* PRM_VC_CMD_VAL_1 specific bits */
 447
 448 /* PRM_VC_CH_CONF */
 449 #define OMAP3430_CMD1                                   (1 << 20)
 450 #define OMAP3430_RACEN1                                 (1 << 19)
 451 #define OMAP3430_RAC1                                   (1 << 18)
 452 #define OMAP3430_RAV1                                   (1 << 17)
 453 #define OMAP3430_PRM_VC_CH_CONF_SA1                     (1 << 16)
 454 #define OMAP3430_CMD0                                   (1 << 4)
 455 #define OMAP3430_RACEN0                                 (1 << 3)
 456 #define OMAP3430_RAC0                                   (1 << 2)
 457 #define OMAP3430_RAV0                                   (1 << 1)
 458 #define OMAP3430_PRM_VC_CH_CONF_SA0                     (1 << 0)
 459
 460 /* PRM_VC_I2C_CFG */
 461 #define OMAP3430_HSMASTER                               (1 << 5)
 462 #define OMAP3430_SREN                                   (1 << 4)
 463 #define OMAP3430_HSEN                                   (1 << 3)
 464 #define OMAP3430_MCODE_SHIFT                            0
 465 #define OMAP3430_MCODE_MASK                             (0x7 << 0)
 466
 467 /* PRM_VC_BYPASS_VAL */
 468 #define OMAP3430_VALID                                  (1 << 24)
 469 #define OMAP3430_DATA_SHIFT                             16
 470 #define OMAP3430_DATA_MASK                              (0xff << 16)
 471 #define OMAP3430_REGADDR_SHIFT                          8
 472 #define OMAP3430_REGADDR_MASK                           (0xff << 8)
 473 #define OMAP3430_SLAVEADDR_SHIFT                        0
 474 #define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
 475
 476 /* PRM_RSTCTRL */
 477 #define OMAP3430_RST_DPLL3                              (1 << 2)
 478 #define OMAP3430_RST_GS                                 (1 << 1)
 479
 480 /* PRM_RSTTIME */
 481 #define OMAP3430_RSTTIME2_SHIFT                         8
 482 #define OMAP3430_RSTTIME2_MASK                          (0x1f << 8)
 483 #define OMAP3430_RSTTIME1_SHIFT                         0
 484 #define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
 485
 486 /* PRM_RSTST */
 487 #define OMAP3430_ICECRUSHER_RST                         (1 << 10)
 488 #define OMAP3430_ICEPICK_RST                            (1 << 9)
 489 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST               (1 << 8)
 490 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST               (1 << 7)
 491 #define OMAP3430_EXTERNAL_WARM_RST                      (1 << 6)
 492 #define OMAP3430_SECURE_WD_RST                          (1 << 5)
 493 #define OMAP3430_MPU_WD_RST                             (1 << 4)
 494 #define OMAP3430_SECURITY_VIOL_RST                      (1 << 3)
 495 #define OMAP3430_GLOBAL_SW_RST                          (1 << 1)
 496 #define OMAP3430_GLOBAL_COLD_RST                        (1 << 0)
 497
 498 /* PRM_VOLTCTRL */
 499 #define OMAP3430_SEL_VMODE                              (1 << 4)
 500 #define OMAP3430_SEL_OFF                                (1 << 3)
 501 #define OMAP3430_AUTO_OFF                               (1 << 2)
 502 #define OMAP3430_AUTO_RET                               (1 << 1)
 503 #define OMAP3430_AUTO_SLEEP                             (1 << 0)
 504
 505 /* PRM_SRAM_PCHARGE */
 506 #define OMAP3430_PCHARGE_TIME_SHIFT                     0
 507 #define OMAP3430_PCHARGE_TIME_MASK                      (0xff << 0)
 508
 509 /* PRM_CLKSRC_CTRL */
 510 #define OMAP3430_SYSCLKDIV_SHIFT                        6
 511 #define OMAP3430_SYSCLKDIV_MASK                         (0x3 << 6)
 512 #define OMAP3430_AUTOEXTCLKMODE_SHIFT                   3
 513 #define OMAP3430_AUTOEXTCLKMODE_MASK                    (0x3 << 3)
 514 #define OMAP3430_SYSCLKSEL_SHIFT                        0
 515 #define OMAP3430_SYSCLKSEL_MASK                         (0x3 << 0)
 516
 517 /* PRM_VOLTSETUP1 */
 518 #define OMAP3430_SETUP_TIME2_SHIFT                      16
 519 #define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
 520 #define OMAP3430_SETUP_TIME1_SHIFT                      0
 521 #define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
 522
 523 /* PRM_VOLTOFFSET */
 524 #define OMAP3430_OFFSET_TIME_SHIFT                      0
 525 #define OMAP3430_OFFSET_TIME_MASK                       (0xffff << 0)
 526
 527 /* PRM_CLKSETUP */
 528 #define OMAP3430_SETUP_TIME_SHIFT                       0
 529 #define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
 530
 531 /* PRM_POLCTRL */
 532 #define OMAP3430_OFFMODE_POL                            (1 << 3)
 533 #define OMAP3430_CLKOUT_POL                             (1 << 2)
 534 #define OMAP3430_CLKREQ_POL                             (1 << 1)
 535 #define OMAP3430_EXTVOL_POL                             (1 << 0)
 536
 537 /* PRM_VOLTSETUP2 */
 538 #define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
 539 #define OMAP3430_OFFMODESETUPTIME_MASK                  (0xffff << 0)
 540
 541 /* PRM_VP1_CONFIG specific bits */
 542
 543 /* PRM_VP1_VSTEPMIN specific bits */
 544
 545 /* PRM_VP1_VSTEPMAX specific bits */
 546
 547 /* PRM_VP1_VLIMITTO specific bits */
 548
 549 /* PRM_VP1_VOLTAGE specific bits */
 550
 551 /* PRM_VP1_STATUS specific bits */
 552
 553 /* PRM_VP2_CONFIG specific bits */
 554
 555 /* PRM_VP2_VSTEPMIN specific bits */
 556
 557 /* PRM_VP2_VSTEPMAX specific bits */
 558
 559 /* PRM_VP2_VLIMITTO specific bits */
 560
 561 /* PRM_VP2_VOLTAGE specific bits */
 562
 563 /* PRM_VP2_STATUS specific bits */
 564
 565 /* RM_RSTST_NEON specific bits */
 566
 567 /* PM_WKDEP_NEON specific bits */
 568
 569 /* PM_PWSTCTRL_NEON specific bits */
 570
 571 /* PM_PWSTST_NEON specific bits */
 572
 573 /* PM_PREPWSTST_NEON specific bits */
 574
 575 #endif