1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include "prcm-common.h"
20 #define OMAP_PRM_REGADDR(module, reg) \
21 (__force void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
23 #define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
25 #define OMAP2430_PRM_REGADDR(module, reg) \
26 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
27 #define OMAP34XX_PRM_REGADDR(module, reg) \
28 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
32 * Architecture-specific global PRM registers
33 * Use __raw_{read,write}l() with these registers.
35 * With a few exceptions, these are the register names beginning with
36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
37 * IRQSTATUS and IRQENABLE bits.)
41 #define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
42 #define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
44 #define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
45 #define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
47 #define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
48 #define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
49 #define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
50 #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
51 #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
52 #define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
53 #define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
54 #define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
55 #define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
56 #define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
58 #define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
59 #define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
61 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
62 #define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
64 #define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
65 #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
66 #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
67 #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
68 #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
69 #define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
70 #define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
71 #define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
72 #define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
73 #define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
74 #define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
75 #define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
76 #define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
77 #define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
78 #define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
79 #define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
80 #define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
81 #define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
82 #define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
83 #define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
84 #define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
85 #define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
86 #define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
87 #define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
88 #define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
89 #define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
90 #define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
91 #define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
92 #define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
93 #define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
94 #define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
96 #define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
97 #define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
101 /* Read-modify-write bits in a PRM register */
102 static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask,
103 u32 bits, void __iomem *va)
118 * Module specific PRM registers from PRM_BASE + domain offset
120 * Use prm_{read,write}_mod_reg() with these registers.
122 * With a few exceptions, these are the register names beginning with
123 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
124 * and IRQENABLE bits.)
128 /* Registers appearing on both 24xx and 34xx */
130 #define RM_RSTCTRL 0x0050
131 #define RM_RSTTIME 0x0054
132 #define RM_RSTST 0x0058
134 #define PM_WKEN 0x00a0
135 #define PM_WKEN1 PM_WKEN
136 #define PM_WKST 0x00b0
137 #define PM_WKST1 PM_WKST
138 #define PM_WKDEP 0x00c8
139 #define PM_EVGENCTRL 0x00d4
140 #define PM_EVGENONTIM 0x00d8
141 #define PM_EVGENOFFTIM 0x00dc
142 #define PM_PWSTCTRL 0x00e0
143 #define PM_PWSTST 0x00e4
145 #define OMAP3430_PM_MPUGRPSEL 0x00a4
146 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
148 #define OMAP3430_PM_IVAGRPSEL 0x00a8
149 #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
151 #define OMAP3430_PM_PREPWSTST 0x00e8
153 #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
154 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
156 #ifndef __ASSEMBLER__
158 /* Read-modify-write bits in a PRM register (by domain) */
159 static u32 __attribute__((unused)) prm_rmw_mod_reg_bits(u32 mask, u32 bits,
162 return prm_rmw_reg_bits(mask, bits, OMAP_PRM_REGADDR(module, idx));
165 static u32 __attribute__((unused)) prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
167 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
170 static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
172 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
175 /* Architecture-specific registers */
177 #define OMAP24XX_PM_WKEN2 0x00a4
178 #define OMAP24XX_PM_WKST2 0x00b4
180 #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
181 #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
182 #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
183 #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
185 /* Power/reset management domain register get/set */
187 static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val,
190 __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
193 static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module,
196 return __raw_readl(OMAP_PRM_REGADDR(module, idx));
202 * Bits common to specific registers
204 * The 3430 register and bit names are generally used,
205 * since they tend to make more sense
208 /* PM_EVGENONTIM_MPU */
209 /* Named PM_EVEGENONTIM_MPU on the 24XX */
210 #define OMAP_ONTIMEVAL_SHIFT 0
211 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
213 /* PM_EVGENOFFTIM_MPU */
214 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
215 #define OMAP_OFFTIMEVAL_SHIFT 0
216 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
218 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
219 /* Named PRCM_CLKSSETUP on the 24XX */
220 #define OMAP_SETUP_TIME_SHIFT 0
221 #define OMAP_SETUP_TIME_MASK (0xffff << 0)
223 /* PRM_CLKSRC_CTRL */
224 /* Named PRCM_CLKSRC_CTRL on the 24XX */
225 #define OMAP_SYSCLKDIV_SHIFT 6
226 #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
227 #define OMAP_AUTOEXTCLKMODE_SHIFT 3
228 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
229 #define OMAP_SYSCLKSEL_SHIFT 0
230 #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
232 /* PM_EVGENCTRL_MPU */
233 #define OMAP_OFFLOADMODE_SHIFT 3
234 #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
235 #define OMAP_ONLOADMODE_SHIFT 1
236 #define OMAP_ONLOADMODE_MASK (0x3 << 1)
237 #define OMAP_ENABLE (1 << 0)
240 /* Named RM_RSTTIME_WKUP on the 24xx */
241 #define OMAP_RSTTIME2_SHIFT 8
242 #define OMAP_RSTTIME2_MASK (0x1f << 8)
243 #define OMAP_RSTTIME1_SHIFT 0
244 #define OMAP_RSTTIME1_MASK (0xff << 0)
248 /* Named RM_RSTCTRL_WKUP on the 24xx */
249 /* 2420 calls RST_DPLL3 'RST_DPLL' */
250 #define OMAP_RST_DPLL3 (1 << 2)
251 #define OMAP_RST_GS (1 << 1)
255 * Bits common to module-shared registers
257 * Not all registers of a particular type support all of these bits -
258 * check TRM if you are unsure
262 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
264 * 2430: PM_PWSTST_MDM
266 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
267 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
270 #define OMAP_INTRANSITION (1 << 20)
274 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
276 * 2430: PM_PWSTST_MDM
278 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
279 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
282 #define OMAP_POWERSTATEST_SHIFT 0
283 #define OMAP_POWERSTATEST_MASK (0x3 << 0)
286 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
287 * called 'COREWKUP_RST'
289 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
290 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
292 #define OMAP_COREDOMAINWKUP_RST (1 << 3)
295 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
299 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
301 #define OMAP_DOMAINWKUP_RST (1 << 2)
304 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
305 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
309 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
311 #define OMAP_GLOBALWARM_RST (1 << 1)
312 #define OMAP_GLOBALCOLD_RST (1 << 0)
315 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
316 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
320 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
323 #define OMAP_EN_WKUP_SHIFT 4
324 #define OMAP_EN_WKUP_MASK (1 << 4)
327 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
330 * 2430: PM_PWSTCTRL_MDM
332 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
333 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
336 #define OMAP_LOGICRETSTATE (1 << 2)
339 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
340 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
342 * 2430: PM_PWSTCTRL_MDM shared bits
344 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
345 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
346 * PM_PWSTCTRL_NEON shared bits
348 #define OMAP_POWERSTATE_SHIFT 0
349 #define OMAP_POWERSTATE_MASK (0x3 << 0)