arch/arm/mach-omap2/prm.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
   2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
   3
   4 /*
   5  * OMAP2/3 Power/Reset Management (PRM) register definitions
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <asm/io.h>
  19 #include "prcm_common.h"
  20
  21
  22 #define OMAP_PRM_REGADDR(module, reg)   (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + module + reg)
  23
  24 /*
  25  * Architecture-specific global PRM registers
  26  * Use prm_{read,write}_reg() with these registers.
  27  *
  28  * With a few exceptions, these are the register names beginning with
  29  * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
  30  * IRQSTATUS and IRQENABLE bits.)
  31  *
  32  */
  33
  34 #define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
  35 #define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
  36
  37 #define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  38 #define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  39
  40 #define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
  41 #define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
  42 #define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
  43 #define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
  44 #define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
  45 #define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
  46 #define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
  47 #define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
  48 #define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
  49 #define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
  50
  51 #define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
  52 #define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
  53
  54 #define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  55 #define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  56
  57
  58 #define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
  59 #define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
  60 #define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
  61 #define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
  62 #define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
  63 #define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
  64 #define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
  65 #define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
  66 #define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
  67 #define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
  68 #define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
  69 #define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
  70 #define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
  71 #define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
  72 #define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
  73 #define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
  74 #define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
  75 #define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
  76 #define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
  77 #define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
  78 #define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
  79 #define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
  80 #define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
  81 #define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
  82 #define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
  83 #define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
  84 #define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
  85 #define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
  86 #define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
  87 #define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
  88 #define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
  89
  90 #define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
  91 #define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  92
  93 /* Power/reset management global register get/set */
  94
  95 static void __attribute__((unused)) prm_write_reg(u32 val, void __iomem *addr)
  96 {
  97         pr_debug("prm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr);
  98
  99         __raw_writel(val, addr);
 100 }
 101
 102 static u32 __attribute__((unused)) prm_read_reg(void __iomem *addr)
 103 {
 104         return __raw_readl(addr);
 105 }
 106
 107
 108 /*
 109  * Module specific PRM registers from PRM_BASE + domain offset
 110  *
 111  * Use prm_{read,write}_mod_reg() with these registers.
 112  *
 113  * With a few exceptions, these are the register names beginning with
 114  * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
 115  * and IRQENABLE bits.)
 116  *
 117  */
 118
 119 /* Registers appearing on both 24xx and 34xx */
 120
 121 #define RM_RSTCTRL                                      0x0050
 122 #define RM_RSTTIME                                      0x0054
 123 #define RM_RSTST                                        0x0058
 124
 125 #define PM_WKEN1                                        0x00a0
 126 #define PM_WKEN                                         PM_WKEN1
 127 #define PM_WKST                                         0x00b0
 128 #define PM_WKST1                                        PM_WKST
 129 #define PM_WKDEP                                        0x00c8
 130 #define PM_EVGENCTRL                                    0x00d4
 131 #define PM_EVGENONTIM                                   0x00d8
 132 #define PM_EVGENOFFTIM                                  0x00dc
 133 #define PM_PWSTCTRL                                     0x00e0
 134 #define PM_PWSTST                                       0x00e4
 135
 136 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 137 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
 138
 139 #define OMAP3430_PM_IVAGRPSEL                           0x00a8
 140 #define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
 141
 142 #define OMAP3430_PM_PREPWSTST                           0x00e8
 143
 144 #define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
 145 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 146
 147
 148 /* Architecture-specific registers */
 149
 150 #define OMAP24XX_PM_WKEN2                               0x00a4
 151 #define OMAP24XX_PM_WKST2                               0x00b4
 152
 153 #define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
 154 #define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
 155 #define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
 156 #define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
 157
 158
 159 /* Power/reset management domain register get/set */
 160
 161 static void __attribute__((unused)) prm_write_mod_reg(u32 val, s16 module, s16 idx)
 162 {
 163         prm_write_reg(val, OMAP_PRM_REGADDR(module, idx));
 164 }
 165
 166 static u32 __attribute__((unused)) prm_read_mod_reg(s16 module, s16 idx)
 167 {
 168         return prm_read_reg(OMAP_PRM_REGADDR(module, idx));
 169 }
 170
 171
 172 /*
 173  * Bits common to specific registers
 174  *
 175  * The 3430 register and bit names are generally used,
 176  * since they tend to make more sense
 177  */
 178
 179 /* PM_EVGENONTIM_MPU */
 180 /* Named PM_EVEGENONTIM_MPU on the 24XX */
 181 #define OMAP_ONTIMEVAL_SHIFT                            0
 182 #define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
 183
 184 /* PM_EVGENOFFTIM_MPU */
 185 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
 186 #define OMAP_OFFTIMEVAL_SHIFT                           0
 187 #define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
 188
 189 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
 190 /* Named PRCM_CLKSSETUP on the 24XX */
 191 #define OMAP_SETUP_TIME_SHIFT                           0
 192 #define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
 193
 194 /* PRM_CLKSRC_CTRL */
 195 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 196 #define OMAP_SYSCLKDIV_SHIFT                            6
 197 #define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
 198 #define OMAP_AUTOEXTCLKMODE_SHIFT                       3
 199 #define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
 200 #define OMAP_SYSCLKSEL_SHIFT                            0
 201 #define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
 202
 203 /* PM_EVGENCTRL_MPU */
 204 #define OMAP_OFFLOADMODE_SHIFT                          3
 205 #define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
 206 #define OMAP_ONLOADMODE_SHIFT                           1
 207 #define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
 208 #define OMAP_ENABLE                                     (1 << 0)
 209
 210 /* PRM_RSTTIME */
 211 /* Named RM_RSTTIME_WKUP on the 24xx */
 212 #define OMAP_RSTTIME2_SHIFT                             8
 213 #define OMAP_RSTTIME2_MASK                              (0x1f << 8)
 214 #define OMAP_RSTTIME1_SHIFT                             0
 215 #define OMAP_RSTTIME1_MASK                              (0xff << 0)
 216
 217
 218 /* PRM_RSTCTRL */
 219 /* Named RM_RSTCTRL_WKUP on the 24xx */
 220 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 221 #define OMAP_RST_DPLL3                                  (1 << 2)
 222 #define OMAP_RST_GS                                     (1 << 1)
 223
 224
 225 /*
 226  * Bits common to module-shared registers
 227  *
 228  * Not all registers of a particular type support all of these bits -
 229  * check TRM if you are unsure
 230  */
 231
 232 /*
 233  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 234  *
 235  * 2430: PM_PWSTST_MDM
 236  *
 237  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 238  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 239  *       PM_PWSTST_NEON
 240  */
 241 #define OMAP_INTRANSITION                               (1 << 20)
 242
 243
 244 /*
 245  * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
 246  *
 247  * 2430: PM_PWSTST_MDM
 248  *
 249  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 250  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 251  *       PM_PWSTST_NEON
 252  */
 253 #define OMAP_POWERSTATEST_SHIFT                         0
 254 #define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
 255
 256 /*
 257  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
 258  *       called 'COREWKUP_RST'
 259  *
 260  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
 261  *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
 262  */
 263 #define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
 264
 265 /*
 266  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
 267  *
 268  * 2430: RM_RSTST_MDM
 269  *
 270  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 271  */
 272 #define OMAP_DOMAINWKUP_RST                             (1 << 2)
 273
 274 /*
 275  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
 276  *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
 277  *
 278  * 2430: RM_RSTST_MDM
 279  *
 280  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 281  */
 282 #define OMAP_GLOBALWARM_RST                             (1 << 1)
 283 #define OMAP_GLOBALCOLD_RST                             (1 << 0)
 284
 285 /*
 286  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
 287  *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
 288  *
 289  * 2430: PM_WKDEP_MDM
 290  *
 291  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
 292  *       PM_WKDEP_PER
 293  */
 294 #define OMAP_EN_WKUP                                    (1 << 4)
 295
 296 /*
 297  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 298  *       PM_PWSTCTRL_DSP
 299  *
 300  * 2430: PM_PWSTCTRL_MDM
 301  *
 302  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 303  *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 304  *       PM_PWSTCTRL_NEON
 305  */
 306 #define OMAP_LOGICRETSTATE                              (1 << 2)
 307
 308 /*
 309  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 310  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
 311  *
 312  * 2430: PM_PWSTCTRL_MDM shared bits
 313  *
 314  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
 315  *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 316  *       PM_PWSTCTRL_NEON shared bits
 317  */
 318 #define OMAP_POWERSTATE_SHIFT                           0
 319 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 320
 321
 322 #endif