1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include "prcm-common.h"
19 #define OMAP2420_PRM_REGADDR(module, reg) \
20 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21 #define OMAP2430_PRM_REGADDR(module, reg) \
22 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23 #define OMAP34XX_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
27 * Architecture-specific global PRM registers
28 * Use prm_{read,write}_mod_reg() with these registers.
30 * With a few exceptions, these are the register names beginning with
31 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
32 * IRQSTATUS and IRQENABLE bits.)
36 /* 24xx register offsets in OCP_MOD */
37 #define OMAP24XX_PRCM_REVISION_OFFSET 0x0000
38 #define OMAP24XX_PRCM_SYSCONFIG_OFFSET 0x0010
39 #define OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
40 #define OMAP24XX_PRCM_IRQENABLE_MPU_OFFSET 0x001c
42 /* 24xx register offsets in OMAP24XX_GR_MOD (Same as OCP_MOD for 24xx) */
43 #define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050
44 #define OMAP24XX_PRCM_VOLTST_OFFSET 0x0054
45 #define OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET 0x0060
46 #define OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET 0x0070
47 #define OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
48 #define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080
49 #define OMAP24XX_PRCM_CLKCFG_STATUS_OFFSET 0x0084
50 #define OMAP24XX_PRCM_VOLTSETUP_OFFSET 0x0090
51 #define OMAP24XX_PRCM_CLKSSETUP_OFFSET 0x0094
52 #define OMAP24XX_PRCM_POLCTRL_OFFSET 0x0098
54 /* 34xx register offsets in OCP_MOD */
55 #define OMAP3430_PRM_REVISION_OFFSET 0x0004
56 #define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014
57 #define OMAP3430_PRM_IRQSTATUS_MPU_OFFSET 0x0018
58 #define OMAP3430_PRM_IRQENABLE_MPU_OFFSET 0x001c
60 /* 34xx register offsets in GR_MOD */
61 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
62 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
63 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
64 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
65 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
66 #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
67 #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
68 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
69 #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
70 #define OMAP3_PRM_RSTTIME_OFFSET 0x0054
71 #define OMAP3_PRM_RSTST_OFFSET 0x0058
72 #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
73 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
74 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
75 #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
76 #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
77 #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
78 #define OMAP3_PRM_POLCTRL_OFFSET 0x009c
79 #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
80 #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
81 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
82 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
83 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
84 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
85 #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
86 #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
87 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
88 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
89 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
90 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
91 #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
93 /* 34xx register offsets in CCR_MOD */
94 #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
95 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
97 /* These will disappear */
99 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
100 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
103 * Module specific PRM registers from PRM_BASE + domain offset
105 * Use prm_{read,write}_mod_reg() with these registers.
107 * With a few exceptions, these are the register names beginning with
108 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
109 * and IRQENABLE bits.)
113 /* Registers appearing on both 24xx and 34xx */
115 #define RM_RSTCTRL 0x0050
116 #define RM_RSTTIME 0x0054
117 #define RM_RSTST 0x0058
119 #define PM_WKEN 0x00a0
120 #define PM_WKEN1 PM_WKEN
121 #define PM_WKST 0x00b0
122 #define PM_WKST1 PM_WKST
123 #define PM_WKDEP 0x00c8
124 #define PM_EVGENCTRL 0x00d4
125 #define PM_EVGENONTIM 0x00d8
126 #define PM_EVGENOFFTIM 0x00dc
127 #define PM_PWSTCTRL 0x00e0
128 #define PM_PWSTST 0x00e4
130 /* Omap2 specific registers */
131 #define OMAP24XX_PM_WKEN2 0x00a4
132 #define OMAP24XX_PM_WKST2 0x00b4
134 #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
135 #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
136 #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
137 #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
139 /* Omap3 specific registers */
140 #define OMAP3430ES2_PM_WKEN3 0x00f0
141 #define OMAP3430ES2_PM_WKST3 0x00b8
143 #define OMAP3430_PM_MPUGRPSEL 0x00a4
144 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
146 #define OMAP3430_PM_IVAGRPSEL 0x00a8
147 #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
149 #define OMAP3430_PM_PREPWSTST 0x00e8
151 #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
152 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
154 #ifndef __ASSEMBLER__
156 /* Power/reset management domain register get/set */
157 extern u32 prm_read_mod_reg(s16 module, u16 idx);
158 extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
159 extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
161 /* Read-modify-write bits in a PRM register (by domain) */
162 static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
164 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
167 static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
169 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
175 * Bits common to specific registers
177 * The 3430 register and bit names are generally used,
178 * since they tend to make more sense
181 /* PM_EVGENONTIM_MPU */
182 /* Named PM_EVEGENONTIM_MPU on the 24XX */
183 #define OMAP_ONTIMEVAL_SHIFT 0
184 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
186 /* PM_EVGENOFFTIM_MPU */
187 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
188 #define OMAP_OFFTIMEVAL_SHIFT 0
189 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
191 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
192 /* Named PRCM_CLKSSETUP on the 24XX */
193 #define OMAP_SETUP_TIME_SHIFT 0
194 #define OMAP_SETUP_TIME_MASK (0xffff << 0)
196 /* PRM_CLKSRC_CTRL */
197 /* Named PRCM_CLKSRC_CTRL on the 24XX */
198 #define OMAP_SYSCLKDIV_SHIFT 6
199 #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
200 #define OMAP_AUTOEXTCLKMODE_SHIFT 3
201 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
202 #define OMAP_SYSCLKSEL_SHIFT 0
203 #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
205 /* PM_EVGENCTRL_MPU */
206 #define OMAP_OFFLOADMODE_SHIFT 3
207 #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
208 #define OMAP_ONLOADMODE_SHIFT 1
209 #define OMAP_ONLOADMODE_MASK (0x3 << 1)
210 #define OMAP_ENABLE (1 << 0)
213 /* Named RM_RSTTIME_WKUP on the 24xx */
214 #define OMAP_RSTTIME2_SHIFT 8
215 #define OMAP_RSTTIME2_MASK (0x1f << 8)
216 #define OMAP_RSTTIME1_SHIFT 0
217 #define OMAP_RSTTIME1_MASK (0xff << 0)
220 /* Named RM_RSTCTRL_WKUP on the 24xx */
221 /* 2420 calls RST_DPLL3 'RST_DPLL' */
222 #define OMAP_RST_DPLL3 (1 << 2)
223 #define OMAP_RST_GS (1 << 1)
227 * Bits common to module-shared registers
229 * Not all registers of a particular type support all of these bits -
230 * check TRM if you are unsure
234 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
236 * 2430: PM_PWSTST_MDM
238 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
239 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
242 #define OMAP_INTRANSITION (1 << 20)
246 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
248 * 2430: PM_PWSTST_MDM
250 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
251 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
254 #define OMAP_POWERSTATEST_SHIFT 0
255 #define OMAP_POWERSTATEST_MASK (0x3 << 0)
258 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
259 * called 'COREWKUP_RST'
261 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
262 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
264 #define OMAP_COREDOMAINWKUP_RST (1 << 3)
267 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
271 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
273 #define OMAP_DOMAINWKUP_RST (1 << 2)
276 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
277 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
281 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
283 #define OMAP_GLOBALWARM_RST (1 << 1)
284 #define OMAP_GLOBALCOLD_RST (1 << 0)
287 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
288 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
292 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
295 #define OMAP_EN_WKUP_SHIFT 4
296 #define OMAP_EN_WKUP_MASK (1 << 4)
299 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
302 * 2430: PM_PWSTCTRL_MDM
304 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
305 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
308 #define OMAP_LOGICRETSTATE (1 << 2)
311 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
312 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
314 * 2430: PM_PWSTCTRL_MDM shared bits
316 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
317 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
318 * PM_PWSTCTRL_NEON shared bits
320 #define OMAP_POWERSTATE_SHIFT 0
321 #define OMAP_POWERSTATE_MASK (0x3 << 0)