1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <asm/bitops.h>
20 #include "prcm-common.h"
23 #define OMAP_PRM_REGADDR(module, reg) \
24 (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
26 #define OMAP2420_PRM_REGADDR(module, reg) \
27 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
28 #define OMAP2430_PRM_REGADDR(module, reg) \
29 IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
30 #define OMAP34XX_PRM_REGADDR(module, reg) \
31 IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
35 * Architecture-specific global PRM registers
36 * Use prm_{read,write}_reg() with these registers.
38 * With a few exceptions, these are the register names beginning with
39 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
40 * IRQSTATUS and IRQENABLE bits.)
44 #define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
45 #define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
47 #define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
48 #define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
50 #define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
51 #define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
52 #define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
53 #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
54 #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
55 #define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
56 #define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
57 #define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
58 #define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
59 #define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
61 #define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
62 #define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
64 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
65 #define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
67 #define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
68 #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
69 #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
70 #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
71 #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
72 #define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
73 #define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
74 #define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
75 #define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
76 #define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
77 #define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
78 #define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
79 #define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
80 #define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
81 #define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
82 #define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
83 #define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
84 #define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
85 #define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
86 #define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
87 #define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
88 #define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
89 #define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
90 #define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
91 #define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
92 #define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
93 #define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
94 #define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
95 #define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
96 #define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
97 #define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
99 #define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
100 #define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
102 #ifndef __ASSEMBLER__
104 /* Read-modify-write bits in a PRM register */
105 static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask,
106 u32 bits, void __iomem *va)
121 * Module specific PRM registers from PRM_BASE + domain offset
123 * Use prm_{read,write}_mod_reg() with these registers.
125 * With a few exceptions, these are the register names beginning with
126 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
127 * and IRQENABLE bits.)
131 /* Registers appearing on both 24xx and 34xx */
133 #define RM_RSTCTRL 0x0050
134 #define RM_RSTTIME 0x0054
135 #define RM_RSTST 0x0058
137 #define PM_WKEN 0x00a0
138 #define PM_WKEN1 PM_WKEN
139 #define PM_WKST 0x00b0
140 #define PM_WKST1 PM_WKST
141 #define PM_WKDEP 0x00c8
142 #define PM_EVGENCTRL 0x00d4
143 #define PM_EVGENONTIM 0x00d8
144 #define PM_EVGENOFFTIM 0x00dc
145 #define PM_PWSTCTRL 0x00e0
146 #define PM_PWSTST 0x00e4
148 #define OMAP3430_PM_MPUGRPSEL 0x00a4
149 #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
151 #define OMAP3430_PM_IVAGRPSEL 0x00a8
152 #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
154 #define OMAP3430_PM_PREPWSTST 0x00e8
156 #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
157 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
159 /* Read-modify-write bits in a PRM register (by domain) */
160 static u32 __attribute__((unused)) prm_rmw_mod_reg_bits(u32 mask, u32 bits,
163 return prm_rmw_reg_bits(mask, bits, OMAP_PRM_REGADDR(module, idx));
166 static u32 __attribute__((unused)) prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
168 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
171 static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
173 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
176 /* Architecture-specific registers */
178 #define OMAP24XX_PM_WKEN2 0x00a4
179 #define OMAP24XX_PM_WKST2 0x00b4
181 #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
182 #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
183 #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
184 #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
186 #ifndef __ASSEMBLER__
188 /* Power/reset management domain register get/set */
190 static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val,
193 __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
196 static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module,
199 return __raw_readl(OMAP_PRM_REGADDR(module, idx));
205 * Bits common to specific registers
207 * The 3430 register and bit names are generally used,
208 * since they tend to make more sense
211 /* PM_EVGENONTIM_MPU */
212 /* Named PM_EVEGENONTIM_MPU on the 24XX */
213 #define OMAP_ONTIMEVAL_SHIFT 0
214 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
216 /* PM_EVGENOFFTIM_MPU */
217 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
218 #define OMAP_OFFTIMEVAL_SHIFT 0
219 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
221 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
222 /* Named PRCM_CLKSSETUP on the 24XX */
223 #define OMAP_SETUP_TIME_SHIFT 0
224 #define OMAP_SETUP_TIME_MASK (0xffff << 0)
226 /* PRM_CLKSRC_CTRL */
227 /* Named PRCM_CLKSRC_CTRL on the 24XX */
228 #define OMAP_SYSCLKDIV_SHIFT 6
229 #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
230 #define OMAP_AUTOEXTCLKMODE_SHIFT 3
231 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
232 #define OMAP_SYSCLKSEL_SHIFT 0
233 #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
235 /* PM_EVGENCTRL_MPU */
236 #define OMAP_OFFLOADMODE_SHIFT 3
237 #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
238 #define OMAP_ONLOADMODE_SHIFT 1
239 #define OMAP_ONLOADMODE_MASK (0x3 << 1)
240 #define OMAP_ENABLE (1 << 0)
243 /* Named RM_RSTTIME_WKUP on the 24xx */
244 #define OMAP_RSTTIME2_SHIFT 8
245 #define OMAP_RSTTIME2_MASK (0x1f << 8)
246 #define OMAP_RSTTIME1_SHIFT 0
247 #define OMAP_RSTTIME1_MASK (0xff << 0)
251 /* Named RM_RSTCTRL_WKUP on the 24xx */
252 /* 2420 calls RST_DPLL3 'RST_DPLL' */
253 #define OMAP_RST_DPLL3 (1 << 2)
254 #define OMAP_RST_GS (1 << 1)
258 * Bits common to module-shared registers
260 * Not all registers of a particular type support all of these bits -
261 * check TRM if you are unsure
265 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
267 * 2430: PM_PWSTST_MDM
269 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
270 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
273 #define OMAP_INTRANSITION (1 << 20)
277 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
279 * 2430: PM_PWSTST_MDM
281 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
282 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
285 #define OMAP_POWERSTATEST_SHIFT 0
286 #define OMAP_POWERSTATEST_MASK (0x3 << 0)
289 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
290 * called 'COREWKUP_RST'
292 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
293 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
295 #define OMAP_COREDOMAINWKUP_RST (1 << 3)
298 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
302 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
304 #define OMAP_DOMAINWKUP_RST (1 << 2)
307 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
308 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
312 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
314 #define OMAP_GLOBALWARM_RST (1 << 1)
315 #define OMAP_GLOBALCOLD_RST (1 << 0)
318 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
319 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
323 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
326 #define OMAP_EN_WKUP_SHIFT 4
327 #define OMAP_EN_WKUP_MASK (1 << 4)
330 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
333 * 2430: PM_PWSTCTRL_MDM
335 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
336 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
339 #define OMAP_LOGICRETSTATE (1 << 2)
342 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
343 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
345 * 2430: PM_PWSTCTRL_MDM shared bits
347 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
348 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
349 * PM_PWSTCTRL_NEON shared bits
351 #define OMAP_POWERSTATE_SHIFT 0
352 #define OMAP_POWERSTATE_MASK (0x3 << 0)