arch/arm/mach-omap2/prm.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
   2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
   3
   4 /*
   5  * OMAP2/3 Power/Reset Management (PRM) register definitions
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prcm-common.h"
  18
  19 #ifndef __ASSEMBLER__
  20 #define OMAP_PRM_REGADDR(module, reg)                                   \
  21         (__force void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
  22 #else
  23 #define OMAP2420_PRM_REGADDR(module, reg)                               \
  24                         IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
  25 #define OMAP2430_PRM_REGADDR(module, reg)                               \
  26                         IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
  27 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
  28                         IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
  29 #endif
  30
  31 /*
  32  * Architecture-specific global PRM registers
  33  * Use __raw_{read,write}l() with these registers.
  34  *
  35  * With a few exceptions, these are the register names beginning with
  36  * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
  37  * IRQSTATUS and IRQENABLE bits.)
  38  *
  39  */
  40
  41 /* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
  42 #define OMAP24XX_PRCM_VOLTCTRL_OFFSET           0x0050
  43 #define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET        0x0080
  44
  45 /* 242x GR_MOD registers, use these only for assembly code */
  46 #define OMAP242X_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
  47                                                 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
  48 #define OMAP242X_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
  49                                                 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
  50
  51 /* 243x GR_MOD registers, use these only for assembly code */
  52 #define OMAP243X_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
  53                                                 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
  54 #define OMAP243X_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
  55                                                 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
  56
  57 /* These will disappear */
  58 #define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
  59 #define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
  60
  61 #define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  62 #define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  63
  64 #define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
  65 #define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
  66 #define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
  67 #define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
  68 #define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
  69 #define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
  70 #define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
  71 #define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
  72
  73 #define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
  74 #define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
  75
  76 #define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  77 #define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  78
  79 #define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
  80 #define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
  81 #define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
  82 #define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
  83 #define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
  84 #define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
  85 #define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
  86 #define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
  87 #define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
  88 #define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
  89 #define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
  90 #define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
  91 #define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
  92 #define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
  93 #define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
  94 #define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
  95 #define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
  96 #define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
  97 #define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
  98 #define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
  99 #define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
 100 #define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
 101 #define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
 102 #define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
 103 #define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
 104 #define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
 105 #define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
 106 #define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
 107 #define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
 108 #define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
 109 #define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
 110
 111 #define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
 112 #define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 113
 114 #ifndef __ASSEMBLER__
 115
 116 /* Read-modify-write bits in a PRM register */
 117 static __inline__ u32 __attribute__((unused)) prm_rmw_reg_bits(u32 mask,
 118                                                 u32 bits, void __iomem *va)
 119 {
 120         u32 v;
 121
 122         v = __raw_readl(va);
 123         v &= ~mask;
 124         v |= bits;
 125         __raw_writel(v, va);
 126
 127         return v;
 128 }
 129
 130 #endif
 131
 132 /*
 133  * Module specific PRM registers from PRM_BASE + domain offset
 134  *
 135  * Use prm_{read,write}_mod_reg() with these registers.
 136  *
 137  * With a few exceptions, these are the register names beginning with
 138  * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
 139  * and IRQENABLE bits.)
 140  *
 141  */
 142
 143 /* Registers appearing on both 24xx and 34xx */
 144
 145 #define RM_RSTCTRL                                      0x0050
 146 #define RM_RSTTIME                                      0x0054
 147 #define RM_RSTST                                        0x0058
 148
 149 #define PM_WKEN                                         0x00a0
 150 #define PM_WKEN1                                        PM_WKEN
 151 #define PM_WKST                                         0x00b0
 152 #define PM_WKST1                                        PM_WKST
 153 #define PM_WKDEP                                        0x00c8
 154 #define PM_EVGENCTRL                                    0x00d4
 155 #define PM_EVGENONTIM                                   0x00d8
 156 #define PM_EVGENOFFTIM                                  0x00dc
 157 #define PM_PWSTCTRL                                     0x00e0
 158 #define PM_PWSTST                                       0x00e4
 159
 160 /* Omap2 specific registers */
 161 #define OMAP24XX_PM_WKEN2                               0x00a4
 162 #define OMAP24XX_PM_WKST2                               0x00b4
 163
 164 #define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
 165 #define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
 166 #define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
 167 #define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
 168
 169 /* Omap3 specific registers */
 170 #define OMAP3430ES2_PM_WKEN3                            0x00f0
 171 #define OMAP3430ES2_PM_WKST3                            0x00b8
 172
 173 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 174 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
 175
 176 #define OMAP3430_PM_IVAGRPSEL                           0x00a8
 177 #define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
 178
 179 #define OMAP3430_PM_PREPWSTST                           0x00e8
 180
 181 #define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
 182 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 183
 184 #ifndef __ASSEMBLER__
 185
 186 /* Read-modify-write bits in a PRM register (by domain) */
 187 static u32 __attribute__((unused)) prm_rmw_mod_reg_bits(u32 mask, u32 bits,
 188                                                         s16 module, s16 idx)
 189 {
 190         return prm_rmw_reg_bits(mask, bits, OMAP_PRM_REGADDR(module, idx));
 191 }
 192
 193 static u32 __attribute__((unused)) prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 194 {
 195         return prm_rmw_mod_reg_bits(bits, bits, module, idx);
 196 }
 197
 198 static u32 __attribute__((unused)) prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 199 {
 200         return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 201 }
 202
 203 /* Power/reset management domain register get/set */
 204
 205 static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val,
 206                                                         s16 module, s16 idx)
 207 {
 208         __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
 209 }
 210
 211 static __inline__ u32 __attribute__((unused)) prm_read_mod_reg(s16 module,
 212                                                         s16 idx)
 213 {
 214         return __raw_readl(OMAP_PRM_REGADDR(module, idx));
 215 }
 216
 217 #endif
 218
 219 /*
 220  * Bits common to specific registers
 221  *
 222  * The 3430 register and bit names are generally used,
 223  * since they tend to make more sense
 224  */
 225
 226 /* PM_EVGENONTIM_MPU */
 227 /* Named PM_EVEGENONTIM_MPU on the 24XX */
 228 #define OMAP_ONTIMEVAL_SHIFT                            0
 229 #define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
 230
 231 /* PM_EVGENOFFTIM_MPU */
 232 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
 233 #define OMAP_OFFTIMEVAL_SHIFT                           0
 234 #define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
 235
 236 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
 237 /* Named PRCM_CLKSSETUP on the 24XX */
 238 #define OMAP_SETUP_TIME_SHIFT                           0
 239 #define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
 240
 241 /* PRM_CLKSRC_CTRL */
 242 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 243 #define OMAP_SYSCLKDIV_SHIFT                            6
 244 #define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
 245 #define OMAP_AUTOEXTCLKMODE_SHIFT                       3
 246 #define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
 247 #define OMAP_SYSCLKSEL_SHIFT                            0
 248 #define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
 249
 250 /* PM_EVGENCTRL_MPU */
 251 #define OMAP_OFFLOADMODE_SHIFT                          3
 252 #define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
 253 #define OMAP_ONLOADMODE_SHIFT                           1
 254 #define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
 255 #define OMAP_ENABLE                                     (1 << 0)
 256
 257 /* PRM_RSTTIME */
 258 /* Named RM_RSTTIME_WKUP on the 24xx */
 259 #define OMAP_RSTTIME2_SHIFT                             8
 260 #define OMAP_RSTTIME2_MASK                              (0x1f << 8)
 261 #define OMAP_RSTTIME1_SHIFT                             0
 262 #define OMAP_RSTTIME1_MASK                              (0xff << 0)
 263
 264 /* PRM_RSTCTRL */
 265 /* Named RM_RSTCTRL_WKUP on the 24xx */
 266 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 267 #define OMAP_RST_DPLL3                                  (1 << 2)
 268 #define OMAP_RST_GS                                     (1 << 1)
 269
 270
 271 /*
 272  * Bits common to module-shared registers
 273  *
 274  * Not all registers of a particular type support all of these bits -
 275  * check TRM if you are unsure
 276  */
 277
 278 /*
 279  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 280  *
 281  * 2430: PM_PWSTST_MDM
 282  *
 283  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 284  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 285  *       PM_PWSTST_NEON
 286  */
 287 #define OMAP_INTRANSITION                               (1 << 20)
 288
 289
 290 /*
 291  * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
 292  *
 293  * 2430: PM_PWSTST_MDM
 294  *
 295  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 296  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 297  *       PM_PWSTST_NEON
 298  */
 299 #define OMAP_POWERSTATEST_SHIFT                         0
 300 #define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
 301
 302 /*
 303  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
 304  *       called 'COREWKUP_RST'
 305  *
 306  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
 307  *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
 308  */
 309 #define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
 310
 311 /*
 312  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
 313  *
 314  * 2430: RM_RSTST_MDM
 315  *
 316  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 317  */
 318 #define OMAP_DOMAINWKUP_RST                             (1 << 2)
 319
 320 /*
 321  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
 322  *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
 323  *
 324  * 2430: RM_RSTST_MDM
 325  *
 326  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 327  */
 328 #define OMAP_GLOBALWARM_RST                             (1 << 1)
 329 #define OMAP_GLOBALCOLD_RST                             (1 << 0)
 330
 331 /*
 332  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
 333  *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
 334  *
 335  * 2430: PM_WKDEP_MDM
 336  *
 337  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
 338  *       PM_WKDEP_PER
 339  */
 340 #define OMAP_EN_WKUP_SHIFT                              4
 341 #define OMAP_EN_WKUP_MASK                               (1 << 4)
 342
 343 /*
 344  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 345  *       PM_PWSTCTRL_DSP
 346  *
 347  * 2430: PM_PWSTCTRL_MDM
 348  *
 349  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 350  *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 351  *       PM_PWSTCTRL_NEON
 352  */
 353 #define OMAP_LOGICRETSTATE                              (1 << 2)
 354
 355 /*
 356  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 357  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
 358  *
 359  * 2430: PM_PWSTCTRL_MDM shared bits
 360  *
 361  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
 362  *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 363  *       PM_PWSTCTRL_NEON shared bits
 364  */
 365 #define OMAP_POWERSTATE_SHIFT                           0
 366 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 367
 368
 369 #endif