1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
5 * OMAP2/3 PRCM base and module definitions
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 /* Module offsets from both CM_BASE & PRM_BASE */
20 /* Offsets that are the same on 24xx and 34xx */
21 /* Technically OCP_MOD is 34xx only, and PLL_MOD is CCR_MOD on 3430 */
24 #define CORE_MOD 0x200
26 #define WKUP_MOD 0x400
30 /* Chip-specific module offsets */
31 #define OMAP24XX_DSP_MOD 0x800
33 #define OMAP2430_MDM_MOD 0xc00
35 /* IVA2 module is < base on 3430 */
36 #define OMAP3430_IVA2_MOD -0x800
37 #define OMAP3430_CCR_MOD PLL_MOD
38 #define OMAP3430_DSS_MOD 0x600
39 #define OMAP3430_CAM_MOD 0x700
40 #define OMAP3430_PER_MOD 0x800
41 #define OMAP3430_EMU_MOD 0x900
42 #define OMAP3430_GR_MOD 0xa00
43 #define OMAP3430_NEON_MOD 0xb00
46 /* 24XX register bits shared between CM & PRM registers */
48 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
49 #define OMAP2420_EN_MMC_SHIFT 26
50 #define OMAP2420_EN_MMC (1 << 26)
51 #define OMAP24XX_EN_UART2_SHIFT 22
52 #define OMAP24XX_EN_UART2 (1 << 22)
53 #define OMAP24XX_EN_UART1_SHIFT 21
54 #define OMAP24XX_EN_UART1 (1 << 21)
55 #define OMAP24XX_EN_MCSPI2_SHIFT 18
56 #define OMAP24XX_EN_MCSPI2 (1 << 18)
57 #define OMAP24XX_EN_MCSPI1_SHIFT 17
58 #define OMAP24XX_EN_MCSPI1 (1 << 17)
59 #define OMAP24XX_EN_MCBSP2_SHIFT 16
60 #define OMAP24XX_EN_MCBSP2 (1 << 16)
61 #define OMAP24XX_EN_MCBSP1_SHIFT 15
62 #define OMAP24XX_EN_MCBSP1 (1 << 15)
63 #define OMAP24XX_EN_GPT12_SHIFT 14
64 #define OMAP24XX_EN_GPT12 (1 << 14)
65 #define OMAP24XX_EN_GPT11_SHIFT 13
66 #define OMAP24XX_EN_GPT11 (1 << 13)
67 #define OMAP24XX_EN_GPT10_SHIFT 12
68 #define OMAP24XX_EN_GPT10 (1 << 12)
69 #define OMAP24XX_EN_GPT9_SHIFT 11
70 #define OMAP24XX_EN_GPT9 (1 << 11)
71 #define OMAP24XX_EN_GPT8_SHIFT 10
72 #define OMAP24XX_EN_GPT8 (1 << 10)
73 #define OMAP24XX_EN_GPT7_SHIFT 9
74 #define OMAP24XX_EN_GPT7 (1 << 9)
75 #define OMAP24XX_EN_GPT6_SHIFT 8
76 #define OMAP24XX_EN_GPT6 (1 << 8)
77 #define OMAP24XX_EN_GPT5_SHIFT 7
78 #define OMAP24XX_EN_GPT5 (1 << 7)
79 #define OMAP24XX_EN_GPT4_SHIFT 6
80 #define OMAP24XX_EN_GPT4 (1 << 6)
81 #define OMAP24XX_EN_GPT3_SHIFT 5
82 #define OMAP24XX_EN_GPT3 (1 << 5)
83 #define OMAP24XX_EN_GPT2_SHIFT 4
84 #define OMAP24XX_EN_GPT2 (1 << 4)
85 #define OMAP2420_EN_VLYNQ_SHIFT 3
86 #define OMAP2420_EN_VLYNQ (1 << 3)
88 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
89 #define OMAP2430_EN_GPIO5_SHIFT 10
90 #define OMAP2430_EN_GPIO5 (1 << 10)
91 #define OMAP2430_EN_MCSPI3_SHIFT 9
92 #define OMAP2430_EN_MCSPI3 (1 << 9)
93 #define OMAP2430_EN_MMCHS2_SHIFT 8
94 #define OMAP2430_EN_MMCHS2 (1 << 8)
95 #define OMAP2430_EN_MMCHS1_SHIFT 7
96 #define OMAP2430_EN_MMCHS1 (1 << 7)
97 #define OMAP24XX_EN_UART3_SHIFT 2
98 #define OMAP24XX_EN_UART3 (1 << 2)
99 #define OMAP24XX_EN_USB_SHIFT 0
100 #define OMAP24XX_EN_USB (1 << 0)
102 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
103 #define OMAP2430_EN_MDM_INTC_SHIFT 11
104 #define OMAP2430_EN_MDM_INTC (1 << 11)
105 #define OMAP2430_EN_USBHS_SHIFT 6
106 #define OMAP2430_EN_USBHS (1 << 6)
108 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
109 #define OMAP2420_ST_MMC (1 << 26)
110 #define OMAP24XX_ST_UART2 (1 << 22)
111 #define OMAP24XX_ST_UART1 (1 << 21)
112 #define OMAP24XX_ST_MCSPI2 (1 << 18)
113 #define OMAP24XX_ST_MCSPI1 (1 << 17)
114 #define OMAP24XX_ST_GPT12 (1 << 14)
115 #define OMAP24XX_ST_GPT11 (1 << 13)
116 #define OMAP24XX_ST_GPT10 (1 << 12)
117 #define OMAP24XX_ST_GPT9 (1 << 11)
118 #define OMAP24XX_ST_GPT8 (1 << 10)
119 #define OMAP24XX_ST_GPT7 (1 << 9)
120 #define OMAP24XX_ST_GPT6 (1 << 8)
121 #define OMAP24XX_ST_GPT5 (1 << 7)
122 #define OMAP24XX_ST_GPT4 (1 << 6)
123 #define OMAP24XX_ST_GPT3 (1 << 5)
124 #define OMAP24XX_ST_GPT2 (1 << 4)
125 #define OMAP2420_ST_VLYNQ (1 << 3)
127 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
128 #define OMAP2430_ST_MDM_INTC (1 << 11)
129 #define OMAP2430_ST_GPIO5 (1 << 10)
130 #define OMAP2430_ST_MCSPI3 (1 << 9)
131 #define OMAP2430_ST_MMCHS2 (1 << 8)
132 #define OMAP2430_ST_MMCHS1 (1 << 7)
133 #define OMAP2430_ST_USBHS (1 << 6)
134 #define OMAP24XX_ST_UART3 (1 << 2)
135 #define OMAP24XX_ST_USB (1 << 0)
137 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
138 #define OMAP24XX_EN_GPIOS_SHIFT 2
139 #define OMAP24XX_EN_GPIOS (1 << 2)
140 #define OMAP24XX_EN_GPT1_SHIFT 0
141 #define OMAP24XX_EN_GPT1 (1 << 0)
143 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
144 #define OMAP24XX_ST_GPIOS (1 << 2)
145 #define OMAP24XX_ST_GPT1 (1 << 0)
147 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
148 #define OMAP2430_ST_MDM (1 << 0)
151 /* 3430 register bits shared between CM & PRM registers */
153 /* CM_REVISION, PRM_REVISION shared bits */
154 #define OMAP3430_REV_SHIFT 0
155 #define OMAP3430_REV_MASK (0xff << 0)
157 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
158 #define OMAP3430_AUTOIDLE (1 << 0)
160 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
161 #define OMAP3430_EN_MMC2 (1 << 25)
162 #define OMAP3430_EN_MMC2_SHIFT 25
163 #define OMAP3430_EN_MMC1 (1 << 24)
164 #define OMAP3430_EN_MMC1_SHIFT 24
165 #define OMAP3430_EN_MCSPI4 (1 << 21)
166 #define OMAP3430_EN_MCSPI4_SHIFT 21
167 #define OMAP3430_EN_MCSPI3 (1 << 20)
168 #define OMAP3430_EN_MCSPI3_SHIFT 20
169 #define OMAP3430_EN_MCSPI2 (1 << 19)
170 #define OMAP3430_EN_MCSPI2_SHIFT 19
171 #define OMAP3430_EN_MCSPI1 (1 << 18)
172 #define OMAP3430_EN_MCSPI1_SHIFT 18
173 #define OMAP3430_EN_I2C3 (1 << 17)
174 #define OMAP3430_EN_I2C3_SHIFT 17
175 #define OMAP3430_EN_I2C2 (1 << 16)
176 #define OMAP3430_EN_I2C2_SHIFT 16
177 #define OMAP3430_EN_I2C1 (1 << 15)
178 #define OMAP3430_EN_I2C1_SHIFT 15
179 #define OMAP3430_EN_UART2 (1 << 14)
180 #define OMAP3430_EN_UART2_SHIFT 14
181 #define OMAP3430_EN_UART1 (1 << 13)
182 #define OMAP3430_EN_UART1_SHIFT 13
183 #define OMAP3430_EN_GPT11 (1 << 12)
184 #define OMAP3430_EN_GPT11_SHIFT 12
185 #define OMAP3430_EN_GPT10 (1 << 11)
186 #define OMAP3430_EN_GPT10_SHIFT 11
187 #define OMAP3430_EN_MCBSP5 (1 << 10)
188 #define OMAP3430_EN_MCBSP5_SHIFT 10
189 #define OMAP3430_EN_MCBSP1 (1 << 9)
190 #define OMAP3430_EN_MCBSP1_SHIFT 9
191 #define OMAP3430_EN_FSHOSTUSB (1 << 5)
192 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5
193 #define OMAP3430_EN_D2D (1 << 3)
194 #define OMAP3430_EN_D2D_SHIFT 3
196 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
197 #define OMAP3430_EN_HSOTGUSB (1 << 4)
198 #define OMAP3430_EN_HSOTGUSB_SHIFT 4
200 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
201 #define OMAP3430_ST_MMC2 (1 << 25)
202 #define OMAP3430_ST_MMC1 (1 << 24)
203 #define OMAP3430_ST_MCSPI4 (1 << 21)
204 #define OMAP3430_ST_MCSPI3 (1 << 20)
205 #define OMAP3430_ST_MCSPI2 (1 << 19)
206 #define OMAP3430_ST_MCSPI1 (1 << 18)
207 #define OMAP3430_ST_I2C3 (1 << 17)
208 #define OMAP3430_ST_I2C2 (1 << 16)
209 #define OMAP3430_ST_I2C1 (1 << 15)
210 #define OMAP3430_ST_UART2 (1 << 14)
211 #define OMAP3430_ST_UART1 (1 << 13)
212 #define OMAP3430_ST_GPT11 (1 << 12)
213 #define OMAP3430_ST_GPT10 (1 << 11)
214 #define OMAP3430_ST_MCBSP5 (1 << 10)
215 #define OMAP3430_ST_MCBSP1 (1 << 9)
216 #define OMAP3430_ST_FSHOSTUSB (1 << 5)
217 #define OMAP3430_ST_HSOTGUSB (1 << 4)
218 #define OMAP3430_ST_D2D (1 << 3)
220 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
221 #define OMAP3430_EN_GPIO1 (1 << 3)
222 #define OMAP3430_EN_GPIO1_SHIFT 3
223 #define OMAP3430_EN_GPT1 (1 << 0)
224 #define OMAP3430_EN_GPT1_SHIFT 0
226 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
227 #define OMAP3430_EN_SR2 (1 << 7)
228 #define OMAP3430_EN_SR2_SHIFT 7
229 #define OMAP3430_EN_SR1 (1 << 6)
230 #define OMAP3430_EN_SR1_SHIFT 6
232 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
233 #define OMAP3430_EN_GPT12 (1 << 1)
234 #define OMAP3430_EN_GPT12_SHIFT 1
236 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
237 #define OMAP3430_ST_SR2 (1 << 7)
238 #define OMAP3430_ST_SR1 (1 << 6)
239 #define OMAP3430_ST_GPIO1 (1 << 3)
240 #define OMAP3430_ST_GPT12 (1 << 1)
241 #define OMAP3430_ST_GPT1 (1 << 0)
244 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
245 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
246 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
248 #define OMAP3430_EN_MPU (1 << 1)
249 #define OMAP3430_EN_MPU_SHIFT 1
251 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
252 #define OMAP3430_EN_GPIO6 (1 << 17)
253 #define OMAP3430_EN_GPIO6_SHIFT 17
254 #define OMAP3430_EN_GPIO5 (1 << 16)
255 #define OMAP3430_EN_GPIO5_SHIFT 16
256 #define OMAP3430_EN_GPIO4 (1 << 15)
257 #define OMAP3430_EN_GPIO4_SHIFT 15
258 #define OMAP3430_EN_GPIO3 (1 << 14)
259 #define OMAP3430_EN_GPIO3_SHIFT 14
260 #define OMAP3430_EN_GPIO2 (1 << 13)
261 #define OMAP3430_EN_GPIO2_SHIFT 13
262 #define OMAP3430_EN_UART3 (1 << 11)
263 #define OMAP3430_EN_UART3_SHIFT 11
264 #define OMAP3430_EN_GPT9 (1 << 10)
265 #define OMAP3430_EN_GPT9_SHIFT 10
266 #define OMAP3430_EN_GPT8 (1 << 9)
267 #define OMAP3430_EN_GPT8_SHIFT 9
268 #define OMAP3430_EN_GPT7 (1 << 8)
269 #define OMAP3430_EN_GPT7_SHIFT 8
270 #define OMAP3430_EN_GPT6 (1 << 7)
271 #define OMAP3430_EN_GPT6_SHIFT 7
272 #define OMAP3430_EN_GPT5 (1 << 6)
273 #define OMAP3430_EN_GPT5_SHIFT 6
274 #define OMAP3430_EN_GPT4 (1 << 5)
275 #define OMAP3430_EN_GPT4_SHIFT 5
276 #define OMAP3430_EN_GPT3 (1 << 4)
277 #define OMAP3430_EN_GPT3_SHIFT 4
278 #define OMAP3430_EN_GPT2 (1 << 3)
279 #define OMAP3430_EN_GPT2_SHIFT 3
281 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
282 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
283 * be ST_* bits instead? */
284 #define OMAP3430_EN_MCBSP4 (1 << 2)
285 #define OMAP3430_EN_MCBSP4_SHIFT 2
286 #define OMAP3430_EN_MCBSP3 (1 << 1)
287 #define OMAP3430_EN_MCBSP3_SHIFT 1
288 #define OMAP3430_EN_MCBSP2 (1 << 0)
289 #define OMAP3430_EN_MCBSP2_SHIFT 0
291 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
292 #define OMAP3430_ST_GPIO6 (1 << 17)
293 #define OMAP3430_ST_GPIO5 (1 << 16)
294 #define OMAP3430_ST_GPIO4 (1 << 15)
295 #define OMAP3430_ST_GPIO3 (1 << 14)
296 #define OMAP3430_ST_GPIO2 (1 << 13)
297 #define OMAP3430_ST_UART3 (1 << 11)
298 #define OMAP3430_ST_GPT9 (1 << 10)
299 #define OMAP3430_ST_GPT8 (1 << 9)
300 #define OMAP3430_ST_GPT7 (1 << 8)
301 #define OMAP3430_ST_GPT6 (1 << 7)
302 #define OMAP3430_ST_GPT5 (1 << 6)
303 #define OMAP3430_ST_GPT4 (1 << 5)
304 #define OMAP3430_ST_GPT3 (1 << 4)
305 #define OMAP3430_ST_GPT2 (1 << 3)
307 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
308 #define OMAP3430_EN_CORE (1 << 0)