2 * linux/arch/arm/mach-omap2/prcm-reg.h
4 * OMAP24XX Power Reset and Clock Management (PRCM) registers
6 * Copyright (C) 2005 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
24 #define __ARCH_ARM_MACH_OMAP2_PRCM_H
26 /* SET_PERFORMANCE_LEVEL PARAMETERS */
27 #define PRCM_HALF_SPEED 1
28 #define PRCM_FULL_SPEED 2
32 #define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
34 #define PRCM_REVISION PRCM_REG32(0x000)
35 #define PRCM_SYSCONFIG PRCM_REG32(0x010)
36 #define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
37 #define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
38 #define PRCM_VOLTCTRL PRCM_REG32(0x050)
39 #define PRCM_VOLTST PRCM_REG32(0x054)
40 #define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
41 #define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
42 #define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
43 #define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
44 #define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
45 #define PRCM_VOLTSETUP PRCM_REG32(0x090)
46 #define PRCM_CLKSSETUP PRCM_REG32(0x094)
47 #define PRCM_POLCTRL PRCM_REG32(0x098)
50 #define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
51 #define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
52 #define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
53 #define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
54 #define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
55 #define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
56 #define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
57 #define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
58 #define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
59 #define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
60 #define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
61 #define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
62 #define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
63 #define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
64 #define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
65 #define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
66 #define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
67 #define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
68 #define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
69 #define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
72 #define CM_CLKSEL_MPU PRCM_REG32(0x140)
73 #define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
74 #define RM_RSTST_MPU PRCM_REG32(0x158)
75 #define PM_WKDEP_MPU PRCM_REG32(0x1C8)
76 #define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
77 #define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
78 #define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
79 #define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
80 #define PM_PWSTST_MPU PRCM_REG32(0x1E4)
83 #define CM_FCLKEN1_CORE PRCM_REG32(0x200)
84 #define CM_FCLKEN2_CORE PRCM_REG32(0x204)
85 #define CM_FCLKEN3_CORE PRCM_REG32(0x208)
86 #define CM_ICLKEN1_CORE PRCM_REG32(0x210)
87 #define CM_ICLKEN2_CORE PRCM_REG32(0x214)
88 #define CM_ICLKEN3_CORE PRCM_REG32(0x218)
89 #define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
90 #define CM_IDLEST1_CORE PRCM_REG32(0x220)
91 #define CM_IDLEST2_CORE PRCM_REG32(0x224)
92 #define CM_IDLEST3_CORE PRCM_REG32(0x228)
93 #define CM_IDLEST4_CORE PRCM_REG32(0x22C)
94 #define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
95 #define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
96 #define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
97 #define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
98 #define CM_CLKSEL1_CORE PRCM_REG32(0x240)
99 #define CM_CLKSEL2_CORE PRCM_REG32(0x244)
100 #define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
101 #define PM_WKEN1_CORE PRCM_REG32(0x2A0)
102 #define PM_WKEN2_CORE PRCM_REG32(0x2A4)
103 #define PM_WKST1_CORE PRCM_REG32(0x2B0)
104 #define PM_WKST2_CORE PRCM_REG32(0x2B4)
105 #define PM_WKDEP_CORE PRCM_REG32(0x2C8)
106 #define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
107 #define PM_PWSTST_CORE PRCM_REG32(0x2E4)
110 #define CM_FCLKEN_GFX PRCM_REG32(0x300)
111 #define CM_ICLKEN_GFX PRCM_REG32(0x310)
112 #define CM_IDLEST_GFX PRCM_REG32(0x320)
113 #define CM_CLKSEL_GFX PRCM_REG32(0x340)
114 #define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
115 #define RM_RSTCTRL_GFX PRCM_REG32(0x350)
116 #define RM_RSTST_GFX PRCM_REG32(0x358)
117 #define PM_WKDEP_GFX PRCM_REG32(0x3C8)
118 #define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
119 #define PM_PWSTST_GFX PRCM_REG32(0x3E4)
122 #define CM_FCLKEN_WKUP PRCM_REG32(0x400)
123 #define CM_ICLKEN_WKUP PRCM_REG32(0x410)
124 #define CM_IDLEST_WKUP PRCM_REG32(0x420)
125 #define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
126 #define CM_CLKSEL_WKUP PRCM_REG32(0x440)
127 #define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
128 #define RM_RSTTIME_WKUP PRCM_REG32(0x454)
129 #define RM_RSTST_WKUP PRCM_REG32(0x458)
130 #define PM_WKEN_WKUP PRCM_REG32(0x4A0)
131 #define PM_WKST_WKUP PRCM_REG32(0x4B0)
134 #define CM_CLKEN_PLL PRCM_REG32(0x500)
135 #define CM_IDLEST_CKGEN PRCM_REG32(0x520)
136 #define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
137 #define CM_CLKSEL1_PLL PRCM_REG32(0x540)
138 #define CM_CLKSEL2_PLL PRCM_REG32(0x544)
141 #define CM_FCLKEN_DSP PRCM_REG32(0x800)
142 #define CM_ICLKEN_DSP PRCM_REG32(0x810)
143 #define CM_IDLEST_DSP PRCM_REG32(0x820)
144 #define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
145 #define CM_CLKSEL_DSP PRCM_REG32(0x840)
146 #define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
147 #define RM_RSTCTRL_DSP PRCM_REG32(0x850)
148 #define RM_RSTST_DSP PRCM_REG32(0x858)
149 #define PM_WKEN_DSP PRCM_REG32(0x8A0)
150 #define PM_WKDEP_DSP PRCM_REG32(0x8C8)
151 #define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
152 #define PM_PWSTST_DSP PRCM_REG32(0x8E4)
153 #define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
154 #define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
157 #define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
158 #define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
161 #define CM_FCLKEN_MDM PRCM_REG32(0xC00)
162 #define CM_ICLKEN_MDM PRCM_REG32(0xC10)
163 #define CM_IDLEST_MDM PRCM_REG32(0xC20)
164 #define CM_CLKSEL_MDM PRCM_REG32(0xC40)
166 /* FIXME: Move to header for 2430 */
167 #define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
168 #define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
170 #define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
171 #define GPMC_BASE (OMAP24XX_GPMC_BASE)
172 #define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
174 #define GPT1_BASE (OMAP24XX_GPT1)
175 #define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
178 #define DISPC_SYSCONFIG DISP_REG32(0x410)
179 #define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
180 #define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
181 #define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
183 //#define DSP_MMU_SYSCONFIG 0x5A000010
184 #define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
185 //#define IVA_MMU_SYSCONFIG 0x5D000010
186 //#define DSP_DMA_SYSCONFIG 0x00FCC02C
187 #define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
188 #define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
189 #define GPMC_SYSCONFIG GPMC_REG32(0x010)
190 #define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
191 #define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
192 #define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
193 #define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
194 //#define IVA_SYSCONFIG 0x5C060010
195 #define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
196 #define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
197 #define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
198 //#define VLYNQ_SYSCONFIG 0x67FFFE10
200 /* rkw - good cannidates for PM_ to start what nm was trying */
201 #define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
202 #define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
203 #define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
204 #define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
205 #define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
206 #define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
207 #define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
208 #define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
209 #define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
210 #define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
211 #define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
213 #define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
214 #define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
215 #define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
216 #define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
217 #define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
218 #define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
219 #define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
220 #define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
221 #define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
222 #define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
223 #define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
224 #define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
226 #define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
228 #define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
229 #define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
230 #define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
231 #define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
234 #define GPTIMER1_TISTAT GPT1_REG32(0x014)
235 #define GPTIMER1_TISR GPT1_REG32(0x018)
236 #define GPTIMER1_TIER GPT1_REG32(0x01C)
237 #define GPTIMER1_TWER GPT1_REG32(0x020)
238 #define GPTIMER1_TCLR GPT1_REG32(0x024)
239 #define GPTIMER1_TCRR GPT1_REG32(0x028)
240 #define GPTIMER1_TLDR GPT1_REG32(0x02C)
241 #define GPTIMER1_TTGR GPT1_REG32(0x030)
242 #define GPTIMER1_TWPS GPT1_REG32(0x034)
243 #define GPTIMER1_TMAR GPT1_REG32(0x038)
244 #define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
245 #define GPTIMER1_TSICR GPT1_REG32(0x040)
246 #define GPTIMER1_TCAR2 GPT1_REG32(0x044)
248 /* rkw -- base fix up please... */
249 #define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
252 #define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
253 #define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
254 #define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
255 #define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
256 #define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
257 #define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
260 #define GPIO1_BASE GPIOX_BASE(1)
261 #define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
262 #define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
263 #define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
264 #define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
265 #define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
266 #define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
267 #define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
268 #define GPIO1_DATAIN GPIO1_REG32(0x038)
269 #define GPIO1_OE GPIO1_REG32(0x034)
270 #define GPIO1_DATAOUT GPIO1_REG32(0x03C)
273 #define GPIO2_BASE GPIOX_BASE(2)
274 #define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
275 #define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
276 #define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
277 #define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
278 #define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
279 #define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
280 #define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
281 #define GPIO2_DATAIN GPIO2_REG32(0x038)
282 #define GPIO2_OE GPIO2_REG32(0x034)
283 #define GPIO2_DATAOUT GPIO2_REG32(0x03C)
286 #define GPIO3_BASE GPIOX_BASE(3)
287 #define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
288 #define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
289 #define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
290 #define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
291 #define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
292 #define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
293 #define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
294 #define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
295 #define GPIO3_DATAIN GPIO3_REG32(0x038)
296 #define GPIO3_OE GPIO3_REG32(0x034)
297 #define GPIO3_DATAOUT GPIO3_REG32(0x03C)
298 #define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
299 #define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
302 #define GPIO4_BASE GPIOX_BASE(4)
303 #define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
304 #define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
305 #define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
306 #define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
307 #define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
308 #define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
309 #define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
310 #define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
311 #define GPIO4_DATAIN GPIO4_REG32(0x038)
312 #define GPIO4_OE GPIO4_REG32(0x034)
313 #define GPIO4_DATAOUT GPIO4_REG32(0x03C)
314 #define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
315 #define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
319 #define CONTROL_BASE (OMAP24XX_CTRL_BASE)
320 #define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
322 #define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
323 #define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
324 #define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
325 #define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
326 #define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
327 #define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
328 #define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
329 #define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
330 #define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
333 #define CONTROL_DEVCONF CONTROL_REG32(0x274)
335 /* INTERRUPT CONTROLLER */
336 #define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
337 #define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
339 #define INTC1_U_BASE INTC_REG32(0x000)
340 #define INTC_MIR0 INTC_REG32(0x084)
341 #define INTC_MIR_SET0 INTC_REG32(0x08C)
342 #define INTC_MIR_CLEAR0 INTC_REG32(0x088)
343 #define INTC_ISR_CLEAR0 INTC_REG32(0x094)
344 #define INTC_MIR1 INTC_REG32(0x0A4)
345 #define INTC_MIR_SET1 INTC_REG32(0x0AC)
346 #define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
347 #define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
348 #define INTC_MIR2 INTC_REG32(0x0C4)
349 #define INTC_MIR_SET2 INTC_REG32(0x0CC)
350 #define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
351 #define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
352 #define INTC_SIR_IRQ INTC_REG32(0x040)
353 #define INTC_CONTROL INTC_REG32(0x048)
354 #define INTC_ILR11 INTC_REG32(0x12C)
355 #define INTC_ILR32 INTC_REG32(0x180)
356 #define INTC_ILR37 INTC_REG32(0x194)
357 #define INTC_SYSCONFIG INTC_REG32(0x010)
360 #define RAMFW_BASE (0x68005000)
361 #define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
363 #define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
364 #define RAMFW_READPERM0 RAMFW_REG32(0x050)
365 #define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
367 /* GPMC CS1 FPGA ON USER INTERFACE MODULE */
368 //#define DEBUG_BOARD_LED_REGISTER 0x04000014
371 #define GPMC_CONFIG1_0 GPMC_REG32(0x060)
372 #define GPMC_CONFIG2_0 GPMC_REG32(0x064)
373 #define GPMC_CONFIG3_0 GPMC_REG32(0x068)
374 #define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
375 #define GPMC_CONFIG5_0 GPMC_REG32(0x070)
376 #define GPMC_CONFIG6_0 GPMC_REG32(0x074)
377 #define GPMC_CONFIG7_0 GPMC_REG32(0x078)
380 #define GPMC_CONFIG1_1 GPMC_REG32(0x090)
381 #define GPMC_CONFIG2_1 GPMC_REG32(0x094)
382 #define GPMC_CONFIG3_1 GPMC_REG32(0x098)
383 #define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
384 #define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
385 #define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
386 #define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
389 #define DSS_CONTROL DISP_REG32(0x040)
390 #define DISPC_CONTROL DISP_REG32(0x440)
391 #define DISPC_SYSSTATUS DISP_REG32(0x414)
392 #define DISPC_IRQSTATUS DISP_REG32(0x418)
393 #define DISPC_IRQENABLE DISP_REG32(0x41C)
394 #define DISPC_CONFIG DISP_REG32(0x444)
395 #define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
396 #define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
397 #define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
398 #define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
399 #define DISPC_LINE_NUMBER DISP_REG32(0x460)
400 #define DISPC_TIMING_H DISP_REG32(0x464)
401 #define DISPC_TIMING_V DISP_REG32(0x468)
402 #define DISPC_POL_FREQ DISP_REG32(0x46C)
403 #define DISPC_DIVISOR DISP_REG32(0x470)
404 #define DISPC_SIZE_DIG DISP_REG32(0x478)
405 #define DISPC_SIZE_LCD DISP_REG32(0x47C)
406 #define DISPC_GFX_BA0 DISP_REG32(0x480)
407 #define DISPC_GFX_BA1 DISP_REG32(0x484)
408 #define DISPC_GFX_POSITION DISP_REG32(0x488)
409 #define DISPC_GFX_SIZE DISP_REG32(0x48C)
410 #define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
411 #define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
412 #define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
413 #define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
414 #define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
415 #define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
416 #define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
417 #define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
418 #define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
420 /* Wake up define for board */
421 #define GPIO97 (1 << 1)
422 #define GPIO88 (1 << 24)
424 #endif /* __ASSEMBLER__ */