arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <asm/arch/irqs.h>
  39 #include <asm/arch/clock.h>
  40 #include <asm/arch/sram.h>
  41 #include <asm/arch/control.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47
  48 #include "prm.h"
  49 #include "prm-regbits-24xx.h"
  50 #include "cm.h"
  51 #include "cm-regbits-24xx.h"
  52 #include "sdrc.h"
  53 #include "pm.h"
  54
  55 #include <asm/arch/powerdomain.h>
  56 #include <asm/arch/clockdomain.h>
  57
  58 static void (*omap2_sram_idle)(void);
  59 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  60 static void (*saved_idle)(void);
  61
  62 static struct powerdomain *mpu_pwrdm;
  63 static struct powerdomain *core_pwrdm;
  64
  65 static struct clockdomain *dsp_clkdm;
  66 static struct clockdomain *gfx_clkdm;
  67
  68 static struct clk *osc_ck, *emul_ck;
  69
  70 static int omap2_fclks_active(void)
  71 {
  72         u32 f1, f2;
  73
  74         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  75         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  76         serial_console_fclk_mask(&f1, &f2);
  77         if (f1 | f2)
  78                 return 1;
  79         return 0;
  80 }
  81
  82 static void omap2_enter_full_retention(void)
  83 {
  84         u32 l, sleep_time = 0;
  85
  86         /* There is 1 reference hold for all children of the oscillator
  87          * clock, the following will remove it. If no one else uses the
  88          * oscillator itself it will be disabled if/when we enter retention
  89          * mode.
  90          */
  91         clk_disable(osc_ck);
  92
  93         /* Clear old wake-up events */
  94         /* REVISIT: These write to reserved bits? */
  95         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  96         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  97         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  98
  99         /*
 100          * Set MPU powerdomain's next power state to RETENTION;
 101          * preserve logic state during retention
 102          */
 103         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 104         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 105
 106         /* Workaround to kill USB */
 107         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 108         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 109
 110         omap2_gpio_prepare_for_retention();
 111
 112         if (omap2_pm_debug) {
 113                 omap2_pm_dump(0, 0, 0);
 114                 sleep_time = omap2_read_32k_sync_counter();
 115         }
 116
 117         /* One last check for pending IRQs to avoid extra latency due
 118          * to sleeping unnecessarily. */
 119         if (omap_irq_pending())
 120                 goto no_sleep;
 121
 122         serial_console_sleep(1);
 123         /* Jump to SRAM suspend code */
 124         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 125 no_sleep:
 126         serial_console_sleep(0);
 127
 128         if (omap2_pm_debug) {
 129                 unsigned long long tmp;
 130                 u32 resume_time;
 131
 132                 resume_time = omap2_read_32k_sync_counter();
 133                 tmp = resume_time - sleep_time;
 134                 tmp *= 1000000;
 135                 omap2_pm_dump(0, 1, tmp / 32768);
 136         }
 137         omap2_gpio_resume_after_retention();
 138
 139         clk_enable(osc_ck);
 140
 141         /* clear CORE wake-up events */
 142         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 143         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 144
 145         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 146         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 147
 148         /* MPU domain wake events */
 149         l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
 150         if (l & 0x01)
 151                 __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 152         if (l & 0x20)
 153                 __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 154
 155         /* Mask future PRCM-to-MPU interrupts */
 156         __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 157 }
 158
 159 static int omap2_i2c_active(void)
 160 {
 161         u32 l;
 162
 163         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 164         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 165 }
 166
 167 static int sti_console_enabled;
 168
 169 static int omap2_allow_mpu_retention(void)
 170 {
 171         u32 l;
 172
 173         if (atomic_read(&sleep_block))
 174                 return 0;
 175
 176         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 177         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 178         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 179                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 180                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 181                 return 0;
 182         /* Check for UART3. */
 183         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 184         if (l & OMAP24XX_EN_UART3)
 185                 return 0;
 186         if (sti_console_enabled)
 187                 return 0;
 188
 189         return 1;
 190 }
 191
 192 static void omap2_enter_mpu_retention(void)
 193 {
 194         u32 sleep_time = 0;
 195         int only_idle = 0;
 196
 197         /* Putting MPU into the WFI state while a transfer is active
 198          * seems to cause the I2C block to timeout. Why? Good question. */
 199         if (omap2_i2c_active())
 200                 return;
 201
 202         /* The peripherals seem not to be able to wake up the MPU when
 203          * it is in retention mode. */
 204         if (omap2_allow_mpu_retention()) {
 205                 /* REVISIT: These write to reserved bits? */
 206                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 207                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 208                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 209
 210                 /* Try to enter MPU retention */
 211                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 212                                   OMAP_LOGICRETSTATE,
 213                                   MPU_MOD, PM_PWSTCTRL);
 214         } else {
 215                 /* Block MPU retention */
 216
 217                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 218                 only_idle = 1;
 219         }
 220
 221         if (omap2_pm_debug) {
 222                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 223                 sleep_time = omap2_read_32k_sync_counter();
 224         }
 225
 226         omap2_sram_idle();
 227
 228         if (omap2_pm_debug) {
 229                 unsigned long long tmp;
 230                 u32 resume_time;
 231
 232                 resume_time = omap2_read_32k_sync_counter();
 233                 tmp = resume_time - sleep_time;
 234                 tmp *= 1000000;
 235                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 236         }
 237 }
 238
 239 static int omap2_can_sleep(void)
 240 {
 241         if (!enable_dyn_sleep)
 242                 return 0;
 243         if (omap2_fclks_active())
 244                 return 0;
 245         if (atomic_read(&sleep_block) > 0)
 246                 return 0;
 247         if (clk_get_usecount(osc_ck) > 1)
 248                 return 0;
 249         if (omap_dma_running())
 250                 return 0;
 251
 252         return 1;
 253 }
 254
 255 /*
 256  * Note that you can use clock_event_device->min_delta_ns if you want to
 257  * avoid reprogramming timer too often when using CONFIG_NO_HZ.
 258  */
 259 static void omap2_pm_idle(void)
 260 {
 261         local_irq_disable();
 262         local_fiq_disable();
 263
 264         if (!omap2_can_sleep()) {
 265                 if (!atomic_read(&sleep_block) && omap_irq_pending())
 266                         goto out;
 267                 omap2_enter_mpu_retention();
 268                 goto out;
 269         }
 270
 271         if (omap_irq_pending())
 272                 goto out;
 273
 274         omap2_enter_full_retention();
 275
 276 out:
 277         local_fiq_enable();
 278         local_irq_enable();
 279 }
 280
 281 static int omap2_pm_prepare(void)
 282 {
 283         /* We cannot sleep in idle until we have resumed */
 284         saved_idle = pm_idle;
 285         pm_idle = NULL;
 286
 287         return 0;
 288 }
 289
 290 static int omap2_pm_suspend(void)
 291 {
 292         u32 wken_wkup, mir1;
 293
 294         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 295         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 296
 297         /* Mask GPT1 */
 298         mir1 = omap_readl(0x480fe0a4);
 299         omap_writel(1 << 5, 0x480fe0ac);
 300
 301         omap2_enter_full_retention();
 302
 303         omap_writel(mir1, 0x480fe0a4);
 304         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 305
 306         return 0;
 307 }
 308
 309 static int omap2_pm_enter(suspend_state_t state)
 310 {
 311         int ret = 0;
 312
 313         switch (state) {
 314         case PM_SUSPEND_STANDBY:
 315         case PM_SUSPEND_MEM:
 316                 ret = omap2_pm_suspend();
 317                 break;
 318         default:
 319                 ret = -EINVAL;
 320         }
 321
 322         return ret;
 323 }
 324
 325 static void omap2_pm_finish(void)
 326 {
 327         pm_idle = saved_idle;
 328 }
 329
 330 static struct platform_suspend_ops omap_pm_ops = {
 331         .prepare        = omap2_pm_prepare,
 332         .enter          = omap2_pm_enter,
 333         .finish         = omap2_pm_finish,
 334         .valid          = suspend_valid_only_mem,
 335 };
 336
 337 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
 338 {
 339         omap2_clkdm_allow_idle(clkdm);
 340         return 0;
 341 }
 342
 343 static void __init prcm_setup_regs(void)
 344 {
 345         int i, num_mem_banks;
 346         struct powerdomain *pwrdm;
 347
 348         /* Enable autoidle */
 349         __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 350
 351         /* Set all domain wakeup dependencies */
 352         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 353         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 354         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 355         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 356         if (cpu_is_omap2430())
 357                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 358
 359         /*
 360          * Set CORE powerdomain memory banks to retain their contents
 361          * during RETENTION
 362          */
 363         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 364         for (i = 0; i < num_mem_banks; i++)
 365                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 366
 367         /* Set CORE powerdomain's next power state to RETENTION */
 368         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 369
 370         /*
 371          * Set MPU powerdomain's next power state to RETENTION;
 372          * preserve logic state during retention
 373          */
 374         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 375         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 376
 377         /* Force-power down DSP, GFX powerdomains */
 378
 379         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 380         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 381         omap2_clkdm_sleep(dsp_clkdm);
 382
 383         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 384         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 385         omap2_clkdm_sleep(gfx_clkdm);
 386
 387         /* Enable clockdomain hardware-supervised control for all clkdms */
 388         clkdm_for_each(_pm_clkdm_enable_hwsup);
 389
 390         /* Enable clock autoidle for all domains */
 391         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 392                          OMAP24XX_AUTO_MAILBOXES |
 393                          OMAP24XX_AUTO_WDT4 |
 394                          OMAP2420_AUTO_WDT3 |
 395                          OMAP24XX_AUTO_MSPRO |
 396                          OMAP2420_AUTO_MMC |
 397                          OMAP24XX_AUTO_FAC |
 398                          OMAP2420_AUTO_EAC |
 399                          OMAP24XX_AUTO_HDQ |
 400                          OMAP24XX_AUTO_UART2 |
 401                          OMAP24XX_AUTO_UART1 |
 402                          OMAP24XX_AUTO_I2C2 |
 403                          OMAP24XX_AUTO_I2C1 |
 404                          OMAP24XX_AUTO_MCSPI2 |
 405                          OMAP24XX_AUTO_MCSPI1 |
 406                          OMAP24XX_AUTO_MCBSP2 |
 407                          OMAP24XX_AUTO_MCBSP1 |
 408                          OMAP24XX_AUTO_GPT12 |
 409                          OMAP24XX_AUTO_GPT11 |
 410                          OMAP24XX_AUTO_GPT10 |
 411                          OMAP24XX_AUTO_GPT9 |
 412                          OMAP24XX_AUTO_GPT8 |
 413                          OMAP24XX_AUTO_GPT7 |
 414                          OMAP24XX_AUTO_GPT6 |
 415                          OMAP24XX_AUTO_GPT5 |
 416                          OMAP24XX_AUTO_GPT4 |
 417                          OMAP24XX_AUTO_GPT3 |
 418                          OMAP24XX_AUTO_GPT2 |
 419                          OMAP2420_AUTO_VLYNQ |
 420                          OMAP24XX_AUTO_DSS,
 421                          CORE_MOD, CM_AUTOIDLE1);
 422         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 423                          OMAP24XX_AUTO_SSI |
 424                          OMAP24XX_AUTO_USB,
 425                          CORE_MOD, CM_AUTOIDLE2);
 426         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 427                          OMAP24XX_AUTO_GPMC |
 428                          OMAP24XX_AUTO_SDMA,
 429                          CORE_MOD, CM_AUTOIDLE3);
 430         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 431                          OMAP24XX_AUTO_AES |
 432                          OMAP24XX_AUTO_RNG |
 433                          OMAP24XX_AUTO_SHA |
 434                          OMAP24XX_AUTO_DES,
 435                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 436
 437         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 438
 439         /* Put DPLL and both APLLs into autoidle mode */
 440         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 441                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 442                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 443                          PLL_MOD, CM_AUTOIDLE);
 444
 445         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 446                          OMAP24XX_AUTO_WDT1 |
 447                          OMAP24XX_AUTO_MPU_WDT |
 448                          OMAP24XX_AUTO_GPIOS |
 449                          OMAP24XX_AUTO_32KSYNC |
 450                          OMAP24XX_AUTO_GPT1,
 451                          WKUP_MOD, CM_AUTOIDLE);
 452
 453         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 454          * stabilisation */
 455         __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 456
 457         /* Configure automatic voltage transition */
 458         __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 459         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
 460                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 461                       OMAP24XX_MEMRETCTRL |
 462                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 463                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 464                       OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET);
 465
 466         /* Enable wake-up events */
 467         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 468                           WKUP_MOD, PM_WKEN);
 469 }
 470
 471 int __init omap2_pm_init(void)
 472 {
 473         u32 l;
 474
 475         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 476         l = __raw_readl(OMAP24XX_PRCM_REVISION);
 477         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 478
 479         /* Look up important powerdomains, clockdomains */
 480
 481         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 482         if (!mpu_pwrdm)
 483                 pr_err("PM: mpu_pwrdm not found\n");
 484
 485         core_pwrdm = pwrdm_lookup("core_pwrdm");
 486         if (!core_pwrdm)
 487                 pr_err("PM: core_pwrdm not found\n");
 488
 489         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 490         if (!dsp_clkdm)
 491                 pr_err("PM: mpu_clkdm not found\n");
 492
 493         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 494         if (!gfx_clkdm)
 495                 pr_err("PM: gfx_clkdm not found\n");
 496
 497
 498         osc_ck = clk_get(NULL, "osc_ck");
 499         if (IS_ERR(osc_ck)) {
 500                 printk(KERN_ERR "could not get osc_ck\n");
 501                 return -ENODEV;
 502         }
 503
 504         if (cpu_is_omap242x()) {
 505                 emul_ck = clk_get(NULL, "emul_ck");
 506                 if (IS_ERR(emul_ck)) {
 507                         printk(KERN_ERR "could not get emul_ck\n");
 508                         clk_put(osc_ck);
 509                         return -ENODEV;
 510                 }
 511         }
 512
 513         prcm_setup_regs();
 514
 515         pm_init_serial_console();
 516
 517         /* Hack to prevent MPU retention when STI console is enabled. */
 518         {
 519                 const struct omap_sti_console_config *sti;
 520
 521                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 522                                       struct omap_sti_console_config);
 523                 if (sti != NULL && sti->enable)
 524                         sti_console_enabled = 1;
 525         }
 526
 527         /*
 528          * We copy the assembler sleep/wakeup routines to SRAM.
 529          * These routines need to be in SRAM as that's the only
 530          * memory the MPU can see when it wakes up.
 531          */
 532         if (cpu_is_omap242x()) {
 533                 omap2_sram_idle = omap_sram_push(omap242x_idle_loop_suspend,
 534                                                  omap242x_idle_loop_suspend_sz);
 535
 536                 omap2_sram_suspend = omap_sram_push(omap242x_cpu_suspend,
 537                                                     omap242x_cpu_suspend_sz);
 538         } else {
 539                 omap2_sram_idle = omap_sram_push(omap243x_idle_loop_suspend,
 540                                                  omap243x_idle_loop_suspend_sz);
 541
 542                 omap2_sram_suspend = omap_sram_push(omap243x_cpu_suspend,
 543                                                     omap243x_cpu_suspend_sz);
 544         }
 545
 546         suspend_set_ops(&omap_pm_ops);
 547         pm_idle = omap2_pm_idle;
 548
 549         return 0;
 550 }