arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <asm/arch/irqs.h>
  39 #include <asm/arch/clock.h>
  40 #include <asm/arch/sram.h>
  41 #include <asm/arch/control.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47
  48 #include "prm.h"
  49 #include "prm-regbits-24xx.h"
  50 #include "cm.h"
  51 #include "cm-regbits-24xx.h"
  52 #include "sdrc.h"
  53 #include "pm.h"
  54
  55 /* These addrs are in assembly language code to be patched at runtime */
  56 extern void *omap2_ocs_sdrc_power;
  57 extern void *omap2_ocs_sdrc_dlla_ctrl;
  58
  59 static void (*omap2_sram_idle)(void);
  60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  61 static void (*saved_idle)(void);
  62
  63 static struct clk *osc_ck, *emul_ck;
  64
  65 static int omap2_fclks_active(void)
  66 {
  67         u32 f1, f2;
  68
  69         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  70         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  71         serial_console_fclk_mask(&f1, &f2);
  72         if (f1 | f2)
  73                 return 1;
  74         return 0;
  75 }
  76
  77 static void omap2_enter_full_retention(void)
  78 {
  79         u32 l, sleep_time = 0;
  80
  81         /* There is 1 reference hold for all children of the oscillator
  82          * clock, the following will remove it. If no one else uses the
  83          * oscillator itself it will be disabled if/when we enter retention
  84          * mode.
  85          */
  86         clk_disable(osc_ck);
  87
  88         /* Clear old wake-up events */
  89         /* REVISIT: These write to reserved bits? */
  90         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  91         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  92         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  93
  94         /* Try to enter retention */
  95         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
  96                           MPU_MOD, PM_PWSTCTRL);
  97
  98         /* Workaround to kill USB */
  99         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 100         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 101
 102         omap2_gpio_prepare_for_retention();
 103
 104         if (omap2_pm_debug) {
 105                 omap2_pm_dump(0, 0, 0);
 106                 sleep_time = omap2_read_32k_sync_counter();
 107         }
 108
 109         /* One last check for pending IRQs to avoid extra latency due
 110          * to sleeping unnecessarily. */
 111         if (omap_irq_pending())
 112                 goto no_sleep;
 113
 114         serial_console_sleep(1);
 115         /* Jump to SRAM suspend code */
 116         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 117 no_sleep:
 118         serial_console_sleep(0);
 119
 120         if (omap2_pm_debug) {
 121                 unsigned long long tmp;
 122                 u32 resume_time;
 123
 124                 resume_time = omap2_read_32k_sync_counter();
 125                 tmp = resume_time - sleep_time;
 126                 tmp *= 1000000;
 127                 omap2_pm_dump(0, 1, tmp / 32768);
 128         }
 129         omap2_gpio_resume_after_retention();
 130
 131         clk_enable(osc_ck);
 132
 133         /* clear CORE wake-up events */
 134         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 135         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 136
 137         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 138         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 139
 140         /* MPU domain wake events */
 141         l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
 142         if (l & 0x01)
 143                 __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 144         if (l & 0x20)
 145                 __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 146
 147         /* Mask future PRCM-to-MPU interrupts */
 148         __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 149 }
 150
 151 static int omap2_i2c_active(void)
 152 {
 153         u32 l;
 154
 155         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 156         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 157 }
 158
 159 static int sti_console_enabled;
 160
 161 static int omap2_allow_mpu_retention(void)
 162 {
 163         u32 l;
 164
 165         if (atomic_read(&sleep_block))
 166                 return 0;
 167
 168         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 169         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 170         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 171                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 172                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 173                 return 0;
 174         /* Check for UART3. */
 175         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 176         if (l & OMAP24XX_EN_UART3)
 177                 return 0;
 178         if (sti_console_enabled)
 179                 return 0;
 180
 181         return 1;
 182 }
 183
 184 static void omap2_enter_mpu_retention(void)
 185 {
 186         u32 sleep_time = 0;
 187         int only_idle = 0;
 188
 189         /* Putting MPU into the WFI state while a transfer is active
 190          * seems to cause the I2C block to timeout. Why? Good question. */
 191         if (omap2_i2c_active())
 192                 return;
 193
 194         /* The peripherals seem not to be able to wake up the MPU when
 195          * it is in retention mode. */
 196         if (omap2_allow_mpu_retention()) {
 197                 /* REVISIT: These write to reserved bits? */
 198                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 199                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 200                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 201
 202                 /* Try to enter MPU retention */
 203                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 204                                   OMAP_LOGICRETSTATE,
 205                                   MPU_MOD, PM_PWSTCTRL);
 206         } else {
 207                 /* Block MPU retention */
 208
 209                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 210                 only_idle = 1;
 211         }
 212
 213         if (omap2_pm_debug) {
 214                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 215                 sleep_time = omap2_read_32k_sync_counter();
 216         }
 217
 218         omap2_sram_idle();
 219
 220         if (omap2_pm_debug) {
 221                 unsigned long long tmp;
 222                 u32 resume_time;
 223
 224                 resume_time = omap2_read_32k_sync_counter();
 225                 tmp = resume_time - sleep_time;
 226                 tmp *= 1000000;
 227                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 228         }
 229 }
 230
 231 static int omap2_can_sleep(void)
 232 {
 233         if (!enable_dyn_sleep)
 234                 return 0;
 235         if (omap2_fclks_active())
 236                 return 0;
 237         if (atomic_read(&sleep_block) > 0)
 238                 return 0;
 239         if (clk_get_usecount(osc_ck) > 1)
 240                 return 0;
 241         if (omap_dma_running())
 242                 return 0;
 243
 244         return 1;
 245 }
 246
 247 /*
 248  * Note that you can use clock_event_device->min_delta_ns if you want to
 249  * avoid reprogramming timer too often when using CONFIG_NO_HZ.
 250  */
 251 static void omap2_pm_idle(void)
 252 {
 253         local_irq_disable();
 254         local_fiq_disable();
 255
 256         if (!omap2_can_sleep()) {
 257                 if (!atomic_read(&sleep_block) && omap_irq_pending())
 258                         goto out;
 259                 omap2_enter_mpu_retention();
 260                 goto out;
 261         }
 262
 263         if (omap_irq_pending())
 264                 goto out;
 265
 266         omap2_enter_full_retention();
 267
 268 out:
 269         local_fiq_enable();
 270         local_irq_enable();
 271 }
 272
 273 static int omap2_pm_prepare(void)
 274 {
 275         /* We cannot sleep in idle until we have resumed */
 276         saved_idle = pm_idle;
 277         pm_idle = NULL;
 278
 279         return 0;
 280 }
 281
 282 static int omap2_pm_suspend(void)
 283 {
 284         u32 wken_wkup, mir1;
 285
 286         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 287         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 288
 289         /* Mask GPT1 */
 290         mir1 = omap_readl(0x480fe0a4);
 291         omap_writel(1 << 5, 0x480fe0ac);
 292
 293         omap2_enter_full_retention();
 294
 295         omap_writel(mir1, 0x480fe0a4);
 296         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 297
 298         return 0;
 299 }
 300
 301 static int omap2_pm_enter(suspend_state_t state)
 302 {
 303         int ret = 0;
 304
 305         switch (state) {
 306         case PM_SUSPEND_STANDBY:
 307         case PM_SUSPEND_MEM:
 308                 ret = omap2_pm_suspend();
 309                 break;
 310         default:
 311                 ret = -EINVAL;
 312         }
 313
 314         return ret;
 315 }
 316
 317 static void omap2_pm_finish(void)
 318 {
 319         pm_idle = saved_idle;
 320 }
 321
 322 static struct platform_suspend_ops omap_pm_ops = {
 323         .prepare        = omap2_pm_prepare,
 324         .enter          = omap2_pm_enter,
 325         .finish         = omap2_pm_finish,
 326         .valid          = suspend_valid_only_mem,
 327 };
 328
 329 static void __init prcm_setup_regs(void)
 330 {
 331         u32 l;
 332
 333         /* Enable autoidle */
 334         __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 335
 336         /* Set all domain wakeup dependencies */
 337         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 338         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 339         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 340         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 341         if (cpu_is_omap2430())
 342                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 343
 344         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 345         /* Enable retention for all memory blocks */
 346         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 347                 OMAP24XX_MEM1RETSTATE;
 348
 349         /* Set power state to RETENTION */
 350         l &= ~OMAP_POWERSTATE_MASK;
 351         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 352         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 353
 354         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 355                           OMAP_LOGICRETSTATE,
 356                           MPU_MOD, PM_PWSTCTRL);
 357
 358         /* Power down DSP and GFX */
 359         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 360                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 361         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 362                           GFX_MOD, PM_PWSTCTRL);
 363
 364         /* Enable clock auto control for all domains */
 365         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU_MASK, MPU_MOD, CM_CLKSTCTRL);
 366         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS_MASK |
 367                          OMAP24XX_AUTOSTATE_L4_MASK |
 368                          OMAP24XX_AUTOSTATE_L3_MASK,
 369                          CORE_MOD, CM_CLKSTCTRL);
 370         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX_MASK, GFX_MOD, CM_CLKSTCTRL);
 371         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA_MASK |
 372                          OMAP24XX_AUTOSTATE_DSP_MASK,
 373                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 374
 375         /* Enable clock autoidle for all domains */
 376         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 377                          OMAP24XX_AUTO_MAILBOXES |
 378                          OMAP24XX_AUTO_WDT4 |
 379                          OMAP2420_AUTO_WDT3 |
 380                          OMAP24XX_AUTO_MSPRO |
 381                          OMAP2420_AUTO_MMC |
 382                          OMAP24XX_AUTO_FAC |
 383                          OMAP2420_AUTO_EAC |
 384                          OMAP24XX_AUTO_HDQ |
 385                          OMAP24XX_AUTO_UART2 |
 386                          OMAP24XX_AUTO_UART1 |
 387                          OMAP24XX_AUTO_I2C2 |
 388                          OMAP24XX_AUTO_I2C1 |
 389                          OMAP24XX_AUTO_MCSPI2 |
 390                          OMAP24XX_AUTO_MCSPI1 |
 391                          OMAP24XX_AUTO_MCBSP2 |
 392                          OMAP24XX_AUTO_MCBSP1 |
 393                          OMAP24XX_AUTO_GPT12 |
 394                          OMAP24XX_AUTO_GPT11 |
 395                          OMAP24XX_AUTO_GPT10 |
 396                          OMAP24XX_AUTO_GPT9 |
 397                          OMAP24XX_AUTO_GPT8 |
 398                          OMAP24XX_AUTO_GPT7 |
 399                          OMAP24XX_AUTO_GPT6 |
 400                          OMAP24XX_AUTO_GPT5 |
 401                          OMAP24XX_AUTO_GPT4 |
 402                          OMAP24XX_AUTO_GPT3 |
 403                          OMAP24XX_AUTO_GPT2 |
 404                          OMAP2420_AUTO_VLYNQ |
 405                          OMAP24XX_AUTO_DSS,
 406                          CORE_MOD, CM_AUTOIDLE1);
 407         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 408                          OMAP24XX_AUTO_SSI |
 409                          OMAP24XX_AUTO_USB,
 410                          CORE_MOD, CM_AUTOIDLE2);
 411         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 412                          OMAP24XX_AUTO_GPMC |
 413                          OMAP24XX_AUTO_SDMA,
 414                          CORE_MOD, CM_AUTOIDLE3);
 415         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 416                          OMAP24XX_AUTO_AES |
 417                          OMAP24XX_AUTO_RNG |
 418                          OMAP24XX_AUTO_SHA |
 419                          OMAP24XX_AUTO_DES,
 420                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 421
 422         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 423
 424         /* Put DPLL and both APLLs into autoidle mode */
 425         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 426                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 427                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 428                          PLL_MOD, CM_AUTOIDLE);
 429
 430         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 431                          OMAP24XX_AUTO_WDT1 |
 432                          OMAP24XX_AUTO_MPU_WDT |
 433                          OMAP24XX_AUTO_GPIOS |
 434                          OMAP24XX_AUTO_32KSYNC |
 435                          OMAP24XX_AUTO_GPT1,
 436                          WKUP_MOD, CM_AUTOIDLE);
 437
 438         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 439          * stabilisation */
 440         __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 441
 442         /* Configure automatic voltage transition */
 443         __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 444         __raw_writel(OMAP24XX_AUTO_EXTVOLT |
 445                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 446                       OMAP24XX_MEMRETCTRL |
 447                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 448                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 449                       OMAP24XX_PRCM_VOLTCTRL);
 450
 451         /* Enable wake-up events */
 452         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 453                           WKUP_MOD, PM_WKEN);
 454 }
 455
 456 int __init omap2_pm_init(void)
 457 {
 458         u32 l;
 459
 460         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 461         l = __raw_readl(OMAP24XX_PRCM_REVISION);
 462         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 463
 464         osc_ck = clk_get(NULL, "osc_ck");
 465         if (IS_ERR(osc_ck)) {
 466                 printk(KERN_ERR "could not get osc_ck\n");
 467                 return -ENODEV;
 468         }
 469
 470         if (cpu_is_omap242x()) {
 471                 emul_ck = clk_get(NULL, "emul_ck");
 472                 if (IS_ERR(emul_ck)) {
 473                         printk(KERN_ERR "could not get emul_ck\n");
 474                         clk_put(osc_ck);
 475                         return -ENODEV;
 476                 }
 477         }
 478
 479         prcm_setup_regs();
 480
 481         pm_init_serial_console();
 482
 483         /* Hack to prevent MPU retention when STI console is enabled. */
 484         {
 485                 const struct omap_sti_console_config *sti;
 486
 487                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 488                                       struct omap_sti_console_config);
 489                 if (sti != NULL && sti->enable)
 490                         sti_console_enabled = 1;
 491         }
 492
 493         /*
 494          * We copy the assembler sleep/wakeup routines to SRAM.
 495          * These routines need to be in SRAM as that's the only
 496          * memory the MPU can see when it wakes up.
 497          */
 498         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 499                                          omap24xx_idle_loop_suspend_sz);
 500
 501         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 502                                             omap24xx_cpu_suspend_sz);
 503
 504         /* Patch in the correct register addresses for multiboot */
 505         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 506                            omap2_sram_suspend,
 507                            OMAP_SDRC_REGADDR(SDRC_POWER));
 508         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 509                            omap2_sram_suspend,
 510                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 511
 512         suspend_set_ops(&omap_pm_ops);
 513         pm_idle = omap2_pm_idle;
 514
 515         return 0;
 516 }