arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32 #include <linux/irq.h>
  33
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/control.h>
  43 #include <asm/arch/gpio.h>
  44 #include <asm/arch/pm.h>
  45 #include <asm/arch/mux.h>
  46 #include <asm/arch/dma.h>
  47 #include <asm/arch/board.h>
  48
  49 #include "prm.h"
  50 #include "prm-regbits-24xx.h"
  51 #include "cm.h"
  52 #include "cm-regbits-24xx.h"
  53 #include "sdrc.h"
  54
  55 /* These addrs are in assembly language code to be patched at runtime */
  56 extern void *omap2_ocs_sdrc_power;
  57 extern void *omap2_ocs_sdrc_dlla_ctrl;
  58
  59 static void (*omap2_sram_idle)(void);
  60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  61 static void (*saved_idle)(void);
  62
  63 static u32 omap2_read_32k_sync_counter(void)
  64 {
  65         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  66 }
  67
  68 #ifdef CONFIG_PM_DEBUG
  69 int omap2_pm_debug = 0;
  70
  71 static int serial_console_clock_disabled;
  72 static int serial_console_uart;
  73 static unsigned int serial_console_next_disable;
  74
  75 static struct clk *console_iclk, *console_fclk;
  76
  77 static void serial_console_kick(void)
  78 {
  79         serial_console_next_disable = omap2_read_32k_sync_counter();
  80         /* Keep the clocks on for 4 secs */
  81         serial_console_next_disable += 4 * 32768;
  82 }
  83
  84 static void serial_wait_tx(void)
  85 {
  86         static const unsigned long uart_bases[3] = {
  87                 0x4806a000, 0x4806c000, 0x4806e000
  88         };
  89         unsigned long lsr_reg;
  90         int looped = 0;
  91
  92         /* Wait for TX FIFO and THR to get empty */
  93         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  94         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  95                 looped = 1;
  96         if (looped)
  97                 serial_console_kick();
  98 }
  99
 100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 101 {
 102         switch (serial_console_uart)  {
 103         case 1:
 104                 *f1 &= ~(1 << 21);
 105                 break;
 106         case 2:
 107                 *f1 &= ~(1 << 22);
 108                 break;
 109         case 3:
 110                 *f2 &= ~(1 << 2);
 111                 break;
 112         }
 113 }
 114
 115 static void serial_console_sleep(int enable)
 116 {
 117         if (console_iclk == NULL || console_fclk == NULL)
 118                 return;
 119
 120         if (enable) {
 121                 BUG_ON(serial_console_clock_disabled);
 122                 if (clk_get_usecount(console_fclk) == 0)
 123                         return;
 124                 if ((int) serial_console_next_disable -
 125                     (int) omap2_read_32k_sync_counter() >= 0)
 126                         return;
 127                 serial_wait_tx();
 128                 clk_disable(console_iclk);
 129                 clk_disable(console_fclk);
 130                 serial_console_clock_disabled = 1;
 131         } else {
 132                 int serial_wakeup = 0;
 133                 u32 l;
 134
 135                 switch (serial_console_uart)  {
 136                 case 1:
 137                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 138                         if (l & OMAP24XX_ST_UART1)
 139                                 serial_wakeup = 1;
 140                         break;
 141                 case 2:
 142                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 143                         if (l & OMAP24XX_ST_UART2)
 144                                 serial_wakeup = 1;
 145                         break;
 146                 case 3:
 147                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 148                         if (l & OMAP24XX_ST_UART3)
 149                                 serial_wakeup = 1;
 150                         break;
 151                 }
 152                 if (serial_wakeup)
 153                         serial_console_kick();
 154                 if (!serial_console_clock_disabled)
 155                         return;
 156                 clk_enable(console_iclk);
 157                 clk_enable(console_fclk);
 158                 serial_console_clock_disabled = 0;
 159         }
 160 }
 161
 162 static void pm_init_serial_console(void)
 163 {
 164         const struct omap_serial_console_config *conf;
 165         char name[16];
 166
 167         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 168                                struct omap_serial_console_config);
 169         if (conf == NULL)
 170                 return;
 171         if (conf->console_uart > 3 || conf->console_uart < 1)
 172                 return;
 173         serial_console_uart = conf->console_uart;
 174         sprintf(name, "uart%d_fck", conf->console_uart);
 175         console_fclk = clk_get(NULL, name);
 176         if (IS_ERR(console_fclk))
 177                 console_fclk = NULL;
 178         name[6] = 'i';
 179         console_iclk = clk_get(NULL, name);
 180         if (IS_ERR(console_fclk))
 181                 console_iclk = NULL;
 182         if (console_fclk == NULL || console_iclk == NULL) {
 183                 serial_console_uart = 0;
 184                 return;
 185         }
 186         switch (serial_console_uart) {
 187         case 1:
 188                 prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
 189                 break;
 190         case 2:
 191                 prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
 192                 break;
 193         case 3:
 194                 prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD,
 195                                      OMAP24XX_PM_WKEN2);
 196                 break;
 197         }
 198 }
 199
 200 #define DUMP_PRM_MOD_REG(mod, reg)    \
 201         regs[reg_count].name = #mod "." #reg; \
 202         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 203 #define DUMP_CM_MOD_REG(mod, reg)     \
 204         regs[reg_count].name = #mod "." #reg; \
 205         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 206 #define DUMP_PRM_REG(reg) \
 207         regs[reg_count].name = #reg; \
 208         regs[reg_count++].val = __raw_readl(reg)
 209 #define DUMP_CM_REG(reg) \
 210         regs[reg_count].name = #reg; \
 211         regs[reg_count++].val = __raw_readl(reg)
 212 #define DUMP_INTC_REG(reg, off) \
 213         regs[reg_count].name = #reg; \
 214         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 215
 216 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 217 {
 218         struct reg {
 219                 const char *name;
 220                 u32 val;
 221         } regs[32];
 222         int reg_count = 0, i;
 223         const char *s1 = NULL, *s2 = NULL;
 224
 225         if (!resume) {
 226 #if 0
 227                 /* MPU */
 228                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 229                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 230                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 231                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 232                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 233 #endif
 234 #if 0
 235                 /* INTC */
 236                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 237                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 238                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 239 #endif
 240 #if 0
 241                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 242                 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 243                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 244                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 245                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 246                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 247                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
 248                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 249                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 250                 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
 251                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 252 #endif
 253 #if 0
 254                 /* DSP */
 255                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 256                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 257                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 258                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 259                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 261                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 262                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 263                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 264                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 265 #endif
 266         } else {
 267                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 268                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 269                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 270                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 271 #if 1
 272                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 273                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 274                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 275 #endif
 276         }
 277
 278         switch (mode) {
 279         case 0:
 280                 s1 = "full";
 281                 s2 = "retention";
 282                 break;
 283         case 1:
 284                 s1 = "MPU";
 285                 s2 = "retention";
 286                 break;
 287         case 2:
 288                 s1 = "MPU";
 289                 s2 = "idle";
 290                 break;
 291         }
 292
 293         if (!resume)
 294 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 295                 pr_debug("--- Going to %s %s (next timer after %u ms)\n", s1,
 296                          s2,
 297                          jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 298                                           jiffies));
 299 #else
 300                 pr_debug("--- Going to %s %s\n", s1, s2);
 301 #endif
 302         else
 303                 pr_debug("--- Woke up (slept for %u.%03u ms)\n", us / 1000,
 304                          us % 1000);
 305
 306         for (i = 0; i < reg_count; i++)
 307                 pr_debug("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 308 }
 309
 310 #else
 311 static inline void serial_console_sleep(int enable) {}
 312 static inline void pm_init_serial_console(void) {}
 313 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 314 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 315
 316 #define omap2_pm_debug 0
 317
 318 #endif
 319
 320 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 321
 322 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 323                          char *buf)
 324 {
 325         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 326 }
 327
 328 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 329                           const char *buf, size_t n)
 330 {
 331         unsigned short value;
 332         if (sscanf(buf, "%hu", &value) != 1 ||
 333             (value != 0 && value != 1)) {
 334                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 335                 return -EINVAL;
 336         }
 337         enable_dyn_sleep = value;
 338         return n;
 339 }
 340
 341 static struct kobj_attribute sleep_while_idle_attr =
 342         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 343
 344 static struct clk *osc_ck, *emul_ck;
 345
 346 static int omap2_fclks_active(void)
 347 {
 348         u32 f1, f2;
 349
 350         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 351         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 352         serial_console_fclk_mask(&f1, &f2);
 353         if (f1 | f2)
 354                 return 1;
 355         return 0;
 356 }
 357
 358 static int omap2_irq_pending(void)
 359 {
 360         u32 pending_reg = 0x480fe098;
 361         int i;
 362
 363         for (i = 0; i < 4; i++) {
 364                 if (omap_readl(pending_reg))
 365                         return 1;
 366                 pending_reg += 0x20;
 367         }
 368         return 0;
 369 }
 370
 371 static atomic_t sleep_block = ATOMIC_INIT(0);
 372
 373 void omap2_block_sleep(void)
 374 {
 375         atomic_inc(&sleep_block);
 376 }
 377
 378 void omap2_allow_sleep(void)
 379 {
 380         int i;
 381
 382         i = atomic_dec_return(&sleep_block);
 383         BUG_ON(i < 0);
 384 }
 385
 386 static void omap2_enter_full_retention(void)
 387 {
 388         u32 l, sleep_time = 0;
 389
 390         /* There is 1 reference hold for all children of the oscillator
 391          * clock, the following will remove it. If no one else uses the
 392          * oscillator itself it will be disabled if/when we enter retention
 393          * mode.
 394          */
 395         clk_disable(osc_ck);
 396
 397         /* Clear old wake-up events */
 398         /* REVISIT: These write to reserved bits? */
 399         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 400         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 401         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 402
 403         /* Try to enter retention */
 404         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 405                           MPU_MOD, PM_PWSTCTRL);
 406
 407         /* Workaround to kill USB */
 408         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 409         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 410
 411         omap2_gpio_prepare_for_retention();
 412
 413         if (omap2_pm_debug) {
 414                 omap2_pm_dump(0, 0, 0);
 415                 sleep_time = omap2_read_32k_sync_counter();
 416         }
 417
 418         /* One last check for pending IRQs to avoid extra latency due
 419          * to sleeping unnecessarily. */
 420         if (omap2_irq_pending())
 421                 goto no_sleep;
 422
 423         serial_console_sleep(1);
 424         /* Jump to SRAM suspend code */
 425         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 426 no_sleep:
 427         serial_console_sleep(0);
 428
 429         if (omap2_pm_debug) {
 430                 unsigned long long tmp;
 431                 u32 resume_time;
 432
 433                 resume_time = omap2_read_32k_sync_counter();
 434                 tmp = resume_time - sleep_time;
 435                 tmp *= 1000000;
 436                 omap2_pm_dump(0, 1, tmp / 32768);
 437         }
 438         omap2_gpio_resume_after_retention();
 439
 440         clk_enable(osc_ck);
 441
 442         /* clear CORE wake-up events */
 443         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 444         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 445
 446         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 447         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 448
 449         /* MPU domain wake events */
 450         l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
 451         if (l & 0x01)
 452                 __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 453         if (l & 0x20)
 454                 __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 455
 456         /* Mask future PRCM-to-MPU interrupts */
 457         __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 458 }
 459
 460 static int omap2_i2c_active(void)
 461 {
 462         u32 l;
 463
 464         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 465         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 466 }
 467
 468 static int sti_console_enabled;
 469
 470 static int omap2_allow_mpu_retention(void)
 471 {
 472         u32 l;
 473
 474         if (atomic_read(&sleep_block))
 475                 return 0;
 476
 477         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 478         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 479         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 480                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 481                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 482                 return 0;
 483         /* Check for UART3. */
 484         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 485         if (l & OMAP24XX_EN_UART3)
 486                 return 0;
 487         if (sti_console_enabled)
 488                 return 0;
 489
 490         return 1;
 491 }
 492
 493 static void omap2_enter_mpu_retention(void)
 494 {
 495         u32 sleep_time = 0;
 496         int only_idle = 0;
 497
 498         /* Putting MPU into the WFI state while a transfer is active
 499          * seems to cause the I2C block to timeout. Why? Good question. */
 500         if (omap2_i2c_active())
 501                 return;
 502
 503         /* The peripherals seem not to be able to wake up the MPU when
 504          * it is in retention mode. */
 505         if (omap2_allow_mpu_retention()) {
 506                 /* REVISIT: These write to reserved bits? */
 507                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 508                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 509                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 510
 511                 /* Try to enter MPU retention */
 512                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 513                                   OMAP_LOGICRETSTATE,
 514                                   MPU_MOD, PM_PWSTCTRL);
 515         } else {
 516                 /* Block MPU retention */
 517
 518                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 519                 only_idle = 1;
 520         }
 521
 522         if (omap2_pm_debug) {
 523                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 524                 sleep_time = omap2_read_32k_sync_counter();
 525         }
 526
 527         omap2_sram_idle();
 528
 529         if (omap2_pm_debug) {
 530                 unsigned long long tmp;
 531                 u32 resume_time;
 532
 533                 resume_time = omap2_read_32k_sync_counter();
 534                 tmp = resume_time - sleep_time;
 535                 tmp *= 1000000;
 536                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 537         }
 538 }
 539
 540 static int omap2_can_sleep(void)
 541 {
 542         if (!enable_dyn_sleep)
 543                 return 0;
 544         if (omap2_fclks_active())
 545                 return 0;
 546         if (atomic_read(&sleep_block) > 0)
 547                 return 0;
 548         if (clk_get_usecount(osc_ck) > 1)
 549                 return 0;
 550         if (omap_dma_running())
 551                 return 0;
 552
 553         return 1;
 554 }
 555
 556 static void omap2_pm_idle(void)
 557 {
 558         local_irq_disable();
 559         local_fiq_disable();
 560
 561         if (!omap2_can_sleep()) {
 562                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 563                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 564                  * transfer to complete), the increased latency is too much.
 565                  *
 566                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 567                  * to indicate this.
 568                  */
 569                 if (atomic_read(&sleep_block) == 0) {
 570                         timer_dyn_reprogram();
 571                         if (omap2_irq_pending())
 572                                 goto out;
 573                 }
 574                 omap2_enter_mpu_retention();
 575                 goto out;
 576         }
 577
 578         /*
 579          * Since an interrupt may set up a timer, we don't want to
 580          * reprogram the hardware timer with interrupts enabled.
 581          * Re-enable interrupts only after returning from idle.
 582          */
 583         timer_dyn_reprogram();
 584
 585         if (omap2_irq_pending())
 586                 goto out;
 587
 588         omap2_enter_full_retention();
 589
 590 out:
 591         local_fiq_enable();
 592         local_irq_enable();
 593 }
 594
 595 static int omap2_pm_prepare(void)
 596 {
 597         /* We cannot sleep in idle until we have resumed */
 598         saved_idle = pm_idle;
 599         pm_idle = NULL;
 600
 601         return 0;
 602 }
 603
 604 static int omap2_pm_suspend(void)
 605 {
 606         u32 wken_wkup, mir1;
 607
 608         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 609         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 610
 611         /* Mask GPT1 */
 612         mir1 = omap_readl(0x480fe0a4);
 613         omap_writel(1 << 5, 0x480fe0ac);
 614
 615         omap2_enter_full_retention();
 616
 617         omap_writel(mir1, 0x480fe0a4);
 618         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 619
 620         return 0;
 621 }
 622
 623 static int omap2_pm_enter(suspend_state_t state)
 624 {
 625         int ret = 0;
 626
 627         switch (state) {
 628         case PM_SUSPEND_STANDBY:
 629         case PM_SUSPEND_MEM:
 630                 ret = omap2_pm_suspend();
 631                 break;
 632         default:
 633                 ret = -EINVAL;
 634         }
 635
 636         return ret;
 637 }
 638
 639 static void omap2_pm_finish(void)
 640 {
 641         pm_idle = saved_idle;
 642 }
 643
 644 static struct platform_suspend_ops omap_pm_ops = {
 645         .prepare        = omap2_pm_prepare,
 646         .enter          = omap2_pm_enter,
 647         .finish         = omap2_pm_finish,
 648         .valid          = suspend_valid_only_mem,
 649 };
 650
 651 static void __init prcm_setup_regs(void)
 652 {
 653         u32 l;
 654
 655         /* Enable autoidle */
 656         __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 657
 658         /* Set all domain wakeup dependencies */
 659         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 660         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 661         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 662         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 663         if (cpu_is_omap2430())
 664                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 665
 666         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 667         /* Enable retention for all memory blocks */
 668         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 669                 OMAP24XX_MEM1RETSTATE;
 670
 671         /* Set power state to RETENTION */
 672         l &= ~OMAP_POWERSTATE_MASK;
 673         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 674         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 675
 676         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 677                           OMAP_LOGICRETSTATE,
 678                           MPU_MOD, PM_PWSTCTRL);
 679
 680         /* Power down DSP and GFX */
 681         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 682                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 683         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 684                           GFX_MOD, PM_PWSTCTRL);
 685
 686         /* Enable clock auto control for all domains */
 687         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU_MASK, MPU_MOD, CM_CLKSTCTRL);
 688         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS_MASK |
 689                          OMAP24XX_AUTOSTATE_L4_MASK |
 690                          OMAP24XX_AUTOSTATE_L3_MASK,
 691                          CORE_MOD, CM_CLKSTCTRL);
 692         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX_MASK, GFX_MOD, CM_CLKSTCTRL);
 693         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA_MASK |
 694                          OMAP24XX_AUTOSTATE_DSP_MASK,
 695                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 696
 697         /* Enable clock autoidle for all domains */
 698         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 699                          OMAP24XX_AUTO_MAILBOXES |
 700                          OMAP24XX_AUTO_WDT4 |
 701                          OMAP2420_AUTO_WDT3 |
 702                          OMAP24XX_AUTO_MSPRO |
 703                          OMAP2420_AUTO_MMC |
 704                          OMAP24XX_AUTO_FAC |
 705                          OMAP2420_AUTO_EAC |
 706                          OMAP24XX_AUTO_HDQ |
 707                          OMAP24XX_AUTO_UART2 |
 708                          OMAP24XX_AUTO_UART1 |
 709                          OMAP24XX_AUTO_I2C2 |
 710                          OMAP24XX_AUTO_I2C1 |
 711                          OMAP24XX_AUTO_MCSPI2 |
 712                          OMAP24XX_AUTO_MCSPI1 |
 713                          OMAP24XX_AUTO_MCBSP2 |
 714                          OMAP24XX_AUTO_MCBSP1 |
 715                          OMAP24XX_AUTO_GPT12 |
 716                          OMAP24XX_AUTO_GPT11 |
 717                          OMAP24XX_AUTO_GPT10 |
 718                          OMAP24XX_AUTO_GPT9 |
 719                          OMAP24XX_AUTO_GPT8 |
 720                          OMAP24XX_AUTO_GPT7 |
 721                          OMAP24XX_AUTO_GPT6 |
 722                          OMAP24XX_AUTO_GPT5 |
 723                          OMAP24XX_AUTO_GPT4 |
 724                          OMAP24XX_AUTO_GPT3 |
 725                          OMAP24XX_AUTO_GPT2 |
 726                          OMAP2420_AUTO_VLYNQ |
 727                          OMAP24XX_AUTO_DSS,
 728                          CORE_MOD, CM_AUTOIDLE1);
 729         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 730                          OMAP24XX_AUTO_SSI |
 731                          OMAP24XX_AUTO_USB,
 732                          CORE_MOD, CM_AUTOIDLE2);
 733         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 734                          OMAP24XX_AUTO_GPMC |
 735                          OMAP24XX_AUTO_SDMA,
 736                          CORE_MOD, CM_AUTOIDLE3);
 737         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 738                          OMAP24XX_AUTO_AES |
 739                          OMAP24XX_AUTO_RNG |
 740                          OMAP24XX_AUTO_SHA |
 741                          OMAP24XX_AUTO_DES,
 742                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 743
 744         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 745
 746         /* Put DPLL and both APLLs into autoidle mode */
 747         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 748                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 749                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 750                          PLL_MOD, CM_AUTOIDLE);
 751
 752         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 753                          OMAP24XX_AUTO_WDT1 |
 754                          OMAP24XX_AUTO_MPU_WDT |
 755                          OMAP24XX_AUTO_GPIOS |
 756                          OMAP24XX_AUTO_32KSYNC |
 757                          OMAP24XX_AUTO_GPT1,
 758                          WKUP_MOD, CM_AUTOIDLE);
 759
 760         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 761          * stabilisation */
 762         __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 763
 764         /* Configure automatic voltage transition */
 765         __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 766         __raw_writel(OMAP24XX_AUTO_EXTVOLT |
 767                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 768                       OMAP24XX_MEMRETCTRL |
 769                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 770                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 771                       OMAP24XX_PRCM_VOLTCTRL);
 772
 773         /* Enable wake-up events */
 774         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 775                           WKUP_MOD, PM_WKEN);
 776 }
 777
 778 static int __init omap2_pm_init(void)
 779 {
 780         u32 l;
 781         int error;
 782
 783         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 784         l = __raw_readl(OMAP24XX_PRCM_REVISION);
 785         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 786
 787         osc_ck = clk_get(NULL, "osc_ck");
 788         if (IS_ERR(osc_ck)) {
 789                 printk(KERN_ERR "could not get osc_ck\n");
 790                 return -ENODEV;
 791         }
 792
 793         if (cpu_is_omap242x()) {
 794                 emul_ck = clk_get(NULL, "emul_ck");
 795                 if (IS_ERR(emul_ck)) {
 796                         printk(KERN_ERR "could not get emul_ck\n");
 797                         clk_put(osc_ck);
 798                         return -ENODEV;
 799                 }
 800         }
 801
 802         prcm_setup_regs();
 803
 804         pm_init_serial_console();
 805
 806         /* Hack to prevent MPU retention when STI console is enabled. */
 807         {
 808                 const struct omap_sti_console_config *sti;
 809
 810                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 811                                       struct omap_sti_console_config);
 812                 if (sti != NULL && sti->enable)
 813                         sti_console_enabled = 1;
 814         }
 815
 816         /*
 817          * We copy the assembler sleep/wakeup routines to SRAM.
 818          * These routines need to be in SRAM as that's the only
 819          * memory the MPU can see when it wakes up.
 820          */
 821         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 822                                          omap24xx_idle_loop_suspend_sz);
 823
 824         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 825                                             omap24xx_cpu_suspend_sz);
 826
 827         /* Patch in the correct register addresses for multiboot */
 828         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 829                            omap2_sram_suspend,
 830                            OMAP_SDRC_REGADDR(SDRC_POWER));
 831         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 832                            omap2_sram_suspend,
 833                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 834
 835         suspend_set_ops(&omap_pm_ops);
 836         pm_idle = omap2_pm_idle;
 837
 838         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 839         if (error)
 840                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 841
 842         return 0;
 843 }
 844
 845 late_initcall(omap2_pm_init);