arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/pm.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/arch/pm.h>
  44 #include <asm/arch/mux.h>
  45 #include <asm/arch/dma.h>
  46 #include <asm/arch/board.h>
  47 #include <asm/arch/gpio.h>
  48
  49 #include "prm.h"
  50 #include "prm_regbits_24xx.h"
  51 #include "cm.h"
  52 #include "cm_regbits_24xx.h"
  53 #include "sdrc.h"
  54
  55 static void (*omap2_sram_idle)(void);
  56 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  57 static void (*saved_idle)(void);
  58
  59 static u32 omap2_read_32k_sync_counter(void)
  60 {
  61         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  62 }
  63
  64 #ifdef CONFIG_PM_DEBUG
  65 int omap2_pm_debug = 0;
  66
  67 static int serial_console_clock_disabled;
  68 static int serial_console_uart;
  69 static unsigned int serial_console_next_disable;
  70
  71 static struct clk *console_iclk, *console_fclk;
  72
  73 static void serial_console_kick(void)
  74 {
  75         serial_console_next_disable = omap2_read_32k_sync_counter();
  76         /* Keep the clocks on for 4 secs */
  77         serial_console_next_disable += 4 * 32768;
  78 }
  79
  80 static void serial_wait_tx(void)
  81 {
  82         static const unsigned long uart_bases[3] = {
  83                 0x4806a000, 0x4806c000, 0x4806e000
  84         };
  85         unsigned long lsr_reg;
  86         int looped = 0;
  87
  88         /* Wait for TX FIFO and THR to get empty */
  89         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  90         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  91                 looped = 1;
  92         if (looped)
  93                 serial_console_kick();
  94 }
  95
  96 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
  97 {
  98         switch (serial_console_uart)  {
  99         case 1:
 100                 *f1 &= ~(1 << 21);
 101                 break;
 102         case 2:
 103                 *f1 &= ~(1 << 22);
 104                 break;
 105         case 3:
 106                 *f2 &= ~(1 << 2);
 107                 break;
 108         }
 109 }
 110
 111 static void serial_console_sleep(int enable)
 112 {
 113         if (console_iclk == NULL || console_fclk == NULL)
 114                 return;
 115
 116         if (enable) {
 117                 BUG_ON(serial_console_clock_disabled);
 118                 if (clk_get_usecount(console_fclk) == 0)
 119                         return;
 120                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 121                         return;
 122                 serial_wait_tx();
 123                 clk_disable(console_iclk);
 124                 clk_disable(console_fclk);
 125                 serial_console_clock_disabled = 1;
 126         } else {
 127                 int serial_wakeup = 0;
 128                 u32 l;
 129
 130                 switch (serial_console_uart)  {
 131                 case 1:
 132                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 133                         if (l & OMAP24XX_ST_UART1)
 134                                 serial_wakeup = 1;
 135                         break;
 136                 case 2:
 137                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 138                         if (l & OMAP24XX_ST_UART2)
 139                                 serial_wakeup = 1;
 140                         break;
 141                 case 3:
 142                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 143                         if (l & OMAP24XX_ST_UART3)
 144                                 serial_wakeup = 1;
 145                         break;
 146                 }
 147                 if (serial_wakeup)
 148                         serial_console_kick();
 149                 if (!serial_console_clock_disabled)
 150                         return;
 151                 clk_enable(console_iclk);
 152                 clk_enable(console_fclk);
 153                 serial_console_clock_disabled = 0;
 154         }
 155 }
 156
 157 static void pm_init_serial_console(void)
 158 {
 159         const struct omap_serial_console_config *conf;
 160         char name[16];
 161         u32 l;
 162
 163         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 164                                struct omap_serial_console_config);
 165         if (conf == NULL)
 166                 return;
 167         if (conf->console_uart > 3 || conf->console_uart < 1)
 168                 return;
 169         serial_console_uart = conf->console_uart;
 170         sprintf(name, "uart%d_fck", conf->console_uart);
 171         console_fclk = clk_get(NULL, name);
 172         if (IS_ERR(console_fclk))
 173                 console_fclk = NULL;
 174         name[6] = 'i';
 175         console_iclk = clk_get(NULL, name);
 176         if (IS_ERR(console_fclk))
 177                 console_iclk = NULL;
 178         if (console_fclk == NULL || console_iclk == NULL) {
 179                 serial_console_uart = 0;
 180                 return;
 181         }
 182         switch (serial_console_uart) {
 183         case 1:
 184                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 185                 l |= OMAP24XX_ST_UART1;
 186                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 187                 break;
 188         case 2:
 189                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 190                 l |= OMAP24XX_ST_UART2;
 191                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 192                 break;
 193         case 3:
 194                 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
 195                 l |= OMAP24XX_ST_UART3;
 196                 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
 197                 break;
 198         }
 199 }
 200
 201 #define DUMP_PRM_MOD_REG(mod, reg)    \
 202         regs[reg_count].name = #mod "." #reg; \
 203         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 204 #define DUMP_CM_MOD_REG(mod, reg)     \
 205         regs[reg_count].name = #mod "." #reg; \
 206         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 207 #define DUMP_PRM_REG(reg) \
 208         regs[reg_count].name = #reg; \
 209         regs[reg_count++].val = prm_read_reg(reg)
 210 #define DUMP_CM_REG(reg) \
 211         regs[reg_count].name = #reg; \
 212         regs[reg_count++].val = cm_read_reg(reg)
 213 #define DUMP_INTC_REG(reg, off) \
 214         regs[reg_count].name = #reg; \
 215         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 216
 217 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 218 {
 219         struct reg {
 220                 const char *name;
 221                 u32 val;
 222         } regs[32];
 223         int reg_count = 0, i;
 224         const char *s1 = NULL, *s2 = NULL;
 225
 226         if (!resume) {
 227 #if 0
 228                 /* MPU */
 229                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 230                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 231                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 232                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 233                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 234 #endif
 235 #if 0
 236                 /* INTC */
 237                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 238                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 239                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 240 #endif
 241 #if 0
 242                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 243                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
 244                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 245                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 246                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 247                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 248                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
 249                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 250                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 251                 DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
 252                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 253 #endif
 254 #if 0
 255                 /* DSP */
 256                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 257                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 258                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 259                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 261                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 262                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 263                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 264                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 265                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 266 #endif
 267         } else {
 268                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 269                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 270                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 271                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 272 #if 1
 273                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 274                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 275                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 276 #endif
 277         }
 278
 279         switch (mode) {
 280         case 0:
 281                 s1 = "full";
 282                 s2 = "retention";
 283                 break;
 284         case 1:
 285                 s1 = "MPU";
 286                 s2 = "retention";
 287                 break;
 288         case 2:
 289                 s1 = "MPU";
 290                 s2 = "idle";
 291                 break;
 292         }
 293
 294         if (!resume)
 295 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 296                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 297                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 298                                         jiffies));
 299 #else
 300                 printk("--- Going to %s %s\n", s1, s2);
 301 #endif
 302         else
 303                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 304         for (i = 0; i < reg_count; i++)
 305                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 306 }
 307
 308 #else
 309 static inline void serial_console_sleep(int enable) {}
 310 static inline void pm_init_serial_console(void) {}
 311 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 312 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 313
 314 #define omap2_pm_debug 0
 315
 316 #endif
 317
 318 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 319
 320 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
 321 {
 322         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 323 }
 324
 325 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
 326                                               const char * buf,
 327                                               size_t n)
 328 {
 329         unsigned short value;
 330         if (sscanf(buf, "%hu", &value) != 1 ||
 331             (value != 0 && value != 1)) {
 332                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 333                 return -EINVAL;
 334         }
 335         enable_dyn_sleep = value;
 336         return n;
 337 }
 338
 339 static struct subsys_attribute sleep_while_idle_attr = {
 340         .attr   = {
 341                 .name = __stringify(sleep_while_idle),
 342                 .mode = 0644,
 343         },
 344         .show   = omap_pm_sleep_while_idle_show,
 345         .store  = omap_pm_sleep_while_idle_store,
 346 };
 347
 348 static struct clk *osc_ck, *emul_ck;
 349
 350 #define CONTROL_DEVCONF         __REG32(OMAP2_CTRL_BASE + 0x274)
 351
 352 static int omap2_fclks_active(void)
 353 {
 354         u32 f1, f2;
 355
 356         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 357         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 358         serial_console_fclk_mask(&f1, &f2);
 359         if (f1 | f2)
 360                 return 1;
 361         return 0;
 362 }
 363
 364 static int omap2_irq_pending(void)
 365 {
 366         u32 pending_reg = IO_ADDRESS(0x480fe098);
 367         int i;
 368
 369         for (i = 0; i < 4; i++) {
 370                 if (__raw_readl(pending_reg))
 371                         return 1;
 372                 pending_reg += 0x20;
 373         }
 374         return 0;
 375 }
 376
 377 static atomic_t sleep_block = ATOMIC_INIT(0);
 378
 379 void omap2_block_sleep(void)
 380 {
 381         atomic_inc(&sleep_block);
 382 }
 383
 384 void omap2_allow_sleep(void)
 385 {
 386         int i;
 387
 388         i = atomic_dec_return(&sleep_block);
 389         BUG_ON(i < 0);
 390 }
 391
 392 static void omap2_enter_full_retention(void)
 393 {
 394         u32 sleep_time = 0;
 395
 396         /* There is 1 reference hold for all children of the oscillator
 397          * clock, the following will remove it. If no one else uses the
 398          * oscillator itself it will be disabled if/when we enter retention
 399          * mode.
 400          */
 401         clk_disable(osc_ck);
 402
 403         /* Clear old wake-up events */
 404         /* REVISIT: These write to reserved bits? */
 405         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 406         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 407         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 408
 409         /* Try to enter retention */
 410         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 411                           MPU_MOD, PM_PWSTCTRL);
 412
 413         /* Workaround to kill USB */
 414         CONTROL_DEVCONF |= 0x00008000;
 415
 416         omap2_gpio_prepare_for_retention();
 417
 418         if (omap2_pm_debug) {
 419                 omap2_pm_dump(0, 0, 0);
 420                 sleep_time = omap2_read_32k_sync_counter();
 421         }
 422
 423         /* One last check for pending IRQs to avoid extra latency due
 424          * to sleeping unnecessarily. */
 425         if (omap2_irq_pending())
 426                 goto no_sleep;
 427
 428         serial_console_sleep(1);
 429         /* Jump to SRAM suspend code */
 430         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 431 no_sleep:
 432         serial_console_sleep(0);
 433
 434         if (omap2_pm_debug) {
 435                 unsigned long long tmp;
 436                 u32 resume_time;
 437
 438                 resume_time = omap2_read_32k_sync_counter();
 439                 tmp = resume_time - sleep_time;
 440                 tmp *= 1000000;
 441                 omap2_pm_dump(0, 1, tmp / 32768);
 442         }
 443         omap2_gpio_resume_after_retention();
 444
 445         clk_enable(osc_ck);
 446
 447 }
 448
 449 static int omap2_i2c_active(void)
 450 {
 451         u32 l;
 452
 453         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 454         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 455 }
 456
 457 static int sti_console_enabled;
 458
 459 static int omap2_allow_mpu_retention(void)
 460 {
 461         u32 l;
 462
 463         if (atomic_read(&sleep_block))
 464                 return 0;
 465
 466         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 467         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 468         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 469                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 470                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 471                 return 0;
 472         /* Check for UART3. */
 473         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 474         if (l & OMAP24XX_EN_UART3)
 475                 return 0;
 476         if (sti_console_enabled)
 477                 return 0;
 478
 479         return 1;
 480 }
 481
 482 static void omap2_enter_mpu_retention(void)
 483 {
 484         u32 sleep_time = 0;
 485         int only_idle = 0;
 486
 487         /* Putting MPU into the WFI state while a transfer is active
 488          * seems to cause the I2C block to timeout. Why? Good question. */
 489         if (omap2_i2c_active())
 490                 return;
 491
 492         /* The peripherals seem not to be able to wake up the MPU when
 493          * it is in retention mode. */
 494         if (omap2_allow_mpu_retention()) {
 495                 /* REVISIT: These write to reserved bits? */
 496                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 497                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 498                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 499
 500                 /* Try to enter MPU retention */
 501                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 502                                   OMAP_LOGICRETSTATE,
 503                                   MPU_MOD, PM_PWSTCTRL);
 504         } else {
 505                 /* Block MPU retention */
 506
 507                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 508                 only_idle = 1;
 509         }
 510
 511         if (omap2_pm_debug) {
 512                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 513                 sleep_time = omap2_read_32k_sync_counter();
 514         }
 515
 516         omap2_sram_idle();
 517
 518         if (omap2_pm_debug) {
 519                 unsigned long long tmp;
 520                 u32 resume_time;
 521
 522                 resume_time = omap2_read_32k_sync_counter();
 523                 tmp = resume_time - sleep_time;
 524                 tmp *= 1000000;
 525                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 526         }
 527 }
 528
 529 static int omap2_can_sleep(void)
 530 {
 531         if (!enable_dyn_sleep)
 532                 return 0;
 533         if (omap2_fclks_active())
 534                 return 0;
 535         if (atomic_read(&sleep_block) > 0)
 536                 return 0;
 537         if (clk_get_usecount(osc_ck) > 1)
 538                 return 0;
 539         if (omap_dma_running())
 540                 return 0;
 541
 542         return 1;
 543 }
 544
 545 static void omap2_pm_idle(void)
 546 {
 547         local_irq_disable();
 548         local_fiq_disable();
 549
 550         if (!omap2_can_sleep()) {
 551                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 552                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 553                  * transfer to complete), the increased latency is too much.
 554                  *
 555                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 556                  * to indicate this.
 557                  */
 558                 if (atomic_read(&sleep_block) == 0) {
 559                         timer_dyn_reprogram();
 560                         if (omap2_irq_pending())
 561                                 goto out;
 562                 }
 563                 omap2_enter_mpu_retention();
 564                 goto out;
 565         }
 566
 567         /*
 568          * Since an interrupt may set up a timer, we don't want to
 569          * reprogram the hardware timer with interrupts enabled.
 570          * Re-enable interrupts only after returning from idle.
 571          */
 572         timer_dyn_reprogram();
 573
 574         if (omap2_irq_pending())
 575                 goto out;
 576
 577         omap2_enter_full_retention();
 578
 579 out:
 580         local_fiq_enable();
 581         local_irq_enable();
 582 }
 583
 584 static int omap2_pm_prepare(suspend_state_t state)
 585 {
 586         int error = 0;
 587
 588         /* We cannot sleep in idle until we have resumed */
 589         saved_idle = pm_idle;
 590         pm_idle = NULL;
 591
 592         switch (state) {
 593         case PM_SUSPEND_STANDBY:
 594         case PM_SUSPEND_MEM:
 595                 break;
 596         default:
 597                 return -EINVAL;
 598         }
 599
 600         return error;
 601 }
 602
 603 static int omap2_pm_suspend(void)
 604 {
 605         u32 wken_wkup, mir1;
 606
 607         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 608         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 609
 610         /* Mask GPT1 */
 611         mir1 = omap_readl(0x480fe0a4);
 612         omap_writel(1 << 5, 0x480fe0ac);
 613
 614         omap2_enter_full_retention();
 615
 616         omap_writel(mir1, 0x480fe0a4);
 617         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 618
 619         return 0;
 620 }
 621
 622 static int omap2_pm_enter(suspend_state_t state)
 623 {
 624         int ret = 0;
 625
 626         switch (state) {
 627         case PM_SUSPEND_STANDBY:
 628         case PM_SUSPEND_MEM:
 629                 ret = omap2_pm_suspend();
 630                 break;
 631         default:
 632                 ret = -EINVAL;
 633         }
 634
 635         return ret;
 636 }
 637
 638 static int omap2_pm_finish(suspend_state_t state)
 639 {
 640         pm_idle = saved_idle;
 641         return 0;
 642 }
 643
 644 static struct pm_ops omap_pm_ops = {
 645         .prepare        = omap2_pm_prepare,
 646         .enter          = omap2_pm_enter,
 647         .finish         = omap2_pm_finish,
 648         .valid          = pm_valid_only_mem,
 649 };
 650
 651 static void __init prcm_setup_regs(void)
 652 {
 653         u32 l;
 654
 655         /* Enable autoidle */
 656         prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 657
 658         /* Set all domain wakeup dependencies */
 659         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 660         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 661         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 662
 663         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 664         /* Enable retention for all memory blocks */
 665         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 666                 OMAP24XX_MEM1RETSTATE;
 667
 668         /* Set power state to RETENTION */
 669         l &= ~OMAP_POWERSTATE_MASK;
 670         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 671         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 672
 673         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 674                           OMAP_LOGICRETSTATE,
 675                           MPU_MOD, PM_PWSTCTRL);
 676
 677         /* Power down DSP and GFX */
 678         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 679                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 680         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 681                           GFX_MOD, PM_PWSTCTRL);
 682
 683         /* Enable clock auto control for all domains */
 684         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 685         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 686                          OMAP24XX_AUTOSTATE_L3,
 687                          CORE_MOD, CM_CLKSTCTRL);
 688         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 689         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 690                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 691
 692         /* Enable clock autoidle for all domains */
 693         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 694                          OMAP24XX_AUTO_MAILBOXES |
 695                          OMAP24XX_AUTO_WDT4 |
 696                          OMAP2420_AUTO_WDT3 |
 697                          OMAP24XX_AUTO_MSPRO |
 698                          OMAP2420_AUTO_MMC |
 699                          OMAP24XX_AUTO_FAC |
 700                          OMAP2420_AUTO_EAC |
 701                          OMAP24XX_AUTO_HDQ |
 702                          OMAP24XX_AUTO_UART2 |
 703                          OMAP24XX_AUTO_UART1 |
 704                          OMAP24XX_AUTO_I2C2 |
 705                          OMAP24XX_AUTO_I2C1 |
 706                          OMAP24XX_AUTO_MCSPI2 |
 707                          OMAP24XX_AUTO_MCSPI1 |
 708                          OMAP24XX_AUTO_MCBSP2 |
 709                          OMAP24XX_AUTO_MCBSP1 |
 710                          OMAP24XX_AUTO_GPT12 |
 711                          OMAP24XX_AUTO_GPT11 |
 712                          OMAP24XX_AUTO_GPT10 |
 713                          OMAP24XX_AUTO_GPT9 |
 714                          OMAP24XX_AUTO_GPT8 |
 715                          OMAP24XX_AUTO_GPT7 |
 716                          OMAP24XX_AUTO_GPT6 |
 717                          OMAP24XX_AUTO_GPT5 |
 718                          OMAP24XX_AUTO_GPT4 |
 719                          OMAP24XX_AUTO_GPT3 |
 720                          OMAP24XX_AUTO_GPT2 |
 721                          OMAP2420_AUTO_VLYNQ |
 722                          OMAP24XX_AUTO_DSS,
 723                          CORE_MOD, CM_AUTOIDLE1);
 724         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 725                          OMAP24XX_AUTO_SSI |
 726                          OMAP24XX_AUTO_USB,
 727                          CORE_MOD, CM_AUTOIDLE2);
 728         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 729                          OMAP24XX_AUTO_GPMC |
 730                          OMAP24XX_AUTO_SDMA,
 731                          CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
 732         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 733                          OMAP24XX_AUTO_AES |
 734                          OMAP24XX_AUTO_RNG |
 735                          OMAP24XX_AUTO_SHA |
 736                          OMAP24XX_AUTO_DES,
 737                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 738
 739         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 740
 741         /* Put DPLL and both APLLs into autoidle mode */
 742         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 743                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 744                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 745                          PLL_MOD, CM_AUTOIDLE);
 746
 747         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 748                          OMAP24XX_AUTO_WDT1 |
 749                          OMAP24XX_AUTO_MPU_WDT |
 750                          OMAP24XX_AUTO_GPIOS |
 751                          OMAP24XX_AUTO_32KSYNC |
 752                          OMAP24XX_AUTO_GPT1,
 753                          WKUP_MOD, CM_AUTOIDLE);
 754
 755         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 756          * stabilisation */
 757         prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 758
 759         /* Configure automatic voltage transition */
 760         prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 761         prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
 762                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 763                       OMAP24XX_MEMRETCTRL |
 764                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 765                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 766                       OMAP24XX_PRCM_VOLTCTRL);
 767
 768         /* Enable wake-up events */
 769         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 770                           WKUP_MOD, PM_WKEN);
 771 }
 772
 773 int __init omap2_pm_init(void)
 774 {
 775         u32 l;
 776
 777         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 778         l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 779         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 780
 781         osc_ck = clk_get(NULL, "osc_ck");
 782         if (IS_ERR(osc_ck)) {
 783                 printk(KERN_ERR "could not get osc_ck\n");
 784                 return -ENODEV;
 785         }
 786
 787         if (cpu_is_omap242x()) {
 788                 emul_ck = clk_get(NULL, "emul_ck");
 789                 if (IS_ERR(emul_ck)) {
 790                         printk(KERN_ERR "could not get emul_ck\n");
 791                         clk_put(osc_ck);
 792                         return -ENODEV;
 793                 }
 794         }
 795
 796         prcm_setup_regs();
 797
 798         pm_init_serial_console();
 799
 800         /* Hack to prevent MPU retention when STI console is enabled. */
 801         {
 802                 const struct omap_sti_console_config *sti;
 803
 804                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 805                                       struct omap_sti_console_config);
 806                 if (sti != NULL && sti->enable)
 807                         sti_console_enabled = 1;
 808         }
 809
 810         /*
 811          * We copy the assembler sleep/wakeup routines to SRAM.
 812          * These routines need to be in SRAM as that's the only
 813          * memory the MPU can see when it wakes up.
 814          */
 815         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 816                                          omap24xx_idle_loop_suspend_sz);
 817         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 818                                             omap24xx_cpu_suspend_sz);
 819
 820         pm_set_ops(&omap_pm_ops);
 821         pm_idle = omap2_pm_idle;
 822
 823         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 824         if (l)
 825                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 826
 827         return 0;
 828 }
 829
 830 late_initcall(omap2_pm_init);