arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2006 Nokia Corporation
   7  * Tony Lindgren <tony@atomide.com>
   8  *
   9  * Fixed suspend-resume/dynamic-idle to get OMAP to retention
  10  * Amit Kucheria <amit.kucheria@nokia.com>
  11  * Igor Stoppa <igor.stoppa@nokia.com>
  12  *
  13  * Fixed MPU sleep to get ARM idle
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Fixed MPU sleep some more
  17  * Juha Yrjola
  18  *
  19  * Copyright (C) 2005 Texas Instruments, Inc.
  20  * Richard Woodruff <r-woodruff2@ti.com>
  21  *
  22  * Based on pm.c for omap1
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License version 2 as
  26  * published by the Free Software Foundation.
  27  */
  28
  29 #include <linux/pm.h>
  30 #include <linux/sched.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/pm.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/sysfs.h>
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/clk.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #include <asm/atomic.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/irq.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <asm/arch/irqs.h>
  47 #include <asm/arch/clock.h>
  48 #include <asm/arch/sram.h>
  49 #include <asm/arch/pm.h>
  50 #include <asm/arch/mux.h>
  51 #include <asm/arch/dma.h>
  52 #include <asm/arch/board.h>
  53
  54 #define PRCM_REVISION           0x000
  55 #define PRCM_SYSCONFIG          0x010
  56 #define PRCM_IRQSTATUS_MPU      0x018
  57 #define PRCM_IRQENABLE_MPU      0x01c
  58 #define PRCM_VOLTCTRL           0x050
  59 #define         AUTO_EXTVOLT    (1 << 15)
  60 #define         FORCE_EXTVOLT   (1 << 14)
  61 #define         SETOFF_LEVEL(x) (((x) & 0x3) << 12)
  62 #define         MEMRETCTRL      (1 << 8)
  63 #define         SETRET_LEVEL(x) (((x) & 0x3) << 6)
  64 #define         VOLT_LEVEL(x)   (((x) & 0x3) << 0)
  65 #define PRCM_CLKSRC_CTRL        0x060
  66 #define PRCM_CLKOUT_CTRL        0x070
  67 #define PRCM_CLKEMUL_CTRL       0x078
  68 #define PRCM_CLKCFG_CTRL        0x080
  69 #define PRCM_VOLTSETUP          0x090
  70 #define PRCM_CLKSSETUP          0x094
  71
  72
  73 #define CM_CLKSEL_MPU           0x140
  74 #define CM_CLKSTCTRL_MPU        0x148
  75 #define         AUTOSTAT_MPU    (1 << 0)
  76 #define PM_WKDEP_MPU            0x1c8
  77 #define         EN_WKUP         (1 << 4)
  78 #define         EN_GFX          (1 << 3)
  79 #define         EN_DSP          (1 << 2)
  80 #define         EN_MPU          (1 << 1)
  81 #define         EN_CORE         (1 << 0)
  82 #define PM_PWSTCTRL_MPU         0x1e0
  83 #define PM_PWSTST_MPU           0x1e4
  84
  85
  86 #define CM_FCLKEN1_CORE         0x200
  87 #define CM_FCLKEN2_CORE         0x204
  88 #define CM_ICLKEN1_CORE         0x210
  89 #define CM_ICLKEN2_CORE         0x214
  90 #define CM_ICLKEN4_CORE         0x21c
  91 #define CM_IDLEST1_CORE         0x220
  92 #define CM_IDLEST2_CORE         0x224
  93 #define CM_AUTOIDLE1_CORE       0x230
  94 #define CM_AUTOIDLE2_CORE       0x234
  95 #define CM_AUTOIDLE3_CORE       0x238
  96 #define CM_AUTOIDLE4_CORE       0x23c
  97 #define CM_CLKSEL1_CORE         0x240
  98 #define CM_CLKSEL2_CORE         0x244
  99 #define CM_CLKSTCTRL_CORE       0x248
 100 #define         AUTOSTAT_DSS    (1 << 2)
 101 #define         AUTOSTAT_L4     (1 << 1)
 102 #define         AUTOSTAT_L3     (1 << 0)
 103 #define PM_WKEN1_CORE           0x2a0
 104 #define PM_WKEN2_CORE           0x2a4
 105 #define PM_WKST1_CORE           0x2b0
 106 #define PM_WKST2_CORE           0x2b4
 107 #define PM_WKDEP_CORE           0x2c8
 108 #define PM_PWSTCTRL_CORE        0x2e0
 109 #define PM_PWSTST_CORE          0x2e4
 110
 111
 112 #define CM_CLKSTCTRL_GFX        0x348
 113 #define         AUTOSTAT_GFX    (1 << 0)
 114 #define PM_WKDEP_GFX            0x3c8
 115 #define PM_PWSTCTRL_GFX         0x3e0
 116
 117
 118 #define CM_FCLKEN_WKUP          0x400
 119 #define CM_ICLKEN_WKUP          0x410
 120 #define CM_AUTOIDLE_WKUP        0x430
 121 #define PM_WKEN_WKUP            0x4a0
 122 #define         EN_GPIOS        (1 << 2)
 123 #define         EN_GPT1         (1 << 0)
 124 #define PM_WKST_WKUP            0x4b0
 125
 126
 127 #define CM_CLKEN_PLL            0x500
 128 #define CM_IDLEST_CKGEN         0x520
 129 #define CM_AUTOIDLE_PLL         0x530
 130 #define CM_CLKSEL1_PLL          0x540
 131 #define CM_CLKSEL2_PLL          0x544
 132
 133
 134 #define CM_FCLKEN_DSP           0x800
 135 #define CM_ICLKEN_DSP           0x810
 136 #define CM_IDLEST_DSP           0x820
 137 #define CM_AUTOIDLE_DSP         0x830
 138 #define CM_CLKSEL_DSP           0x840
 139 #define CM_CLKSTCTRL_DSP        0x848
 140 #define         AUTOSTAT_IVA    (1 << 8)
 141 #define         AUTOSTAT_DSP    (1 << 0)
 142 #define RM_RSTCTRL_DSP          0x850
 143 #define RM_RSTST_DSP            0x858
 144 #define PM_WKDEP_DSP            0x8c8
 145 #define PM_PWSTCTRL_DSP         0x8e0
 146 #define PM_PWSTST_DSP           0x8e4
 147
 148 static void (*omap2_sram_idle)(void);
 149 static void (*omap2_sram_suspend)(int dllctrl);
 150 static void (*saved_idle)(void);
 151
 152 static u32 prcm_base = IO_ADDRESS(OMAP24XX_PRCM_BASE);
 153
 154 static inline void prcm_write_reg(int idx, u32 val)
 155 {
 156         __raw_writel(val, prcm_base + idx);
 157 }
 158
 159 static inline u32 prcm_read_reg(int idx)
 160 {
 161         return __raw_readl(prcm_base + idx);
 162 }
 163
 164 static u32 omap2_read_32k_sync_counter(void)
 165 {
 166         return omap_readl(0x48004010);
 167 }
 168
 169 #ifdef CONFIG_PM_DEBUG
 170 int omap2_pm_debug = 0;
 171
 172 static int serial_console_clock_disabled;
 173 static int serial_console_uart;
 174 static unsigned int serial_console_next_disable;
 175
 176 static struct clk *console_iclk, *console_fclk;
 177
 178 static void serial_console_kick(void)
 179 {
 180         serial_console_next_disable = omap2_read_32k_sync_counter();
 181         /* Keep the clocks on for 4 secs */
 182         serial_console_next_disable += 4 * 32768;
 183 }
 184
 185 static void serial_wait_tx(void)
 186 {
 187         static const unsigned long uart_bases[3] = {
 188                 0x4806a000, 0x4806c000, 0x4806e000
 189         };
 190         unsigned long lsr_reg;
 191         int looped = 0;
 192
 193         /* Wait for TX FIFO and THR to get empty */
 194         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
 195         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
 196                 looped = 1;
 197         if (looped)
 198                 serial_console_kick();
 199 }
 200
 201 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 202 {
 203         switch (serial_console_uart)  {
 204         case 1:
 205                 *f1 &= ~(1 << 21);
 206                 break;
 207         case 2:
 208                 *f1 &= ~(1 << 22);
 209                 break;
 210         case 3:
 211                 *f2 &= ~(1 << 2);
 212                 break;
 213         }
 214 }
 215
 216 static void serial_console_sleep(int enable)
 217 {
 218         if (console_iclk == NULL || console_fclk == NULL)
 219                 return;
 220
 221         if (enable) {
 222                 BUG_ON(serial_console_clock_disabled);
 223                 if (clk_get_usecount(console_fclk) == 0)
 224                         return;
 225                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 226                         return;
 227                 serial_wait_tx();
 228                 clk_disable(console_iclk);
 229                 clk_disable(console_fclk);
 230                 serial_console_clock_disabled = 1;
 231         } else {
 232                 int serial_wakeup = 0;
 233                 u32 l;
 234
 235                 switch (serial_console_uart)  {
 236                 case 1:
 237                         l = prcm_read_reg(PM_WKST1_CORE);
 238                         if (l & (1 << 21))
 239                                 serial_wakeup = 1;
 240                         break;
 241                 case 2:
 242                         l = prcm_read_reg(PM_WKST1_CORE);
 243                         if (l & (1 << 22))
 244                                 serial_wakeup = 1;
 245                         break;
 246                 case 3:
 247                         l = prcm_read_reg(PM_WKST2_CORE);
 248                         if (l & (1 << 2))
 249                                 serial_wakeup = 1;
 250                         break;
 251                 }
 252                 if (serial_wakeup)
 253                         serial_console_kick();
 254                 if (!serial_console_clock_disabled)
 255                         return;
 256                 clk_enable(console_iclk);
 257                 clk_enable(console_fclk);
 258                 serial_console_clock_disabled = 0;
 259         }
 260 }
 261
 262 static void pm_init_serial_console(void)
 263 {
 264         const struct omap_serial_console_config *conf;
 265         char name[16];
 266         u32 l;
 267
 268         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 269                                struct omap_serial_console_config);
 270         if (conf == NULL)
 271                 return;
 272         if (conf->console_uart > 3 || conf->console_uart < 1)
 273                 return;
 274         serial_console_uart = conf->console_uart;
 275         sprintf(name, "uart%d_fck", conf->console_uart);
 276         console_fclk = clk_get(NULL, name);
 277         if (IS_ERR(console_fclk))
 278                 console_fclk = NULL;
 279         name[6] = 'i';
 280         console_iclk = clk_get(NULL, name);
 281         if (IS_ERR(console_fclk))
 282                 console_iclk = NULL;
 283         if (console_fclk == NULL || console_iclk == NULL) {
 284                 serial_console_uart = 0;
 285                 return;
 286         }
 287         switch (serial_console_uart) {
 288         case 1:
 289                 l = prcm_read_reg(PM_WKEN1_CORE);
 290                 l |= 1 << 21;
 291                 prcm_write_reg(PM_WKEN1_CORE, l);
 292                 break;
 293         case 2:
 294                 l = prcm_read_reg(PM_WKEN1_CORE);
 295                 l |= 1 << 22;
 296                 prcm_write_reg(PM_WKEN1_CORE, l);
 297                 break;
 298         case 3:
 299                 l = prcm_read_reg(PM_WKEN2_CORE);
 300                 l |= 1 << 2;
 301                 prcm_write_reg(PM_WKEN2_CORE, l);
 302                 break;
 303         }
 304 }
 305
 306 #define DUMP_REG(reg) \
 307         regs[reg_count].name = #reg; \
 308         regs[reg_count++].val = prcm_read_reg(reg)
 309 #define DUMP_INTC_REG(reg, off) \
 310         regs[reg_count].name = #reg; \
 311         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 312
 313 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 314 {
 315         struct reg {
 316                 const char *name;
 317                 u32 val;
 318         } regs[32];
 319         int reg_count = 0, i;
 320         const char *s1 = NULL, *s2 = NULL;
 321
 322         if (!resume) {
 323 #if 0
 324                 /* MPU */
 325                 DUMP_REG(PRCM_IRQENABLE_MPU);
 326                 DUMP_REG(CM_CLKSTCTRL_MPU);
 327                 DUMP_REG(PM_PWSTCTRL_MPU);
 328                 DUMP_REG(PM_PWSTST_MPU);
 329                 DUMP_REG(PM_WKDEP_MPU);
 330 #endif
 331 #if 0
 332                 /* INTC */
 333                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 334                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 335                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 336 #endif
 337 #if 0
 338                 DUMP_REG(CM_FCLKEN1_CORE);
 339                 DUMP_REG(CM_FCLKEN2_CORE);
 340                 DUMP_REG(CM_FCLKEN_WKUP);
 341                 DUMP_REG(CM_ICLKEN1_CORE);
 342                 DUMP_REG(CM_ICLKEN2_CORE);
 343                 DUMP_REG(CM_ICLKEN_WKUP);
 344                 DUMP_REG(CM_CLKEN_PLL);
 345                 DUMP_REG(PRCM_CLKEMUL_CTRL);
 346                 DUMP_REG(CM_AUTOIDLE_PLL);
 347                 DUMP_REG(PM_PWSTST_CORE);
 348                 DUMP_REG(PRCM_CLKSRC_CTRL);
 349 #endif
 350 #if 0
 351                 /* DSP */
 352                 DUMP_REG(CM_FCLKEN_DSP);
 353                 DUMP_REG(CM_ICLKEN_DSP);
 354                 DUMP_REG(CM_IDLEST_DSP);
 355                 DUMP_REG(CM_AUTOIDLE_DSP);
 356                 DUMP_REG(CM_CLKSEL_DSP);
 357                 DUMP_REG(CM_CLKSTCTRL_DSP);
 358                 DUMP_REG(RM_RSTCTRL_DSP);
 359                 DUMP_REG(RM_RSTST_DSP);
 360                 DUMP_REG(PM_PWSTCTRL_DSP);
 361                 DUMP_REG(PM_PWSTST_DSP);
 362 #endif
 363         } else {
 364                 DUMP_REG(PM_WKST1_CORE);
 365                 DUMP_REG(PM_WKST2_CORE);
 366                 DUMP_REG(PM_WKST_WKUP);
 367                 DUMP_REG(PRCM_IRQSTATUS_MPU);
 368 #if 1
 369                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 370                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 371                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 372 #endif
 373         }
 374
 375         switch (mode) {
 376         case 0:
 377                 s1 = "full";
 378                 s2 = "retention";
 379                 break;
 380         case 1:
 381                 s1 = "MPU";
 382                 s2 = "retention";
 383                 break;
 384         case 2:
 385                 s1 = "MPU";
 386                 s2 = "idle";
 387                 break;
 388         }
 389
 390         if (!resume)
 391 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 392                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 393                        jiffies_to_msecs(next_timer_interrupt() - jiffies));
 394 #else
 395                 printk("--- Going to %s %s\n", s1, s2);
 396 #endif
 397         else
 398                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 399         for (i = 0; i < reg_count; i++)
 400                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 401 }
 402
 403 #else
 404 static inline void serial_console_sleep(int enable) {}
 405 static inline void pm_init_serial_console(void) {}
 406 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 407 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 408
 409 #define omap2_pm_debug 0
 410
 411 #endif
 412
 413 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 414
 415 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
 416 {
 417         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 418 }
 419
 420 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
 421                                               const char * buf,
 422                                               size_t n)
 423 {
 424         unsigned short value;
 425         if (sscanf(buf, "%hu", &value) != 1 ||
 426             (value != 0 && value != 1)) {
 427                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 428                 return -EINVAL;
 429         }
 430         enable_dyn_sleep = value;
 431         return n;
 432 }
 433
 434 static struct subsys_attribute sleep_while_idle_attr = {
 435         .attr   = {
 436                 .name = __stringify(sleep_while_idle),
 437                 .mode = 0644,
 438         },
 439         .show   = omap_pm_sleep_while_idle_show,
 440         .store  = omap_pm_sleep_while_idle_store,
 441 };
 442
 443 extern struct subsystem power_subsys;
 444
 445 static struct clk *osc_ck, *emul_ck;
 446
 447 #define CONTROL_DEVCONF         __REG32(0x48000274)
 448 #define SDRC_DLLA_CTRL          __REG32(0x68009060)
 449
 450 static int omap2_fclks_active(void)
 451 {
 452         u32 f1, f2;
 453
 454         f1 = prcm_read_reg(CM_FCLKEN1_CORE);
 455         f2 = prcm_read_reg(CM_FCLKEN2_CORE);
 456         serial_console_fclk_mask(&f1, &f2);
 457         if (f1 | f2)
 458                 return 1;
 459         return 0;
 460 }
 461
 462 static int omap2_irq_pending(void)
 463 {
 464         u32 pending_reg = IO_ADDRESS(0x480fe098);
 465         int i;
 466
 467         for (i = 0; i < 4; i++) {
 468                 if (__raw_readl(pending_reg))
 469                         return 1;
 470                 pending_reg += 0x20;
 471         }
 472         return 0;
 473 }
 474
 475 static atomic_t sleep_block = ATOMIC_INIT(0);
 476
 477 void omap2_block_sleep(void)
 478 {
 479         atomic_inc(&sleep_block);
 480 }
 481
 482 void omap2_allow_sleep(void)
 483 {
 484         int i;
 485
 486         i = atomic_dec_return(&sleep_block);
 487         BUG_ON(i < 0);
 488 }
 489
 490 extern void omap2_gpio_prepare_for_retention(void);
 491 extern void omap2_gpio_resume_after_retention(void);
 492
 493 static void omap2_enter_full_retention(void)
 494 {
 495         u32 sleep_time = 0;
 496
 497         /* There is 1 reference hold for all children of the oscillator
 498          * clock, the following will remove it. If no one else uses the
 499          * oscillator itself it will be disabled if/when we enter retention
 500          * mode.
 501          */
 502         clk_disable(osc_ck);
 503
 504         /* Clear old wake-up events */
 505         prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 506         prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 507         prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 508
 509         /* Try to enter retention */
 510         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 511
 512         /* Workaround to kill USB */
 513         CONTROL_DEVCONF |= 0x00008000;
 514
 515         omap2_gpio_prepare_for_retention();
 516
 517         if (omap2_pm_debug) {
 518                 omap2_pm_dump(0, 0, 0);
 519                 sleep_time = omap2_read_32k_sync_counter();
 520         }
 521
 522         /* One last check for pending IRQs to avoid extra latency due
 523          * to sleeping unnecessarily. */
 524         if (omap2_irq_pending())
 525                 goto no_sleep;
 526
 527         serial_console_sleep(1);
 528         /* Jump to SRAM suspend code */
 529         omap2_sram_suspend(SDRC_DLLA_CTRL);
 530 no_sleep:
 531         serial_console_sleep(0);
 532
 533         if (omap2_pm_debug) {
 534                 unsigned long long tmp;
 535                 u32 resume_time;
 536
 537                 resume_time = omap2_read_32k_sync_counter();
 538                 tmp = resume_time - sleep_time;
 539                 tmp *= 1000000;
 540                 omap2_pm_dump(0, 1, tmp / 32768);
 541         }
 542         omap2_gpio_resume_after_retention();
 543
 544         clk_enable(osc_ck);
 545
 546 }
 547
 548 static int omap2_i2c_active(void)
 549 {
 550         u32 l;
 551
 552         l = prcm_read_reg(CM_FCLKEN1_CORE);
 553         return l & ((1 << 19) | (1 << 20));
 554 }
 555
 556 static int sti_console_enabled;
 557
 558 static int omap2_allow_mpu_retention(void)
 559 {
 560         u32 l;
 561
 562         if (atomic_read(&sleep_block))
 563                 return 0;
 564
 565         /* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
 566         l = prcm_read_reg(CM_FCLKEN1_CORE);
 567         if (l & 0x04660001)
 568                 return 0;
 569         /* Check for UART3. */
 570         l = prcm_read_reg(CM_FCLKEN2_CORE);
 571         if (l & (1 << 2))
 572                 return 0;
 573         if (sti_console_enabled)
 574                 return 0;
 575
 576         /* FIXME: Enable soon */
 577         return 0;
 578 }
 579
 580 static void omap2_enter_mpu_retention(void)
 581 {
 582         u32 sleep_time = 0;
 583         int only_idle = 0;
 584
 585         /* Putting MPU into the WFI state while a transfer is active
 586          * seems to cause the I2C block to timeout. Why? Good question. */
 587         if (omap2_i2c_active())
 588                 return;
 589
 590         /* The peripherals seem not to be able to wake up the MPU when
 591          * it is in retention mode. */
 592         if (omap2_allow_mpu_retention()) {
 593                 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 594                 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 595                 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 596
 597                 /* Try to enter MPU retention */
 598                 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 599         } else {
 600                 /* Block MPU retention */
 601                 prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
 602                 only_idle = 1;
 603         }
 604
 605         if (omap2_pm_debug) {
 606                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 607                 sleep_time = omap2_read_32k_sync_counter();
 608         }
 609
 610         omap2_sram_idle();
 611
 612         if (omap2_pm_debug) {
 613                 unsigned long long tmp;
 614                 u32 resume_time;
 615
 616                 resume_time = omap2_read_32k_sync_counter();
 617                 tmp = resume_time - sleep_time;
 618                 tmp *= 1000000;
 619                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 620         }
 621 }
 622
 623 static int omap2_can_sleep(void)
 624 {
 625         if (!enable_dyn_sleep)
 626                 return 0;
 627         if (omap2_fclks_active())
 628                 return 0;
 629         if (atomic_read(&sleep_block) > 0)
 630                 return 0;
 631         if (clk_get_usecount(osc_ck) > 1)
 632                 return 0;
 633         if (omap_dma_running())
 634                 return 0;
 635
 636         return 1;
 637 }
 638
 639 static void omap2_pm_idle(void)
 640 {
 641         local_irq_disable();
 642         local_fiq_disable();
 643
 644         if (!omap2_can_sleep()) {
 645                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 646                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 647                  * transfer to complete), the increased latency is too much.
 648                  *
 649                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 650                  * to indicate this.
 651                  */
 652                 if (atomic_read(&sleep_block) == 0) {
 653                         timer_dyn_reprogram();
 654                         if (omap2_irq_pending())
 655                                 goto out;
 656                 }
 657                 omap2_enter_mpu_retention();
 658                 goto out;
 659         }
 660
 661         /*
 662          * Since an interrupt may set up a timer, we don't want to
 663          * reprogram the hardware timer with interrupts enabled.
 664          * Re-enable interrupts only after returning from idle.
 665          */
 666         timer_dyn_reprogram();
 667
 668         if (omap2_irq_pending())
 669                 goto out;
 670
 671         omap2_enter_full_retention();
 672
 673 out:
 674         local_fiq_enable();
 675         local_irq_enable();
 676 }
 677
 678 static int omap2_pm_prepare(suspend_state_t state)
 679 {
 680         int error = 0;
 681
 682         /* We cannot sleep in idle until we have resumed */
 683         saved_idle = pm_idle;
 684         pm_idle = NULL;
 685
 686         switch (state) {
 687         case PM_SUSPEND_STANDBY:
 688         case PM_SUSPEND_MEM:
 689                 break;
 690         case PM_SUSPEND_DISK:
 691                 return -ENOTSUPP;
 692         default:
 693                 return -EINVAL;
 694         }
 695
 696         return error;
 697 }
 698
 699 static int omap2_pm_suspend(void)
 700 {
 701         u32 wken_wkup, mir1;
 702
 703         wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
 704         prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
 705
 706         /* Mask GPT1 */
 707         mir1 = omap_readl(0x480fe0a4);
 708         omap_writel(1 << 5, 0x480fe0ac);
 709
 710         omap2_enter_full_retention();
 711
 712         omap_writel(mir1, 0x480fe0a4);
 713         prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
 714
 715         return 0;
 716 }
 717
 718 static int omap2_pm_enter(suspend_state_t state)
 719 {
 720         int ret = 0;
 721
 722         switch (state) {
 723         case PM_SUSPEND_STANDBY:
 724         case PM_SUSPEND_MEM:
 725                 ret = omap2_pm_suspend();
 726                 break;
 727         case PM_SUSPEND_DISK:
 728                 ret = -ENOTSUPP;
 729                 break;
 730         default:
 731                 ret = -EINVAL;
 732         }
 733
 734         return ret;
 735 }
 736
 737 static int omap2_pm_finish(suspend_state_t state)
 738 {
 739         pm_idle = saved_idle;
 740         return 0;
 741 }
 742
 743 static struct pm_ops omap_pm_ops = {
 744         .pm_disk_mode   = 0,
 745         .prepare        = omap2_pm_prepare,
 746         .enter          = omap2_pm_enter,
 747         .finish         = omap2_pm_finish,
 748 };
 749
 750 static void __init prcm_setup_regs(void)
 751 {
 752         u32 l;
 753
 754         /* Enable autoidle */
 755         prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
 756
 757         /* Set all domain wakeup dependencies */
 758         prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
 759         prcm_write_reg(PM_WKDEP_DSP, 0);
 760         prcm_write_reg(PM_WKDEP_GFX, 0);
 761
 762         l = prcm_read_reg(PM_PWSTCTRL_CORE);
 763         /* Enable retention for all memory blocks */
 764         l |= (1 << 3) | (1 << 4) | (1 << 5);
 765         /* Set power state to RETENTION */
 766         l &= ~0x03;
 767         l |= 0x01 << 0;
 768         prcm_write_reg(PM_PWSTCTRL_CORE, l);
 769
 770         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 771
 772         /* Power down DSP and GFX */
 773         prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
 774         prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
 775
 776         /* Enable clock auto control for all domains */
 777         prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
 778         prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
 779         prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
 780         prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
 781
 782         /* Enable clock autoidle for all domains */
 783         prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
 784         prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
 785         prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
 786         prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
 787
 788         prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
 789
 790         /* Put DPLL and both APLLs into autoidle mode */
 791         prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
 792
 793         prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
 794
 795         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 796          * stabilisation */
 797         prcm_write_reg(PRCM_CLKSSETUP, 15);
 798
 799         /* Configure automatic voltage transition */
 800         prcm_write_reg(PRCM_VOLTSETUP, 2);
 801         l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
 802                 SETRET_LEVEL(1) | VOLT_LEVEL(0);
 803         prcm_write_reg(PRCM_VOLTCTRL, l);
 804
 805         /* Enable wake-up events */
 806         prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
 807 }
 808
 809 int __init omap2_pm_init(void)
 810 {
 811         u32 l;
 812
 813         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 814         l = prcm_read_reg(PRCM_REVISION);
 815         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 816
 817         osc_ck = clk_get(NULL, "osc_ck");
 818         if (IS_ERR(osc_ck)) {
 819                 printk(KERN_ERR "could not get osc_ck\n");
 820                 return -ENODEV;
 821         }
 822
 823         emul_ck = clk_get(NULL, "emul_ck");
 824         if (IS_ERR(emul_ck)) {
 825                 printk(KERN_ERR "could not get emul_ck\n");
 826                 clk_put(osc_ck);
 827                 return -ENODEV;
 828         }
 829
 830         prcm_setup_regs();
 831
 832         pm_init_serial_console();
 833
 834         /* Hack to prevent MPU retention when STI console is enabled. */
 835         {
 836                 const struct omap_sti_console_config *sti;
 837
 838                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 839                                       struct omap_sti_console_config);
 840                 if (sti != NULL && sti->enable)
 841                         sti_console_enabled = 1;
 842         }
 843
 844         /*
 845          * We copy the assembler sleep/wakeup routines to SRAM.
 846          * These routines need to be in SRAM as that's the only
 847          * memory the MPU can see when it wakes up.
 848          */
 849         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 850                                          omap24xx_idle_loop_suspend_sz);
 851         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 852                                             omap24xx_cpu_suspend_sz);
 853
 854         pm_set_ops(&omap_pm_ops);
 855         pm_idle = omap2_pm_idle;
 856
 857         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 858         if (l)
 859                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 860
 861         return 0;
 862 }
 863
 864 late_initcall(omap2_pm_init);