arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006-2008 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/control.h>
  43 #include <asm/arch/gpio.h>
  44 #include <asm/arch/pm.h>
  45 #include <asm/arch/mux.h>
  46 #include <asm/arch/dma.h>
  47 #include <asm/arch/board.h>
  48
  49 #include "prm.h"
  50 #include "prm-regbits-24xx.h"
  51 #include "cm.h"
  52 #include "cm-regbits-24xx.h"
  53 #include "sdrc.h"
  54
  55 /* These addrs are in assembly language code to be patched at runtime */
  56 extern void *omap2_ocs_sdrc_power;
  57 extern void *omap2_ocs_sdrc_dlla_ctrl;
  58
  59 static void (*omap2_sram_idle)(void);
  60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  61 static void (*saved_idle)(void);
  62
  63 static u32 omap2_read_32k_sync_counter(void)
  64 {
  65         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  66 }
  67
  68 #ifdef CONFIG_PM_DEBUG
  69 int omap2_pm_debug = 0;
  70
  71 static int serial_console_clock_disabled;
  72 static int serial_console_uart;
  73 static unsigned int serial_console_next_disable;
  74
  75 static struct clk *console_iclk, *console_fclk;
  76
  77 static void serial_console_kick(void)
  78 {
  79         serial_console_next_disable = omap2_read_32k_sync_counter();
  80         /* Keep the clocks on for 4 secs */
  81         serial_console_next_disable += 4 * 32768;
  82 }
  83
  84 static void serial_wait_tx(void)
  85 {
  86         static const unsigned long uart_bases[3] = {
  87                 0x4806a000, 0x4806c000, 0x4806e000
  88         };
  89         unsigned long lsr_reg;
  90         int looped = 0;
  91
  92         /* Wait for TX FIFO and THR to get empty */
  93         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  94         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  95                 looped = 1;
  96         if (looped)
  97                 serial_console_kick();
  98 }
  99
 100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 101 {
 102         switch (serial_console_uart)  {
 103         case 1:
 104                 *f1 &= ~(1 << 21);
 105                 break;
 106         case 2:
 107                 *f1 &= ~(1 << 22);
 108                 break;
 109         case 3:
 110                 *f2 &= ~(1 << 2);
 111                 break;
 112         }
 113 }
 114
 115 static void serial_console_sleep(int enable)
 116 {
 117         if (console_iclk == NULL || console_fclk == NULL)
 118                 return;
 119
 120         if (enable) {
 121                 BUG_ON(serial_console_clock_disabled);
 122                 if (clk_get_usecount(console_fclk) == 0)
 123                         return;
 124                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 125                         return;
 126                 serial_wait_tx();
 127                 clk_disable(console_iclk);
 128                 clk_disable(console_fclk);
 129                 serial_console_clock_disabled = 1;
 130         } else {
 131                 int serial_wakeup = 0;
 132                 u32 l;
 133
 134                 switch (serial_console_uart)  {
 135                 case 1:
 136                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 137                         if (l & OMAP24XX_ST_UART1)
 138                                 serial_wakeup = 1;
 139                         break;
 140                 case 2:
 141                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 142                         if (l & OMAP24XX_ST_UART2)
 143                                 serial_wakeup = 1;
 144                         break;
 145                 case 3:
 146                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 147                         if (l & OMAP24XX_ST_UART3)
 148                                 serial_wakeup = 1;
 149                         break;
 150                 }
 151                 if (serial_wakeup)
 152                         serial_console_kick();
 153                 if (!serial_console_clock_disabled)
 154                         return;
 155                 clk_enable(console_iclk);
 156                 clk_enable(console_fclk);
 157                 serial_console_clock_disabled = 0;
 158         }
 159 }
 160
 161 static void pm_init_serial_console(void)
 162 {
 163         const struct omap_serial_console_config *conf;
 164         char name[16];
 165
 166         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 167                                struct omap_serial_console_config);
 168         if (conf == NULL)
 169                 return;
 170         if (conf->console_uart > 3 || conf->console_uart < 1)
 171                 return;
 172         serial_console_uart = conf->console_uart;
 173         sprintf(name, "uart%d_fck", conf->console_uart);
 174         console_fclk = clk_get(NULL, name);
 175         if (IS_ERR(console_fclk))
 176                 console_fclk = NULL;
 177         name[6] = 'i';
 178         console_iclk = clk_get(NULL, name);
 179         if (IS_ERR(console_fclk))
 180                 console_iclk = NULL;
 181         if (console_fclk == NULL || console_iclk == NULL) {
 182                 serial_console_uart = 0;
 183                 return;
 184         }
 185         switch (serial_console_uart) {
 186         case 1:
 187                 prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
 188                 break;
 189         case 2:
 190                 prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
 191                 break;
 192         case 3:
 193                 prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
 194                 break;
 195         }
 196 }
 197
 198 #define DUMP_PRM_MOD_REG(mod, reg)    \
 199         regs[reg_count].name = #mod "." #reg; \
 200         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 201 #define DUMP_CM_MOD_REG(mod, reg)     \
 202         regs[reg_count].name = #mod "." #reg; \
 203         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 204 #define DUMP_PRM_REG(reg) \
 205         regs[reg_count].name = #reg; \
 206         regs[reg_count++].val = __raw_readl(reg)
 207 #define DUMP_CM_REG(reg) \
 208         regs[reg_count].name = #reg; \
 209         regs[reg_count++].val = __raw_readl(reg)
 210 #define DUMP_INTC_REG(reg, off) \
 211         regs[reg_count].name = #reg; \
 212         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 213
 214 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 215 {
 216         struct reg {
 217                 const char *name;
 218                 u32 val;
 219         } regs[32];
 220         int reg_count = 0, i;
 221         const char *s1 = NULL, *s2 = NULL;
 222
 223         if (!resume) {
 224 #if 0
 225                 /* MPU */
 226                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 227                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 228                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 229                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 230                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 231 #endif
 232 #if 0
 233                 /* INTC */
 234                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 235                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 236                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 237 #endif
 238 #if 0
 239                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 240                 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 241                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 242                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 243                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 244                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 245                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
 246                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 247                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 248                 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
 249                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 250 #endif
 251 #if 0
 252                 /* DSP */
 253                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 254                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 255                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 256                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 257                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 258                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 259                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 260                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 261                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 262                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 263 #endif
 264         } else {
 265                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 266                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 267                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 268                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 269 #if 1
 270                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 271                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 272                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 273 #endif
 274         }
 275
 276         switch (mode) {
 277         case 0:
 278                 s1 = "full";
 279                 s2 = "retention";
 280                 break;
 281         case 1:
 282                 s1 = "MPU";
 283                 s2 = "retention";
 284                 break;
 285         case 2:
 286                 s1 = "MPU";
 287                 s2 = "idle";
 288                 break;
 289         }
 290
 291         if (!resume)
 292 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 293                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 294                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 295                                         jiffies));
 296 #else
 297                 printk("--- Going to %s %s\n", s1, s2);
 298 #endif
 299         else
 300                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 301         for (i = 0; i < reg_count; i++)
 302                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 303 }
 304
 305 #else
 306 static inline void serial_console_sleep(int enable) {}
 307 static inline void pm_init_serial_console(void) {}
 308 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 309 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 310
 311 #define omap2_pm_debug 0
 312
 313 #endif
 314
 315 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 316
 317 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 318                          char *buf)
 319 {
 320         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 321 }
 322
 323 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 324                           const char * buf, size_t n)
 325 {
 326         unsigned short value;
 327         if (sscanf(buf, "%hu", &value) != 1 ||
 328             (value != 0 && value != 1)) {
 329                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 330                 return -EINVAL;
 331         }
 332         enable_dyn_sleep = value;
 333         return n;
 334 }
 335
 336 static struct kobj_attribute sleep_while_idle_attr =
 337         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 338
 339 static struct clk *osc_ck, *emul_ck;
 340
 341 static int omap2_fclks_active(void)
 342 {
 343         u32 f1, f2;
 344
 345         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 346         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 347         serial_console_fclk_mask(&f1, &f2);
 348         if (f1 | f2)
 349                 return 1;
 350         return 0;
 351 }
 352
 353 static int omap2_irq_pending(void)
 354 {
 355         u32 pending_reg = IO_ADDRESS(0x480fe098);
 356         int i;
 357
 358         for (i = 0; i < 4; i++) {
 359                 if (__raw_readl(pending_reg))
 360                         return 1;
 361                 pending_reg += 0x20;
 362         }
 363         return 0;
 364 }
 365
 366 static atomic_t sleep_block = ATOMIC_INIT(0);
 367
 368 void omap2_block_sleep(void)
 369 {
 370         atomic_inc(&sleep_block);
 371 }
 372
 373 void omap2_allow_sleep(void)
 374 {
 375         int i;
 376
 377         i = atomic_dec_return(&sleep_block);
 378         BUG_ON(i < 0);
 379 }
 380
 381 static void omap2_enter_full_retention(void)
 382 {
 383         u32 l, sleep_time = 0;
 384
 385         /* There is 1 reference hold for all children of the oscillator
 386          * clock, the following will remove it. If no one else uses the
 387          * oscillator itself it will be disabled if/when we enter retention
 388          * mode.
 389          */
 390         clk_disable(osc_ck);
 391
 392         /* Clear old wake-up events */
 393         /* REVISIT: These write to reserved bits? */
 394         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 395         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 396         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 397
 398         /* Try to enter retention */
 399         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 400                           MPU_MOD, PM_PWSTCTRL);
 401
 402         /* Workaround to kill USB */
 403         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 404         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 405
 406         omap2_gpio_prepare_for_retention();
 407
 408         if (omap2_pm_debug) {
 409                 omap2_pm_dump(0, 0, 0);
 410                 sleep_time = omap2_read_32k_sync_counter();
 411         }
 412
 413         /* One last check for pending IRQs to avoid extra latency due
 414          * to sleeping unnecessarily. */
 415         if (omap2_irq_pending())
 416                 goto no_sleep;
 417
 418         serial_console_sleep(1);
 419         /* Jump to SRAM suspend code */
 420         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 421 no_sleep:
 422         serial_console_sleep(0);
 423
 424         if (omap2_pm_debug) {
 425                 unsigned long long tmp;
 426                 u32 resume_time;
 427
 428                 resume_time = omap2_read_32k_sync_counter();
 429                 tmp = resume_time - sleep_time;
 430                 tmp *= 1000000;
 431                 omap2_pm_dump(0, 1, tmp / 32768);
 432         }
 433         omap2_gpio_resume_after_retention();
 434
 435         clk_enable(osc_ck);
 436
 437         /* clear CORE wake-up events */
 438         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 439         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 440
 441         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 442         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 443
 444         /* MPU domain wake events */
 445         l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
 446         if (l & 0x01)
 447                 __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 448         if (l & 0x20)
 449                 __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 450
 451         /* Mask future PRCM-to-MPU interrupts */
 452         __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 453 }
 454
 455 static int omap2_i2c_active(void)
 456 {
 457         u32 l;
 458
 459         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 460         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 461 }
 462
 463 static int sti_console_enabled;
 464
 465 static int omap2_allow_mpu_retention(void)
 466 {
 467         u32 l;
 468
 469         if (atomic_read(&sleep_block))
 470                 return 0;
 471
 472         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 473         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 474         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 475                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 476                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 477                 return 0;
 478         /* Check for UART3. */
 479         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 480         if (l & OMAP24XX_EN_UART3)
 481                 return 0;
 482         if (sti_console_enabled)
 483                 return 0;
 484
 485         return 1;
 486 }
 487
 488 static void omap2_enter_mpu_retention(void)
 489 {
 490         u32 sleep_time = 0;
 491         int only_idle = 0;
 492
 493         /* Putting MPU into the WFI state while a transfer is active
 494          * seems to cause the I2C block to timeout. Why? Good question. */
 495         if (omap2_i2c_active())
 496                 return;
 497
 498         /* The peripherals seem not to be able to wake up the MPU when
 499          * it is in retention mode. */
 500         if (omap2_allow_mpu_retention()) {
 501                 /* REVISIT: These write to reserved bits? */
 502                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 503                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 504                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 505
 506                 /* Try to enter MPU retention */
 507                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 508                                   OMAP_LOGICRETSTATE,
 509                                   MPU_MOD, PM_PWSTCTRL);
 510         } else {
 511                 /* Block MPU retention */
 512
 513                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 514                 only_idle = 1;
 515         }
 516
 517         if (omap2_pm_debug) {
 518                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 519                 sleep_time = omap2_read_32k_sync_counter();
 520         }
 521
 522         omap2_sram_idle();
 523
 524         if (omap2_pm_debug) {
 525                 unsigned long long tmp;
 526                 u32 resume_time;
 527
 528                 resume_time = omap2_read_32k_sync_counter();
 529                 tmp = resume_time - sleep_time;
 530                 tmp *= 1000000;
 531                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 532         }
 533 }
 534
 535 static int omap2_can_sleep(void)
 536 {
 537         if (!enable_dyn_sleep)
 538                 return 0;
 539         if (omap2_fclks_active())
 540                 return 0;
 541         if (atomic_read(&sleep_block) > 0)
 542                 return 0;
 543         if (clk_get_usecount(osc_ck) > 1)
 544                 return 0;
 545         if (omap_dma_running())
 546                 return 0;
 547
 548         return 1;
 549 }
 550
 551 static void omap2_pm_idle(void)
 552 {
 553         local_irq_disable();
 554         local_fiq_disable();
 555
 556         if (!omap2_can_sleep()) {
 557                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 558                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 559                  * transfer to complete), the increased latency is too much.
 560                  *
 561                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 562                  * to indicate this.
 563                  */
 564                 if (atomic_read(&sleep_block) == 0) {
 565                         timer_dyn_reprogram();
 566                         if (omap2_irq_pending())
 567                                 goto out;
 568                 }
 569                 omap2_enter_mpu_retention();
 570                 goto out;
 571         }
 572
 573         /*
 574          * Since an interrupt may set up a timer, we don't want to
 575          * reprogram the hardware timer with interrupts enabled.
 576          * Re-enable interrupts only after returning from idle.
 577          */
 578         timer_dyn_reprogram();
 579
 580         if (omap2_irq_pending())
 581                 goto out;
 582
 583         omap2_enter_full_retention();
 584
 585 out:
 586         local_fiq_enable();
 587         local_irq_enable();
 588 }
 589
 590 static int omap2_pm_prepare(void)
 591 {
 592         /* We cannot sleep in idle until we have resumed */
 593         saved_idle = pm_idle;
 594         pm_idle = NULL;
 595
 596         return 0;
 597 }
 598
 599 static int omap2_pm_suspend(void)
 600 {
 601         u32 wken_wkup, mir1;
 602
 603         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 604         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 605
 606         /* Mask GPT1 */
 607         mir1 = omap_readl(0x480fe0a4);
 608         omap_writel(1 << 5, 0x480fe0ac);
 609
 610         omap2_enter_full_retention();
 611
 612         omap_writel(mir1, 0x480fe0a4);
 613         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 614
 615         return 0;
 616 }
 617
 618 static int omap2_pm_enter(suspend_state_t state)
 619 {
 620         int ret = 0;
 621
 622         switch (state) {
 623         case PM_SUSPEND_STANDBY:
 624         case PM_SUSPEND_MEM:
 625                 ret = omap2_pm_suspend();
 626                 break;
 627         default:
 628                 ret = -EINVAL;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static void omap2_pm_finish(void)
 635 {
 636         pm_idle = saved_idle;
 637 }
 638
 639 static struct platform_suspend_ops omap_pm_ops = {
 640         .prepare        = omap2_pm_prepare,
 641         .enter          = omap2_pm_enter,
 642         .finish         = omap2_pm_finish,
 643         .valid          = suspend_valid_only_mem,
 644 };
 645
 646 static void __init prcm_setup_regs(void)
 647 {
 648         u32 l;
 649
 650         /* Enable autoidle */
 651         __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 652
 653         /* Set all domain wakeup dependencies */
 654         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 655         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 656         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 657         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 658         if (cpu_is_omap2430())
 659                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 660
 661         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 662         /* Enable retention for all memory blocks */
 663         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 664                 OMAP24XX_MEM1RETSTATE;
 665
 666         /* Set power state to RETENTION */
 667         l &= ~OMAP_POWERSTATE_MASK;
 668         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 669         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 670
 671         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 672                           OMAP_LOGICRETSTATE,
 673                           MPU_MOD, PM_PWSTCTRL);
 674
 675         /* Power down DSP and GFX */
 676         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 677                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 678         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 679                           GFX_MOD, PM_PWSTCTRL);
 680
 681         /* Enable clock auto control for all domains */
 682         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 683         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 684                          OMAP24XX_AUTOSTATE_L3,
 685                          CORE_MOD, CM_CLKSTCTRL);
 686         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 687         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 688                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 689
 690         /* Enable clock autoidle for all domains */
 691         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 692                          OMAP24XX_AUTO_MAILBOXES |
 693                          OMAP24XX_AUTO_WDT4 |
 694                          OMAP2420_AUTO_WDT3 |
 695                          OMAP24XX_AUTO_MSPRO |
 696                          OMAP2420_AUTO_MMC |
 697                          OMAP24XX_AUTO_FAC |
 698                          OMAP2420_AUTO_EAC |
 699                          OMAP24XX_AUTO_HDQ |
 700                          OMAP24XX_AUTO_UART2 |
 701                          OMAP24XX_AUTO_UART1 |
 702                          OMAP24XX_AUTO_I2C2 |
 703                          OMAP24XX_AUTO_I2C1 |
 704                          OMAP24XX_AUTO_MCSPI2 |
 705                          OMAP24XX_AUTO_MCSPI1 |
 706                          OMAP24XX_AUTO_MCBSP2 |
 707                          OMAP24XX_AUTO_MCBSP1 |
 708                          OMAP24XX_AUTO_GPT12 |
 709                          OMAP24XX_AUTO_GPT11 |
 710                          OMAP24XX_AUTO_GPT10 |
 711                          OMAP24XX_AUTO_GPT9 |
 712                          OMAP24XX_AUTO_GPT8 |
 713                          OMAP24XX_AUTO_GPT7 |
 714                          OMAP24XX_AUTO_GPT6 |
 715                          OMAP24XX_AUTO_GPT5 |
 716                          OMAP24XX_AUTO_GPT4 |
 717                          OMAP24XX_AUTO_GPT3 |
 718                          OMAP24XX_AUTO_GPT2 |
 719                          OMAP2420_AUTO_VLYNQ |
 720                          OMAP24XX_AUTO_DSS,
 721                          CORE_MOD, CM_AUTOIDLE1);
 722         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 723                          OMAP24XX_AUTO_SSI |
 724                          OMAP24XX_AUTO_USB,
 725                          CORE_MOD, CM_AUTOIDLE2);
 726         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 727                          OMAP24XX_AUTO_GPMC |
 728                          OMAP24XX_AUTO_SDMA,
 729                          CORE_MOD, CM_AUTOIDLE3);
 730         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 731                          OMAP24XX_AUTO_AES |
 732                          OMAP24XX_AUTO_RNG |
 733                          OMAP24XX_AUTO_SHA |
 734                          OMAP24XX_AUTO_DES,
 735                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 736
 737         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 738
 739         /* Put DPLL and both APLLs into autoidle mode */
 740         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 741                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 742                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 743                          PLL_MOD, CM_AUTOIDLE);
 744
 745         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 746                          OMAP24XX_AUTO_WDT1 |
 747                          OMAP24XX_AUTO_MPU_WDT |
 748                          OMAP24XX_AUTO_GPIOS |
 749                          OMAP24XX_AUTO_32KSYNC |
 750                          OMAP24XX_AUTO_GPT1,
 751                          WKUP_MOD, CM_AUTOIDLE);
 752
 753         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 754          * stabilisation */
 755         __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 756
 757         /* Configure automatic voltage transition */
 758         __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 759         __raw_writel(OMAP24XX_AUTO_EXTVOLT |
 760                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 761                       OMAP24XX_MEMRETCTRL |
 762                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 763                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 764                       OMAP24XX_PRCM_VOLTCTRL);
 765
 766         /* Enable wake-up events */
 767         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 768                           WKUP_MOD, PM_WKEN);
 769 }
 770
 771 int __init omap2_pm_init(void)
 772 {
 773         u32 l;
 774         int error;
 775
 776         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 777         l = __raw_readl(OMAP24XX_PRCM_REVISION);
 778         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 779
 780         osc_ck = clk_get(NULL, "osc_ck");
 781         if (IS_ERR(osc_ck)) {
 782                 printk(KERN_ERR "could not get osc_ck\n");
 783                 return -ENODEV;
 784         }
 785
 786         if (cpu_is_omap242x()) {
 787                 emul_ck = clk_get(NULL, "emul_ck");
 788                 if (IS_ERR(emul_ck)) {
 789                         printk(KERN_ERR "could not get emul_ck\n");
 790                         clk_put(osc_ck);
 791                         return -ENODEV;
 792                 }
 793         }
 794
 795         prcm_setup_regs();
 796
 797         pm_init_serial_console();
 798
 799         /* Hack to prevent MPU retention when STI console is enabled. */
 800         {
 801                 const struct omap_sti_console_config *sti;
 802
 803                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 804                                       struct omap_sti_console_config);
 805                 if (sti != NULL && sti->enable)
 806                         sti_console_enabled = 1;
 807         }
 808
 809         /*
 810          * We copy the assembler sleep/wakeup routines to SRAM.
 811          * These routines need to be in SRAM as that's the only
 812          * memory the MPU can see when it wakes up.
 813          */
 814         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 815                                          omap24xx_idle_loop_suspend_sz);
 816
 817         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 818                                             omap24xx_cpu_suspend_sz);
 819
 820         /* Patch in the correct register addresses for multiboot */
 821         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 822                            omap2_sram_suspend,
 823                            OMAP_SDRC_REGADDR(SDRC_POWER));
 824         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 825                            omap2_sram_suspend,
 826                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 827
 828         suspend_set_ops(&omap_pm_ops);
 829         pm_idle = omap2_pm_idle;
 830
 831         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 832         if (error)
 833                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 834
 835         return 0;
 836 }
 837
 838 late_initcall(omap2_pm_init);