arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/suspend.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/control.h>
  43 #include <asm/arch/gpio.h>
  44 #include <asm/arch/pm.h>
  45 #include <asm/arch/mux.h>
  46 #include <asm/arch/dma.h>
  47 #include <asm/arch/board.h>
  48
  49 #include "prm.h"
  50 #include "prm_regbits_24xx.h"
  51 #include "cm.h"
  52 #include "cm_regbits_24xx.h"
  53 #include "sdrc.h"
  54
  55 /* These addrs are in assembly language code to be patched at runtime */
  56 extern void *omap2_ocs_sdrc_power;
  57 extern void *omap2_ocs_sdrc_dlla_ctrl;
  58
  59 static void (*omap2_sram_idle)(void);
  60 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  61 static void (*saved_idle)(void);
  62
  63 static u32 omap2_read_32k_sync_counter(void)
  64 {
  65         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  66 }
  67
  68 #ifdef CONFIG_PM_DEBUG
  69 int omap2_pm_debug = 0;
  70
  71 static int serial_console_clock_disabled;
  72 static int serial_console_uart;
  73 static unsigned int serial_console_next_disable;
  74
  75 static struct clk *console_iclk, *console_fclk;
  76
  77 static void serial_console_kick(void)
  78 {
  79         serial_console_next_disable = omap2_read_32k_sync_counter();
  80         /* Keep the clocks on for 4 secs */
  81         serial_console_next_disable += 4 * 32768;
  82 }
  83
  84 static void serial_wait_tx(void)
  85 {
  86         static const unsigned long uart_bases[3] = {
  87                 0x4806a000, 0x4806c000, 0x4806e000
  88         };
  89         unsigned long lsr_reg;
  90         int looped = 0;
  91
  92         /* Wait for TX FIFO and THR to get empty */
  93         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  94         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  95                 looped = 1;
  96         if (looped)
  97                 serial_console_kick();
  98 }
  99
 100 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 101 {
 102         switch (serial_console_uart)  {
 103         case 1:
 104                 *f1 &= ~(1 << 21);
 105                 break;
 106         case 2:
 107                 *f1 &= ~(1 << 22);
 108                 break;
 109         case 3:
 110                 *f2 &= ~(1 << 2);
 111                 break;
 112         }
 113 }
 114
 115 static void serial_console_sleep(int enable)
 116 {
 117         if (console_iclk == NULL || console_fclk == NULL)
 118                 return;
 119
 120         if (enable) {
 121                 BUG_ON(serial_console_clock_disabled);
 122                 if (clk_get_usecount(console_fclk) == 0)
 123                         return;
 124                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 125                         return;
 126                 serial_wait_tx();
 127                 clk_disable(console_iclk);
 128                 clk_disable(console_fclk);
 129                 serial_console_clock_disabled = 1;
 130         } else {
 131                 int serial_wakeup = 0;
 132                 u32 l;
 133
 134                 switch (serial_console_uart)  {
 135                 case 1:
 136                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 137                         if (l & OMAP24XX_ST_UART1)
 138                                 serial_wakeup = 1;
 139                         break;
 140                 case 2:
 141                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 142                         if (l & OMAP24XX_ST_UART2)
 143                                 serial_wakeup = 1;
 144                         break;
 145                 case 3:
 146                         l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
 147                         if (l & OMAP24XX_ST_UART3)
 148                                 serial_wakeup = 1;
 149                         break;
 150                 }
 151                 if (serial_wakeup)
 152                         serial_console_kick();
 153                 if (!serial_console_clock_disabled)
 154                         return;
 155                 clk_enable(console_iclk);
 156                 clk_enable(console_fclk);
 157                 serial_console_clock_disabled = 0;
 158         }
 159 }
 160
 161 static void pm_init_serial_console(void)
 162 {
 163         const struct omap_serial_console_config *conf;
 164         char name[16];
 165         u32 l;
 166
 167         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 168                                struct omap_serial_console_config);
 169         if (conf == NULL)
 170                 return;
 171         if (conf->console_uart > 3 || conf->console_uart < 1)
 172                 return;
 173         serial_console_uart = conf->console_uart;
 174         sprintf(name, "uart%d_fck", conf->console_uart);
 175         console_fclk = clk_get(NULL, name);
 176         if (IS_ERR(console_fclk))
 177                 console_fclk = NULL;
 178         name[6] = 'i';
 179         console_iclk = clk_get(NULL, name);
 180         if (IS_ERR(console_fclk))
 181                 console_iclk = NULL;
 182         if (console_fclk == NULL || console_iclk == NULL) {
 183                 serial_console_uart = 0;
 184                 return;
 185         }
 186         switch (serial_console_uart) {
 187         case 1:
 188                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 189                 l |= OMAP24XX_ST_UART1;
 190                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 191                 break;
 192         case 2:
 193                 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
 194                 l |= OMAP24XX_ST_UART2;
 195                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 196                 break;
 197         case 3:
 198                 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
 199                 l |= OMAP24XX_ST_UART3;
 200                 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
 201                 break;
 202         }
 203 }
 204
 205 #define DUMP_PRM_MOD_REG(mod, reg)    \
 206         regs[reg_count].name = #mod "." #reg; \
 207         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 208 #define DUMP_CM_MOD_REG(mod, reg)     \
 209         regs[reg_count].name = #mod "." #reg; \
 210         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 211 #define DUMP_PRM_REG(reg) \
 212         regs[reg_count].name = #reg; \
 213         regs[reg_count++].val = prm_read_reg(reg)
 214 #define DUMP_CM_REG(reg) \
 215         regs[reg_count].name = #reg; \
 216         regs[reg_count++].val = cm_read_reg(reg)
 217 #define DUMP_INTC_REG(reg, off) \
 218         regs[reg_count].name = #reg; \
 219         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 220
 221 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 222 {
 223         struct reg {
 224                 const char *name;
 225                 u32 val;
 226         } regs[32];
 227         int reg_count = 0, i;
 228         const char *s1 = NULL, *s2 = NULL;
 229
 230         if (!resume) {
 231 #if 0
 232                 /* MPU */
 233                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 234                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 235                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 236                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 237                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 238 #endif
 239 #if 0
 240                 /* INTC */
 241                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 242                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 243                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 244 #endif
 245 #if 0
 246                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 247                 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 248                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 249                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 250                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 251                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 252                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
 253                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 254                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 255                 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
 256                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 257 #endif
 258 #if 0
 259                 /* DSP */
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 261                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 262                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 263                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 264                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 265                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 266                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 267                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 268                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 269                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 270 #endif
 271         } else {
 272                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 273                 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
 274                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 275                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 276 #if 1
 277                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 278                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 279                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 280 #endif
 281         }
 282
 283         switch (mode) {
 284         case 0:
 285                 s1 = "full";
 286                 s2 = "retention";
 287                 break;
 288         case 1:
 289                 s1 = "MPU";
 290                 s2 = "retention";
 291                 break;
 292         case 2:
 293                 s1 = "MPU";
 294                 s2 = "idle";
 295                 break;
 296         }
 297
 298         if (!resume)
 299 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 300                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 301                        jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
 302                                         jiffies));
 303 #else
 304                 printk("--- Going to %s %s\n", s1, s2);
 305 #endif
 306         else
 307                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 308         for (i = 0; i < reg_count; i++)
 309                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 310 }
 311
 312 #else
 313 static inline void serial_console_sleep(int enable) {}
 314 static inline void pm_init_serial_console(void) {}
 315 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 316 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 317
 318 #define omap2_pm_debug 0
 319
 320 #endif
 321
 322 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 323
 324 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 325                          char *buf)
 326 {
 327         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 328 }
 329
 330 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 331                           const char * buf, size_t n)
 332 {
 333         unsigned short value;
 334         if (sscanf(buf, "%hu", &value) != 1 ||
 335             (value != 0 && value != 1)) {
 336                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 337                 return -EINVAL;
 338         }
 339         enable_dyn_sleep = value;
 340         return n;
 341 }
 342
 343 static struct kobj_attribute sleep_while_idle_attr =
 344         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
 345
 346 static struct clk *osc_ck, *emul_ck;
 347
 348 static int omap2_fclks_active(void)
 349 {
 350         u32 f1, f2;
 351
 352         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 353         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 354         serial_console_fclk_mask(&f1, &f2);
 355         if (f1 | f2)
 356                 return 1;
 357         return 0;
 358 }
 359
 360 static int omap2_irq_pending(void)
 361 {
 362         u32 pending_reg = IO_ADDRESS(0x480fe098);
 363         int i;
 364
 365         for (i = 0; i < 4; i++) {
 366                 if (__raw_readl(pending_reg))
 367                         return 1;
 368                 pending_reg += 0x20;
 369         }
 370         return 0;
 371 }
 372
 373 static atomic_t sleep_block = ATOMIC_INIT(0);
 374
 375 void omap2_block_sleep(void)
 376 {
 377         atomic_inc(&sleep_block);
 378 }
 379
 380 void omap2_allow_sleep(void)
 381 {
 382         int i;
 383
 384         i = atomic_dec_return(&sleep_block);
 385         BUG_ON(i < 0);
 386 }
 387
 388 static void omap2_enter_full_retention(void)
 389 {
 390         u32 l, sleep_time = 0;
 391
 392         /* There is 1 reference hold for all children of the oscillator
 393          * clock, the following will remove it. If no one else uses the
 394          * oscillator itself it will be disabled if/when we enter retention
 395          * mode.
 396          */
 397         clk_disable(osc_ck);
 398
 399         /* Clear old wake-up events */
 400         /* REVISIT: These write to reserved bits? */
 401         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 402         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 403         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 404
 405         /* Try to enter retention */
 406         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 407                           MPU_MOD, PM_PWSTCTRL);
 408
 409         /* Workaround to kill USB */
 410         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 411         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 412
 413         omap2_gpio_prepare_for_retention();
 414
 415         if (omap2_pm_debug) {
 416                 omap2_pm_dump(0, 0, 0);
 417                 sleep_time = omap2_read_32k_sync_counter();
 418         }
 419
 420         /* One last check for pending IRQs to avoid extra latency due
 421          * to sleeping unnecessarily. */
 422         if (omap2_irq_pending())
 423                 goto no_sleep;
 424
 425         serial_console_sleep(1);
 426         /* Jump to SRAM suspend code */
 427         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 428 no_sleep:
 429         serial_console_sleep(0);
 430
 431         if (omap2_pm_debug) {
 432                 unsigned long long tmp;
 433                 u32 resume_time;
 434
 435                 resume_time = omap2_read_32k_sync_counter();
 436                 tmp = resume_time - sleep_time;
 437                 tmp *= 1000000;
 438                 omap2_pm_dump(0, 1, tmp / 32768);
 439         }
 440         omap2_gpio_resume_after_retention();
 441
 442         clk_enable(osc_ck);
 443
 444         /* clear CORE wake-up events */
 445         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 446         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 447
 448         /* wakeup domain events */
 449         l = prm_read_mod_reg(WKUP_MOD, PM_WKST);
 450         l &= 0x5;  /* bit 1: GPT1, bit5 GPIO */
 451         prm_write_mod_reg(l, WKUP_MOD, PM_WKST);
 452
 453         /* MPU domain wake events */
 454         l = prm_read_reg(OMAP24XX_PRCM_IRQSTATUS_MPU);
 455         if (l & 0x01)
 456                 prm_write_reg(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
 457         if (l & 0x20)
 458                 prm_write_reg(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
 459
 460         /* Mask future PRCM-to-MPU interrupts */
 461         prm_write_reg(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
 462 }
 463
 464 static int omap2_i2c_active(void)
 465 {
 466         u32 l;
 467
 468         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 469         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 470 }
 471
 472 static int sti_console_enabled;
 473
 474 static int omap2_allow_mpu_retention(void)
 475 {
 476         u32 l;
 477
 478         if (atomic_read(&sleep_block))
 479                 return 0;
 480
 481         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 482         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 483         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 484                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 485                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 486                 return 0;
 487         /* Check for UART3. */
 488         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 489         if (l & OMAP24XX_EN_UART3)
 490                 return 0;
 491         if (sti_console_enabled)
 492                 return 0;
 493
 494         return 1;
 495 }
 496
 497 static void omap2_enter_mpu_retention(void)
 498 {
 499         u32 sleep_time = 0;
 500         int only_idle = 0;
 501
 502         /* Putting MPU into the WFI state while a transfer is active
 503          * seems to cause the I2C block to timeout. Why? Good question. */
 504         if (omap2_i2c_active())
 505                 return;
 506
 507         /* The peripherals seem not to be able to wake up the MPU when
 508          * it is in retention mode. */
 509         if (omap2_allow_mpu_retention()) {
 510                 /* REVISIT: These write to reserved bits? */
 511                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 512                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 513                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 514
 515                 /* Try to enter MPU retention */
 516                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 517                                   OMAP_LOGICRETSTATE,
 518                                   MPU_MOD, PM_PWSTCTRL);
 519         } else {
 520                 /* Block MPU retention */
 521
 522                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 523                 only_idle = 1;
 524         }
 525
 526         if (omap2_pm_debug) {
 527                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 528                 sleep_time = omap2_read_32k_sync_counter();
 529         }
 530
 531         omap2_sram_idle();
 532
 533         if (omap2_pm_debug) {
 534                 unsigned long long tmp;
 535                 u32 resume_time;
 536
 537                 resume_time = omap2_read_32k_sync_counter();
 538                 tmp = resume_time - sleep_time;
 539                 tmp *= 1000000;
 540                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 541         }
 542 }
 543
 544 static int omap2_can_sleep(void)
 545 {
 546         if (!enable_dyn_sleep)
 547                 return 0;
 548         if (omap2_fclks_active())
 549                 return 0;
 550         if (atomic_read(&sleep_block) > 0)
 551                 return 0;
 552         if (clk_get_usecount(osc_ck) > 1)
 553                 return 0;
 554         if (omap_dma_running())
 555                 return 0;
 556
 557         return 1;
 558 }
 559
 560 static void omap2_pm_idle(void)
 561 {
 562         local_irq_disable();
 563         local_fiq_disable();
 564
 565         if (!omap2_can_sleep()) {
 566                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 567                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 568                  * transfer to complete), the increased latency is too much.
 569                  *
 570                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 571                  * to indicate this.
 572                  */
 573                 if (atomic_read(&sleep_block) == 0) {
 574                         timer_dyn_reprogram();
 575                         if (omap2_irq_pending())
 576                                 goto out;
 577                 }
 578                 omap2_enter_mpu_retention();
 579                 goto out;
 580         }
 581
 582         /*
 583          * Since an interrupt may set up a timer, we don't want to
 584          * reprogram the hardware timer with interrupts enabled.
 585          * Re-enable interrupts only after returning from idle.
 586          */
 587         timer_dyn_reprogram();
 588
 589         if (omap2_irq_pending())
 590                 goto out;
 591
 592         omap2_enter_full_retention();
 593
 594 out:
 595         local_fiq_enable();
 596         local_irq_enable();
 597 }
 598
 599 static int omap2_pm_prepare(void)
 600 {
 601         /* We cannot sleep in idle until we have resumed */
 602         saved_idle = pm_idle;
 603         pm_idle = NULL;
 604
 605         return 0;
 606 }
 607
 608 static int omap2_pm_suspend(void)
 609 {
 610         u32 wken_wkup, mir1;
 611
 612         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 613         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 614
 615         /* Mask GPT1 */
 616         mir1 = omap_readl(0x480fe0a4);
 617         omap_writel(1 << 5, 0x480fe0ac);
 618
 619         omap2_enter_full_retention();
 620
 621         omap_writel(mir1, 0x480fe0a4);
 622         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 623
 624         return 0;
 625 }
 626
 627 static int omap2_pm_enter(suspend_state_t state)
 628 {
 629         int ret = 0;
 630
 631         switch (state) {
 632         case PM_SUSPEND_STANDBY:
 633         case PM_SUSPEND_MEM:
 634                 ret = omap2_pm_suspend();
 635                 break;
 636         default:
 637                 ret = -EINVAL;
 638         }
 639
 640         return ret;
 641 }
 642
 643 static void omap2_pm_finish(void)
 644 {
 645         pm_idle = saved_idle;
 646 }
 647
 648 static struct platform_suspend_ops omap_pm_ops = {
 649         .prepare        = omap2_pm_prepare,
 650         .enter          = omap2_pm_enter,
 651         .finish         = omap2_pm_finish,
 652         .valid          = suspend_valid_only_mem,
 653 };
 654
 655 static void __init prcm_setup_regs(void)
 656 {
 657         u32 l;
 658
 659         /* Enable autoidle */
 660         prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 661
 662         /* Set all domain wakeup dependencies */
 663         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 664         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 665         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 666         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 667         if (cpu_is_omap2430())
 668                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 669
 670         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 671         /* Enable retention for all memory blocks */
 672         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 673                 OMAP24XX_MEM1RETSTATE;
 674
 675         /* Set power state to RETENTION */
 676         l &= ~OMAP_POWERSTATE_MASK;
 677         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 678         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 679
 680         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 681                           OMAP_LOGICRETSTATE,
 682                           MPU_MOD, PM_PWSTCTRL);
 683
 684         /* Power down DSP and GFX */
 685         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 686                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 687         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 688                           GFX_MOD, PM_PWSTCTRL);
 689
 690         /* Enable clock auto control for all domains */
 691         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 692         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 693                          OMAP24XX_AUTOSTATE_L3,
 694                          CORE_MOD, CM_CLKSTCTRL);
 695         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 696         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 697                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 698
 699         /* Enable clock autoidle for all domains */
 700         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 701                          OMAP24XX_AUTO_MAILBOXES |
 702                          OMAP24XX_AUTO_WDT4 |
 703                          OMAP2420_AUTO_WDT3 |
 704                          OMAP24XX_AUTO_MSPRO |
 705                          OMAP2420_AUTO_MMC |
 706                          OMAP24XX_AUTO_FAC |
 707                          OMAP2420_AUTO_EAC |
 708                          OMAP24XX_AUTO_HDQ |
 709                          OMAP24XX_AUTO_UART2 |
 710                          OMAP24XX_AUTO_UART1 |
 711                          OMAP24XX_AUTO_I2C2 |
 712                          OMAP24XX_AUTO_I2C1 |
 713                          OMAP24XX_AUTO_MCSPI2 |
 714                          OMAP24XX_AUTO_MCSPI1 |
 715                          OMAP24XX_AUTO_MCBSP2 |
 716                          OMAP24XX_AUTO_MCBSP1 |
 717                          OMAP24XX_AUTO_GPT12 |
 718                          OMAP24XX_AUTO_GPT11 |
 719                          OMAP24XX_AUTO_GPT10 |
 720                          OMAP24XX_AUTO_GPT9 |
 721                          OMAP24XX_AUTO_GPT8 |
 722                          OMAP24XX_AUTO_GPT7 |
 723                          OMAP24XX_AUTO_GPT6 |
 724                          OMAP24XX_AUTO_GPT5 |
 725                          OMAP24XX_AUTO_GPT4 |
 726                          OMAP24XX_AUTO_GPT3 |
 727                          OMAP24XX_AUTO_GPT2 |
 728                          OMAP2420_AUTO_VLYNQ |
 729                          OMAP24XX_AUTO_DSS,
 730                          CORE_MOD, CM_AUTOIDLE1);
 731         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 732                          OMAP24XX_AUTO_SSI |
 733                          OMAP24XX_AUTO_USB,
 734                          CORE_MOD, CM_AUTOIDLE2);
 735         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 736                          OMAP24XX_AUTO_GPMC |
 737                          OMAP24XX_AUTO_SDMA,
 738                          CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
 739         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 740                          OMAP24XX_AUTO_AES |
 741                          OMAP24XX_AUTO_RNG |
 742                          OMAP24XX_AUTO_SHA |
 743                          OMAP24XX_AUTO_DES,
 744                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 745
 746         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 747
 748         /* Put DPLL and both APLLs into autoidle mode */
 749         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 750                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 751                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 752                          PLL_MOD, CM_AUTOIDLE);
 753
 754         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 755                          OMAP24XX_AUTO_WDT1 |
 756                          OMAP24XX_AUTO_MPU_WDT |
 757                          OMAP24XX_AUTO_GPIOS |
 758                          OMAP24XX_AUTO_32KSYNC |
 759                          OMAP24XX_AUTO_GPT1,
 760                          WKUP_MOD, CM_AUTOIDLE);
 761
 762         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 763          * stabilisation */
 764         prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 765
 766         /* Configure automatic voltage transition */
 767         prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 768         prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
 769                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 770                       OMAP24XX_MEMRETCTRL |
 771                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 772                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 773                       OMAP24XX_PRCM_VOLTCTRL);
 774
 775         /* Enable wake-up events */
 776         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 777                           WKUP_MOD, PM_WKEN);
 778 }
 779
 780 int __init omap2_pm_init(void)
 781 {
 782         u32 l;
 783         int error;
 784
 785         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 786         l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 787         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 788
 789         osc_ck = clk_get(NULL, "osc_ck");
 790         if (IS_ERR(osc_ck)) {
 791                 printk(KERN_ERR "could not get osc_ck\n");
 792                 return -ENODEV;
 793         }
 794
 795         if (cpu_is_omap242x()) {
 796                 emul_ck = clk_get(NULL, "emul_ck");
 797                 if (IS_ERR(emul_ck)) {
 798                         printk(KERN_ERR "could not get emul_ck\n");
 799                         clk_put(osc_ck);
 800                         return -ENODEV;
 801                 }
 802         }
 803
 804         prcm_setup_regs();
 805
 806         pm_init_serial_console();
 807
 808         /* Hack to prevent MPU retention when STI console is enabled. */
 809         {
 810                 const struct omap_sti_console_config *sti;
 811
 812                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 813                                       struct omap_sti_console_config);
 814                 if (sti != NULL && sti->enable)
 815                         sti_console_enabled = 1;
 816         }
 817
 818         /*
 819          * We copy the assembler sleep/wakeup routines to SRAM.
 820          * These routines need to be in SRAM as that's the only
 821          * memory the MPU can see when it wakes up.
 822          */
 823         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 824                                          omap24xx_idle_loop_suspend_sz);
 825
 826         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 827                                             omap24xx_cpu_suspend_sz);
 828
 829         /* Patch in the correct register addresses for multiboot */
 830         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
 831                            omap2_sram_suspend,
 832                            OMAP_SDRC_REGADDR(SDRC_POWER));
 833         omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
 834                            omap2_sram_suspend,
 835                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 836
 837         suspend_set_ops(&omap_pm_ops);
 838         pm_idle = omap2_pm_idle;
 839
 840         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr);
 841         if (error)
 842                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 843
 844         return 0;
 845 }
 846
 847 late_initcall(omap2_pm_init);