arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2006 Nokia Corporation
   7  * Tony Lindgren <tony@atomide.com>
   8  *
   9  * Fixed suspend-resume/dynamic-idle to get OMAP to retention
  10  * Amit Kucheria <amit.kucheria@nokia.com>
  11  * Igor Stoppa <igor.stoppa@nokia.com>
  12  *
  13  * Fixed MPU sleep to get ARM idle
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Fixed MPU sleep some more
  17  * Juha Yrjola
  18  *
  19  * Copyright (C) 2005 Texas Instruments, Inc.
  20  * Richard Woodruff <r-woodruff2@ti.com>
  21  *
  22  * Based on pm.c for omap1
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License version 2 as
  26  * published by the Free Software Foundation.
  27  */
  28
  29 #include <linux/pm.h>
  30 #include <linux/sched.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/pm.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/sysfs.h>
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/clk.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #include <asm/atomic.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/irq.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <asm/arch/irqs.h>
  47 #include <asm/arch/clock.h>
  48 #include <asm/arch/sram.h>
  49 #include <asm/arch/pm.h>
  50 #include <asm/arch/mux.h>
  51 #include <asm/arch/dma.h>
  52 #include <asm/arch/board.h>
  53
  54 #define PRCM_BASE               0x48008000
  55 #define PRCM_REVISION           0x000
  56 #define PRCM_SYSCONFIG          0x010
  57 #define PRCM_IRQSTATUS_MPU      0x018
  58 #define PRCM_IRQENABLE_MPU      0x01c
  59 #define PRCM_VOLTCTRL           0x050
  60 #define         AUTO_EXTVOLT    (1 << 15)
  61 #define         FORCE_EXTVOLT   (1 << 14)
  62 #define         SETOFF_LEVEL(x) (((x) & 0x3) << 12)
  63 #define         MEMRETCTRL      (1 << 8)
  64 #define         SETRET_LEVEL(x) (((x) & 0x3) << 6)
  65 #define         VOLT_LEVEL(x)   (((x) & 0x3) << 0)
  66 #define PRCM_CLKSRC_CTRL        0x060
  67 #define PRCM_CLKOUT_CTRL        0x070
  68 #define PRCM_CLKEMUL_CTRL       0x078
  69 #define PRCM_CLKCFG_CTRL        0x080
  70 #define PRCM_VOLTSETUP          0x090
  71 #define PRCM_CLKSSETUP          0x094
  72
  73
  74 #define CM_CLKSEL_MPU           0x140
  75 #define CM_CLKSTCTRL_MPU        0x148
  76 #define         AUTOSTAT_MPU    (1 << 0)
  77 #define PM_WKDEP_MPU            0x1c8
  78 #define         EN_WKUP         (1 << 4)
  79 #define         EN_GFX          (1 << 3)
  80 #define         EN_DSP          (1 << 2)
  81 #define         EN_MPU          (1 << 1)
  82 #define         EN_CORE         (1 << 0)
  83 #define PM_PWSTCTRL_MPU         0x1e0
  84 #define PM_PWSTST_MPU           0x1e4
  85
  86
  87 #define CM_FCLKEN1_CORE         0x200
  88 #define CM_FCLKEN2_CORE         0x204
  89 #define CM_ICLKEN1_CORE         0x210
  90 #define CM_ICLKEN2_CORE         0x214
  91 #define CM_ICLKEN4_CORE         0x21c
  92 #define CM_IDLEST1_CORE         0x220
  93 #define CM_IDLEST2_CORE         0x224
  94 #define CM_AUTOIDLE1_CORE       0x230
  95 #define CM_AUTOIDLE2_CORE       0x234
  96 #define CM_AUTOIDLE3_CORE       0x238
  97 #define CM_AUTOIDLE4_CORE       0x23c
  98 #define CM_CLKSEL1_CORE         0x240
  99 #define CM_CLKSEL2_CORE         0x244
 100 #define CM_CLKSTCTRL_CORE       0x248
 101 #define         AUTOSTAT_DSS    (1 << 2)
 102 #define         AUTOSTAT_L4     (1 << 1)
 103 #define         AUTOSTAT_L3     (1 << 0)
 104 #define PM_WKEN1_CORE           0x2a0
 105 #define PM_WKEN2_CORE           0x2a4
 106 #define PM_WKST1_CORE           0x2b0
 107 #define PM_WKST2_CORE           0x2b4
 108 #define PM_WKDEP_CORE           0x2c8
 109 #define PM_PWSTCTRL_CORE        0x2e0
 110 #define PM_PWSTST_CORE          0x2e4
 111
 112
 113 #define CM_CLKSTCTRL_GFX        0x348
 114 #define         AUTOSTAT_GFX    (1 << 0)
 115 #define PM_WKDEP_GFX            0x3c8
 116 #define PM_PWSTCTRL_GFX         0x3e0
 117
 118
 119 #define CM_FCLKEN_WKUP          0x400
 120 #define CM_ICLKEN_WKUP          0x410
 121 #define CM_AUTOIDLE_WKUP        0x430
 122 #define PM_WKEN_WKUP            0x4a0
 123 #define         EN_GPIOS        (1 << 2)
 124 #define         EN_GPT1         (1 << 0)
 125 #define PM_WKST_WKUP            0x4b0
 126
 127
 128 #define CM_CLKEN_PLL            0x500
 129 #define CM_IDLEST_CKGEN         0x520
 130 #define CM_AUTOIDLE_PLL         0x530
 131 #define CM_CLKSEL1_PLL          0x540
 132 #define CM_CLKSEL2_PLL          0x544
 133
 134
 135 #define CM_FCLKEN_DSP           0x800
 136 #define CM_ICLKEN_DSP           0x810
 137 #define CM_IDLEST_DSP           0x820
 138 #define CM_AUTOIDLE_DSP         0x830
 139 #define CM_CLKSEL_DSP           0x840
 140 #define CM_CLKSTCTRL_DSP        0x848
 141 #define         AUTOSTAT_IVA    (1 << 8)
 142 #define         AUTOSTAT_DSP    (1 << 0)
 143 #define RM_RSTCTRL_DSP          0x850
 144 #define RM_RSTST_DSP            0x858
 145 #define PM_WKDEP_DSP            0x8c8
 146 #define PM_PWSTCTRL_DSP         0x8e0
 147 #define PM_PWSTST_DSP           0x8e4
 148
 149 static void (*omap2_sram_idle)(void);
 150 static void (*omap2_sram_suspend)(int dllctrl);
 151 static void (*saved_idle)(void);
 152
 153 static u32 prcm_base = IO_ADDRESS(PRCM_BASE);
 154
 155 static inline void prcm_write_reg(int idx, u32 val)
 156 {
 157         __raw_writel(val, prcm_base + idx);
 158 }
 159
 160 static inline u32 prcm_read_reg(int idx)
 161 {
 162         return __raw_readl(prcm_base + idx);
 163 }
 164
 165 static u32 omap2_read_32k_sync_counter(void)
 166 {
 167         return omap_readl(0x48004010);
 168 }
 169
 170 #ifdef CONFIG_PM_DEBUG
 171 int omap2_pm_debug = 0;
 172
 173 static int serial_console_clock_disabled;
 174 static int serial_console_uart;
 175 static unsigned int serial_console_next_disable;
 176
 177 static struct clk *console_iclk, *console_fclk;
 178
 179 static void serial_console_kick(void)
 180 {
 181         serial_console_next_disable = omap2_read_32k_sync_counter();
 182         /* Keep the clocks on for 4 secs */
 183         serial_console_next_disable += 4 * 32768;
 184 }
 185
 186 static void serial_wait_tx(void)
 187 {
 188         static const unsigned long uart_bases[3] = {
 189                 0x4806a000, 0x4806c000, 0x4806e000
 190         };
 191         unsigned long lsr_reg;
 192         int looped = 0;
 193
 194         /* Wait for TX FIFO and THR to get empty */
 195         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
 196         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
 197                 looped = 1;
 198         if (looped)
 199                 serial_console_kick();
 200 }
 201
 202 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
 203 {
 204         switch (serial_console_uart)  {
 205         case 1:
 206                 *f1 &= ~(1 << 21);
 207                 break;
 208         case 2:
 209                 *f1 &= ~(1 << 22);
 210                 break;
 211         case 3:
 212                 *f2 &= ~(1 << 2);
 213                 break;
 214         }
 215 }
 216
 217 static void serial_console_sleep(int enable)
 218 {
 219         if (console_iclk == NULL || console_fclk == NULL)
 220                 return;
 221
 222         if (enable) {
 223                 BUG_ON(serial_console_clock_disabled);
 224                 if (clk_get_usecount(console_fclk) == 0)
 225                         return;
 226                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 227                         return;
 228                 serial_wait_tx();
 229                 clk_disable(console_iclk);
 230                 clk_disable(console_fclk);
 231                 serial_console_clock_disabled = 1;
 232         } else {
 233                 int serial_wakeup = 0;
 234                 u32 l;
 235
 236                 switch (serial_console_uart)  {
 237                 case 1:
 238                         l = prcm_read_reg(PM_WKST1_CORE);
 239                         if (l & (1 << 21))
 240                                 serial_wakeup = 1;
 241                         break;
 242                 case 2:
 243                         l = prcm_read_reg(PM_WKST1_CORE);
 244                         if (l & (1 << 22))
 245                                 serial_wakeup = 1;
 246                         break;
 247                 case 3:
 248                         l = prcm_read_reg(PM_WKST2_CORE);
 249                         if (l & (1 << 2))
 250                                 serial_wakeup = 1;
 251                         break;
 252                 }
 253                 if (serial_wakeup)
 254                         serial_console_kick();
 255                 if (!serial_console_clock_disabled)
 256                         return;
 257                 clk_enable(console_iclk);
 258                 clk_enable(console_fclk);
 259                 serial_console_clock_disabled = 0;
 260         }
 261 }
 262
 263 static void pm_init_serial_console(void)
 264 {
 265         const struct omap_serial_console_config *conf;
 266         char name[16];
 267         u32 l;
 268
 269         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 270                                struct omap_serial_console_config);
 271         if (conf == NULL)
 272                 return;
 273         if (conf->console_uart > 3 || conf->console_uart < 1)
 274                 return;
 275         serial_console_uart = conf->console_uart;
 276         sprintf(name, "uart%d_fck", conf->console_uart);
 277         console_fclk = clk_get(NULL, name);
 278         if (IS_ERR(console_fclk))
 279                 console_fclk = NULL;
 280         name[6] = 'i';
 281         console_iclk = clk_get(NULL, name);
 282         if (IS_ERR(console_fclk))
 283                 console_iclk = NULL;
 284         if (console_fclk == NULL || console_iclk == NULL) {
 285                 serial_console_uart = 0;
 286                 return;
 287         }
 288         switch (serial_console_uart) {
 289         case 1:
 290                 l = prcm_read_reg(PM_WKEN1_CORE);
 291                 l |= 1 << 21;
 292                 prcm_write_reg(PM_WKEN1_CORE, l);
 293                 break;
 294         case 2:
 295                 l = prcm_read_reg(PM_WKEN1_CORE);
 296                 l |= 1 << 22;
 297                 prcm_write_reg(PM_WKEN1_CORE, l);
 298                 break;
 299         case 3:
 300                 l = prcm_read_reg(PM_WKEN2_CORE);
 301                 l |= 1 << 2;
 302                 prcm_write_reg(PM_WKEN2_CORE, l);
 303                 break;
 304         }
 305 }
 306
 307 #define DUMP_REG(reg) \
 308         regs[reg_count].name = #reg; \
 309         regs[reg_count++].val = prcm_read_reg(reg)
 310 #define DUMP_INTC_REG(reg, off) \
 311         regs[reg_count].name = #reg; \
 312         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 313
 314 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 315 {
 316         struct reg {
 317                 const char *name;
 318                 u32 val;
 319         } regs[32];
 320         int reg_count = 0, i;
 321         const char *s1 = NULL, *s2 = NULL;
 322
 323         if (!resume) {
 324 #if 0
 325                 /* MPU */
 326                 DUMP_REG(PRCM_IRQENABLE_MPU);
 327                 DUMP_REG(CM_CLKSTCTRL_MPU);
 328                 DUMP_REG(PM_PWSTCTRL_MPU);
 329                 DUMP_REG(PM_PWSTST_MPU);
 330                 DUMP_REG(PM_WKDEP_MPU);
 331 #endif
 332 #if 0
 333                 /* INTC */
 334                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 335                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 336                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 337 #endif
 338 #if 0
 339                 DUMP_REG(CM_FCLKEN1_CORE);
 340                 DUMP_REG(CM_FCLKEN2_CORE);
 341                 DUMP_REG(CM_FCLKEN_WKUP);
 342                 DUMP_REG(CM_ICLKEN1_CORE);
 343                 DUMP_REG(CM_ICLKEN2_CORE);
 344                 DUMP_REG(CM_ICLKEN_WKUP);
 345                 DUMP_REG(CM_CLKEN_PLL);
 346                 DUMP_REG(PRCM_CLKEMUL_CTRL);
 347                 DUMP_REG(CM_AUTOIDLE_PLL);
 348                 DUMP_REG(PM_PWSTST_CORE);
 349                 DUMP_REG(PRCM_CLKSRC_CTRL);
 350 #endif
 351 #if 0
 352                 /* DSP */
 353                 DUMP_REG(CM_FCLKEN_DSP);
 354                 DUMP_REG(CM_ICLKEN_DSP);
 355                 DUMP_REG(CM_IDLEST_DSP);
 356                 DUMP_REG(CM_AUTOIDLE_DSP);
 357                 DUMP_REG(CM_CLKSEL_DSP);
 358                 DUMP_REG(CM_CLKSTCTRL_DSP);
 359                 DUMP_REG(RM_RSTCTRL_DSP);
 360                 DUMP_REG(RM_RSTST_DSP);
 361                 DUMP_REG(PM_PWSTCTRL_DSP);
 362                 DUMP_REG(PM_PWSTST_DSP);
 363 #endif
 364         } else {
 365                 DUMP_REG(PM_WKST1_CORE);
 366                 DUMP_REG(PM_WKST2_CORE);
 367                 DUMP_REG(PM_WKST_WKUP);
 368                 DUMP_REG(PRCM_IRQSTATUS_MPU);
 369 #if 1
 370                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 371                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 372                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 373 #endif
 374         }
 375
 376         switch (mode) {
 377         case 0:
 378                 s1 = "full";
 379                 s2 = "retention";
 380                 break;
 381         case 1:
 382                 s1 = "MPU";
 383                 s2 = "retention";
 384                 break;
 385         case 2:
 386                 s1 = "MPU";
 387                 s2 = "idle";
 388                 break;
 389         }
 390
 391         if (!resume)
 392 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 393                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 394                        jiffies_to_msecs(next_timer_interrupt() - jiffies));
 395 #else
 396                 printk("--- Going to %s %s\n", s1, s2);
 397 #endif
 398         else
 399                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 400         for (i = 0; i < reg_count; i++)
 401                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 402 }
 403
 404 #else
 405 static inline void serial_console_sleep(int enable) {}
 406 static inline void pm_init_serial_console(void) {}
 407 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 408 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 409
 410 #define omap2_pm_debug 0
 411
 412 #endif
 413
 414 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 415
 416 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
 417 {
 418         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 419 }
 420
 421 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
 422                                               const char * buf,
 423                                               size_t n)
 424 {
 425         unsigned short value;
 426         if (sscanf(buf, "%hu", &value) != 1 ||
 427             (value != 0 && value != 1)) {
 428                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 429                 return -EINVAL;
 430         }
 431         enable_dyn_sleep = value;
 432         return n;
 433 }
 434
 435 static struct subsys_attribute sleep_while_idle_attr = {
 436         .attr   = {
 437                 .name = __stringify(sleep_while_idle),
 438                 .mode = 0644,
 439         },
 440         .show   = omap_pm_sleep_while_idle_show,
 441         .store  = omap_pm_sleep_while_idle_store,
 442 };
 443
 444 extern struct subsystem power_subsys;
 445
 446 static struct clk *osc_ck, *emul_ck;
 447
 448 #define CONTROL_DEVCONF         __REG32(0x48000274)
 449 #define SDRC_DLLA_CTRL          __REG32(0x68009060)
 450
 451 static int omap2_fclks_active(void)
 452 {
 453         u32 f1, f2;
 454
 455         f1 = prcm_read_reg(CM_FCLKEN1_CORE);
 456         f2 = prcm_read_reg(CM_FCLKEN2_CORE);
 457         serial_console_fclk_mask(&f1, &f2);
 458         if (f1 | f2)
 459                 return 1;
 460         return 0;
 461 }
 462
 463 static int omap2_irq_pending(void)
 464 {
 465         u32 pending_reg = IO_ADDRESS(0x480fe098);
 466         int i;
 467
 468         for (i = 0; i < 4; i++) {
 469                 if (__raw_readl(pending_reg))
 470                         return 1;
 471                 pending_reg += 0x20;
 472         }
 473         return 0;
 474 }
 475
 476 static atomic_t sleep_block = ATOMIC_INIT(0);
 477
 478 void omap2_block_sleep(void)
 479 {
 480         atomic_inc(&sleep_block);
 481 }
 482
 483 void omap2_allow_sleep(void)
 484 {
 485         int i;
 486
 487         i = atomic_dec_return(&sleep_block);
 488         BUG_ON(i < 0);
 489 }
 490
 491 extern void omap2_gpio_prepare_for_retention(void);
 492 extern void omap2_gpio_resume_after_retention(void);
 493
 494 static void omap2_enter_full_retention(void)
 495 {
 496         u32 sleep_time = 0;
 497
 498         /* There is 1 reference hold for all children of the oscillator
 499          * clock, the following will remove it. If no one else uses the
 500          * oscillator itself it will be disabled if/when we enter retention
 501          * mode.
 502          */
 503         clk_disable(osc_ck);
 504
 505         /* Clear old wake-up events */
 506         prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 507         prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 508         prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 509
 510         /* Try to enter retention */
 511         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 512
 513         /* Workaround to kill USB */
 514         CONTROL_DEVCONF |= 0x00008000;
 515
 516         omap2_gpio_prepare_for_retention();
 517
 518         if (omap2_pm_debug) {
 519                 omap2_pm_dump(0, 0, 0);
 520                 sleep_time = omap2_read_32k_sync_counter();
 521         }
 522
 523         /* One last check for pending IRQs to avoid extra latency due
 524          * to sleeping unnecessarily. */
 525         if (omap2_irq_pending())
 526                 goto no_sleep;
 527
 528         serial_console_sleep(1);
 529         /* Jump to SRAM suspend code */
 530         omap2_sram_suspend(SDRC_DLLA_CTRL);
 531 no_sleep:
 532         serial_console_sleep(0);
 533
 534         if (omap2_pm_debug) {
 535                 unsigned long long tmp;
 536                 u32 resume_time;
 537
 538                 resume_time = omap2_read_32k_sync_counter();
 539                 tmp = resume_time - sleep_time;
 540                 tmp *= 1000000;
 541                 omap2_pm_dump(0, 1, tmp / 32768);
 542         }
 543         omap2_gpio_resume_after_retention();
 544
 545         clk_enable(osc_ck);
 546
 547 }
 548
 549 static int omap2_i2c_active(void)
 550 {
 551         u32 l;
 552
 553         l = prcm_read_reg(CM_FCLKEN1_CORE);
 554         return l & ((1 << 19) | (1 << 20));
 555 }
 556
 557 static int sti_console_enabled;
 558
 559 static int omap2_allow_mpu_retention(void)
 560 {
 561         u32 l;
 562
 563         if (atomic_read(&sleep_block))
 564                 return 0;
 565
 566         /* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
 567         l = prcm_read_reg(CM_FCLKEN1_CORE);
 568         if (l & 0x04660001)
 569                 return 0;
 570         /* Check for UART3. */
 571         l = prcm_read_reg(CM_FCLKEN2_CORE);
 572         if (l & (1 << 2))
 573                 return 0;
 574         if (sti_console_enabled)
 575                 return 0;
 576
 577         /* FIXME: Enable soon */
 578         return 0;
 579 }
 580
 581 static void omap2_enter_mpu_retention(void)
 582 {
 583         u32 sleep_time = 0;
 584         int only_idle = 0;
 585
 586         /* Putting MPU into the WFI state while a transfer is active
 587          * seems to cause the I2C block to timeout. Why? Good question. */
 588         if (omap2_i2c_active())
 589                 return;
 590
 591         /* The peripherals seem not to be able to wake up the MPU when
 592          * it is in retention mode. */
 593         if (omap2_allow_mpu_retention()) {
 594                 prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
 595                 prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
 596                 prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
 597
 598                 /* Try to enter MPU retention */
 599                 prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 600         } else {
 601                 /* Block MPU retention */
 602                 prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
 603                 only_idle = 1;
 604         }
 605
 606         if (omap2_pm_debug) {
 607                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 608                 sleep_time = omap2_read_32k_sync_counter();
 609         }
 610
 611         omap2_sram_idle();
 612
 613         if (omap2_pm_debug) {
 614                 unsigned long long tmp;
 615                 u32 resume_time;
 616
 617                 resume_time = omap2_read_32k_sync_counter();
 618                 tmp = resume_time - sleep_time;
 619                 tmp *= 1000000;
 620                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 621         }
 622 }
 623
 624 static int omap2_can_sleep(void)
 625 {
 626         if (!enable_dyn_sleep)
 627                 return 0;
 628         if (omap2_fclks_active())
 629                 return 0;
 630         if (atomic_read(&sleep_block) > 0)
 631                 return 0;
 632         if (clk_get_usecount(osc_ck) > 1)
 633                 return 0;
 634         if (omap_dma_running())
 635                 return 0;
 636
 637         return 1;
 638 }
 639
 640 static void omap2_pm_idle(void)
 641 {
 642         local_irq_disable();
 643         local_fiq_disable();
 644
 645         if (!omap2_can_sleep()) {
 646                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 647                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 648                  * transfer to complete), the increased latency is too much.
 649                  *
 650                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 651                  * to indicate this.
 652                  */
 653                 if (atomic_read(&sleep_block) == 0) {
 654                         timer_dyn_reprogram();
 655                         if (omap2_irq_pending())
 656                                 goto out;
 657                 }
 658                 omap2_enter_mpu_retention();
 659                 goto out;
 660         }
 661
 662         /*
 663          * Since an interrupt may set up a timer, we don't want to
 664          * reprogram the hardware timer with interrupts enabled.
 665          * Re-enable interrupts only after returning from idle.
 666          */
 667         timer_dyn_reprogram();
 668
 669         if (omap2_irq_pending())
 670                 goto out;
 671
 672         omap2_enter_full_retention();
 673
 674 out:
 675         local_fiq_enable();
 676         local_irq_enable();
 677 }
 678
 679 static int omap2_pm_prepare(suspend_state_t state)
 680 {
 681         int error = 0;
 682
 683         /* We cannot sleep in idle until we have resumed */
 684         saved_idle = pm_idle;
 685         pm_idle = NULL;
 686
 687         switch (state) {
 688         case PM_SUSPEND_STANDBY:
 689         case PM_SUSPEND_MEM:
 690                 break;
 691         case PM_SUSPEND_DISK:
 692                 return -ENOTSUPP;
 693         default:
 694                 return -EINVAL;
 695         }
 696
 697         return error;
 698 }
 699
 700 static int omap2_pm_suspend(void)
 701 {
 702         u32 wken_wkup, mir1;
 703
 704         wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
 705         prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
 706
 707         /* Mask GPT1 */
 708         mir1 = omap_readl(0x480fe0a4);
 709         omap_writel(1 << 5, 0x480fe0ac);
 710
 711         omap2_enter_full_retention();
 712
 713         omap_writel(mir1, 0x480fe0a4);
 714         prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
 715
 716         return 0;
 717 }
 718
 719 static int omap2_pm_enter(suspend_state_t state)
 720 {
 721         int ret = 0;
 722
 723         switch (state) {
 724         case PM_SUSPEND_STANDBY:
 725         case PM_SUSPEND_MEM:
 726                 ret = omap2_pm_suspend();
 727                 break;
 728         case PM_SUSPEND_DISK:
 729                 ret = -ENOTSUPP;
 730                 break;
 731         default:
 732                 ret = -EINVAL;
 733         }
 734
 735         return ret;
 736 }
 737
 738 static int omap2_pm_finish(suspend_state_t state)
 739 {
 740         pm_idle = saved_idle;
 741         return 0;
 742 }
 743
 744 static struct pm_ops omap_pm_ops = {
 745         .pm_disk_mode   = 0,
 746         .prepare        = omap2_pm_prepare,
 747         .enter          = omap2_pm_enter,
 748         .finish         = omap2_pm_finish,
 749 };
 750
 751 static void __init prcm_setup_regs(void)
 752 {
 753         u32 l;
 754
 755         /* Enable autoidle */
 756         prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
 757
 758         /* Set all domain wakeup dependencies */
 759         prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
 760         prcm_write_reg(PM_WKDEP_DSP, 0);
 761         prcm_write_reg(PM_WKDEP_GFX, 0);
 762
 763         l = prcm_read_reg(PM_PWSTCTRL_CORE);
 764         /* Enable retention for all memory blocks */
 765         l |= (1 << 3) | (1 << 4) | (1 << 5);
 766         /* Set power state to RETENTION */
 767         l &= ~0x03;
 768         l |= 0x01 << 0;
 769         prcm_write_reg(PM_PWSTCTRL_CORE, l);
 770
 771         prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
 772
 773         /* Power down DSP and GFX */
 774         prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
 775         prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
 776
 777         /* Enable clock auto control for all domains */
 778         prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
 779         prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
 780         prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
 781         prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
 782
 783         /* Enable clock autoidle for all domains */
 784         prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
 785         prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
 786         prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
 787         prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
 788
 789         prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
 790
 791         /* Put DPLL and both APLLs into autoidle mode */
 792         prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
 793
 794         prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
 795
 796         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 797          * stabilisation */
 798         prcm_write_reg(PRCM_CLKSSETUP, 15);
 799
 800         /* Configure automatic voltage transition */
 801         prcm_write_reg(PRCM_VOLTSETUP, 2);
 802         l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
 803                 SETRET_LEVEL(1) | VOLT_LEVEL(0);
 804         prcm_write_reg(PRCM_VOLTCTRL, l);
 805
 806         /* Enable wake-up events */
 807         prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
 808 }
 809
 810 int __init omap2_pm_init(void)
 811 {
 812         u32 l;
 813
 814         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 815         l = prcm_read_reg(PRCM_REVISION);
 816         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 817
 818         osc_ck = clk_get(NULL, "osc_ck");
 819         if (IS_ERR(osc_ck)) {
 820                 printk(KERN_ERR "could not get osc_ck\n");
 821                 return -ENODEV;
 822         }
 823
 824         emul_ck = clk_get(NULL, "emul_ck");
 825         if (IS_ERR(emul_ck)) {
 826                 printk(KERN_ERR "could not get emul_ck\n");
 827                 clk_put(osc_ck);
 828                 return -ENODEV;
 829         }
 830
 831         prcm_setup_regs();
 832
 833         pm_init_serial_console();
 834
 835         /* Hack to prevent MPU retention when STI console is enabled. */
 836         {
 837                 const struct omap_sti_console_config *sti;
 838
 839                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 840                                       struct omap_sti_console_config);
 841                 if (sti != NULL && sti->enable)
 842                         sti_console_enabled = 1;
 843         }
 844
 845         /*
 846          * We copy the assembler sleep/wakeup routines to SRAM.
 847          * These routines need to be in SRAM as that's the only
 848          * memory the MPU can see when it wakes up.
 849          */
 850         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 851                                          omap24xx_idle_loop_suspend_sz);
 852         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 853                                             omap24xx_cpu_suspend_sz);
 854
 855         pm_set_ops(&omap_pm_ops);
 856         pm_idle = omap2_pm_idle;
 857
 858         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 859         if (l)
 860                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 861
 862         return 0;
 863 }
 864
 865 late_initcall(omap2_pm_init);