arch/arm/mach-omap2/mmu.h

   1 #ifndef __MACH_OMAP2_MMU_H
   2 #define __MACH_OMAP2_MMU_H
   3
   4 #include <asm/arch/mmu.h>
   5 #include <asm/io.h>
   6
   7 #define MMU_LOCK_BASE_MASK              (0x1f << 10)
   8 #define MMU_LOCK_VICTIM_MASK            (0x1f << 4)
   9
  10 #define OMAP_MMU_REVISION               0x00
  11 #define OMAP_MMU_SYSCONFIG              0x10
  12 #define OMAP_MMU_SYSSTATUS              0x14
  13 #define OMAP_MMU_IRQSTATUS              0x18
  14 #define OMAP_MMU_IRQENABLE              0x1c
  15 #define OMAP_MMU_WALKING_ST             0x40
  16 #define OMAP_MMU_CNTL                   0x44
  17 #define OMAP_MMU_FAULT_AD               0x48
  18 #define OMAP_MMU_TTB                    0x4c
  19 #define OMAP_MMU_LOCK                   0x50
  20 #define OMAP_MMU_LD_TLB                 0x54
  21 #define OMAP_MMU_CAM                    0x58
  22 #define OMAP_MMU_RAM                    0x5c
  23 #define OMAP_MMU_GFLUSH                 0x60
  24 #define OMAP_MMU_FLUSH_ENTRY            0x64
  25 #define OMAP_MMU_READ_CAM               0x68
  26 #define OMAP_MMU_READ_RAM               0x6c
  27 #define OMAP_MMU_EMU_FAULT_AD           0x70
  28
  29 #define OMAP_MMU_CNTL_BURST_16MNGT_EN   0x0020
  30 #define OMAP_MMU_CNTL_WTL_EN            0x0004
  31 #define OMAP_MMU_CNTL_MMU_EN            0x0002
  32 #define OMAP_MMU_CNTL_RESET_SW          0x0001
  33
  34 #define OMAP_MMU_IRQ_MULTIHITFAULT      0x00000010
  35 #define OMAP_MMU_IRQ_TABLEWALKFAULT     0x00000008
  36 #define OMAP_MMU_IRQ_EMUMISS            0x00000004
  37 #define OMAP_MMU_IRQ_TRANSLATIONFAULT   0x00000002
  38 #define OMAP_MMU_IRQ_TLBMISS            0x00000001
  39
  40 #define OMAP_MMU_CAM_VATAG_MASK         0xfffff000
  41 #define OMAP_MMU_CAM_P                  0x00000008
  42 #define OMAP_MMU_CAM_V                  0x00000004
  43 #define OMAP_MMU_CAM_PAGESIZE_MASK      0x00000003
  44 #define OMAP_MMU_CAM_PAGESIZE_1MB       0x00000000
  45 #define OMAP_MMU_CAM_PAGESIZE_64KB      0x00000001
  46 #define OMAP_MMU_CAM_PAGESIZE_4KB       0x00000002
  47 #define OMAP_MMU_CAM_PAGESIZE_16MB      0x00000003
  48
  49 #define OMAP_MMU_RAM_PADDR_MASK         0xfffff000
  50 #define OMAP_MMU_RAM_ENDIANNESS         0x00000200
  51 #define OMAP_MMU_RAM_ENDIANNESS_BIG     0x00000200
  52 #define OMAP_MMU_RAM_ENDIANNESS_LITTLE  0x00000000
  53 #define OMAP_MMU_RAM_ELEMENTSIZE_MASK   0x00000180
  54 #define OMAP_MMU_RAM_ELEMENTSIZE_8      0x00000000
  55 #define OMAP_MMU_RAM_ELEMENTSIZE_16     0x00000080
  56 #define OMAP_MMU_RAM_ELEMENTSIZE_32     0x00000100
  57 #define OMAP_MMU_RAM_ELEMENTSIZE_NONE   0x00000180
  58 #define OMAP_MMU_RAM_MIXED              0x00000040
  59
  60 #define IOMAP_VAL       0x3f
  61
  62 #define omap_dsp_request_mem()  do { } while (0)
  63 #define omap_dsp_release_mem()  do { } while (0)
  64
  65 #define INIT_TLB_ENTRY(ent,v,p,ps)                              \
  66 do {                                                            \
  67         (ent)->va       = (v);                                  \
  68         (ent)->pa       = (p);                                  \
  69         (ent)->pgsz     = (ps);                                 \
  70         (ent)->prsvd    = 0;                                    \
  71         (ent)->endian   = OMAP_MMU_RAM_ENDIANNESS_LITTLE;       \
  72         (ent)->elsz     = OMAP_MMU_RAM_ELEMENTSIZE_16;          \
  73         (ent)->mixed    = 0;                                    \
  74         (ent)->tlb      = 1;                                    \
  75 } while (0)
  76
  77 #define INIT_TLB_ENTRY_4KB_PRESERVED(ent,v,p) \
  78 do {                                                            \
  79         (ent)->va       = (v);                                  \
  80         (ent)->pa       = (p);                                  \
  81         (ent)->pgsz     = OMAP_MMU_CAM_PAGESIZE_4KB;            \
  82         (ent)->prsvd    = OMAP_MMU_CAM_P;                       \
  83         (ent)->endian   = OMAP_MMU_RAM_ENDIANNESS_LITTLE;       \
  84         (ent)->elsz     = OMAP_MMU_RAM_ELEMENTSIZE_16;          \
  85         (ent)->mixed    = 0;                                    \
  86 } while (0)
  87
  88 #define INIT_TLB_ENTRY_4KB_ES32_PRESERVED(ent,v,p)              \
  89 do {                                                            \
  90         (ent)->va       = (v);                                  \
  91         (ent)->pa       = (p);                                  \
  92         (ent)->pgsz     = OMAP_MMU_CAM_PAGESIZE_4KB;            \
  93         (ent)->prsvd    = OMAP_MMU_CAM_P;                       \
  94         (ent)->endian   = OMAP_MMU_RAM_ENDIANNESS_LITTLE;       \
  95         (ent)->elsz     = OMAP_MMU_RAM_ELEMENTSIZE_32;          \
  96         (ent)->mixed    = 0;                                    \
  97 } while (0)
  98
  99 extern struct omap_mmu_ops omap2_mmu_ops;
 100
 101 struct omap_mmu_tlb_entry {
 102         unsigned long va;
 103         unsigned long pa;
 104         unsigned int pgsz, prsvd, valid;
 105
 106         u32 endian, elsz, mixed;
 107         unsigned int tlb;
 108 };
 109
 110 static inline unsigned long
 111 omap_mmu_read_reg(struct omap_mmu *mmu, unsigned long reg)
 112 {
 113         return __raw_readl(mmu->base + reg);
 114 }
 115
 116 static inline void omap_mmu_write_reg(struct omap_mmu *mmu,
 117                                unsigned long val, unsigned long reg)
 118 {
 119         __raw_writel(val, mmu->base + reg);
 120 }
 121 static inline void omap_mmu_itack(struct omap_mmu *mmu)
 122 {
 123 }
 124 #endif /* __MACH_OMAP2_MMU_H */