1 #ifndef __MACH_OMAP2_MMU_H
2 #define __MACH_OMAP2_MMU_H
4 #include <asm/arch/mmu.h>
7 #define MMU_LOCK_BASE_MASK (0x1f << 10)
8 #define MMU_LOCK_VICTIM_MASK (0x1f << 4)
10 #define OMAP_MMU_REVISION 0x00
11 #define OMAP_MMU_SYSCONFIG 0x10
12 #define OMAP_MMU_SYSSTATUS 0x14
13 #define OMAP_MMU_IRQSTATUS 0x18
14 #define OMAP_MMU_IRQENABLE 0x1c
15 #define OMAP_MMU_WALKING_ST 0x40
16 #define OMAP_MMU_CNTL 0x44
17 #define OMAP_MMU_FAULT_AD 0x48
18 #define OMAP_MMU_TTB 0x4c
19 #define OMAP_MMU_LOCK 0x50
20 #define OMAP_MMU_LD_TLB 0x54
21 #define OMAP_MMU_CAM 0x58
22 #define OMAP_MMU_RAM 0x5c
23 #define OMAP_MMU_GFLUSH 0x60
24 #define OMAP_MMU_FLUSH_ENTRY 0x64
25 #define OMAP_MMU_READ_CAM 0x68
26 #define OMAP_MMU_READ_RAM 0x6c
27 #define OMAP_MMU_EMU_FAULT_AD 0x70
29 #define OMAP_MMU_CNTL_BURST_16MNGT_EN 0x0020
30 #define OMAP_MMU_CNTL_WTL_EN 0x0004
31 #define OMAP_MMU_CNTL_MMU_EN 0x0002
32 #define OMAP_MMU_CNTL_RESET_SW 0x0001
34 #define OMAP_MMU_IRQ_MULTIHITFAULT 0x00000010
35 #define OMAP_MMU_IRQ_TABLEWALKFAULT 0x00000008
36 #define OMAP_MMU_IRQ_EMUMISS 0x00000004
37 #define OMAP_MMU_IRQ_TRANSLATIONFAULT 0x00000002
38 #define OMAP_MMU_IRQ_TLBMISS 0x00000001
40 #define OMAP_MMU_CAM_VATAG_MASK 0xfffff000
41 #define OMAP_MMU_CAM_P 0x00000008
42 #define OMAP_MMU_CAM_V 0x00000004
43 #define OMAP_MMU_CAM_PAGESIZE_MASK 0x00000003
44 #define OMAP_MMU_CAM_PAGESIZE_1MB 0x00000000
45 #define OMAP_MMU_CAM_PAGESIZE_64KB 0x00000001
46 #define OMAP_MMU_CAM_PAGESIZE_4KB 0x00000002
47 #define OMAP_MMU_CAM_PAGESIZE_16MB 0x00000003
49 #define OMAP_MMU_RAM_PADDR_MASK 0xfffff000
50 #define OMAP_MMU_RAM_ENDIANNESS 0x00000200
51 #define OMAP_MMU_RAM_ENDIANNESS_BIG 0x00000200
52 #define OMAP_MMU_RAM_ENDIANNESS_LITTLE 0x00000000
53 #define OMAP_MMU_RAM_ELEMENTSIZE_MASK 0x00000180
54 #define OMAP_MMU_RAM_ELEMENTSIZE_8 0x00000000
55 #define OMAP_MMU_RAM_ELEMENTSIZE_16 0x00000080
56 #define OMAP_MMU_RAM_ELEMENTSIZE_32 0x00000100
57 #define OMAP_MMU_RAM_ELEMENTSIZE_NONE 0x00000180
58 #define OMAP_MMU_RAM_MIXED 0x00000040
60 #define IOMAP_VAL 0x3f
62 #define INIT_TLB_ENTRY(ent, v, p, ps) \
68 (ent)->endian = OMAP_MMU_RAM_ENDIANNESS_LITTLE; \
69 (ent)->elsz = OMAP_MMU_RAM_ELEMENTSIZE_16; \
74 #define INIT_TLB_ENTRY_4KB_PRESERVED(ent, v, p) \
78 (ent)->pgsz = OMAP_MMU_CAM_PAGESIZE_4KB; \
79 (ent)->prsvd = OMAP_MMU_CAM_P; \
80 (ent)->endian = OMAP_MMU_RAM_ENDIANNESS_LITTLE; \
81 (ent)->elsz = OMAP_MMU_RAM_ELEMENTSIZE_16; \
85 #define INIT_TLB_ENTRY_4KB_ES32_PRESERVED(ent, v, p) \
89 (ent)->pgsz = OMAP_MMU_CAM_PAGESIZE_4KB; \
90 (ent)->prsvd = OMAP_MMU_CAM_P; \
91 (ent)->endian = OMAP_MMU_RAM_ENDIANNESS_LITTLE; \
92 (ent)->elsz = OMAP_MMU_RAM_ELEMENTSIZE_32; \
96 struct omap_mmu_tlb_entry {
99 unsigned int pgsz, prsvd, valid;
101 u32 endian, elsz, mixed;
105 static inline unsigned long
106 omap_mmu_read_reg(struct omap_mmu *mmu, unsigned long reg)
108 return __raw_readl(mmu->base + reg);
111 static inline void omap_mmu_write_reg(struct omap_mmu *mmu,
112 unsigned long val, unsigned long reg)
114 __raw_writel(val, mmu->base + reg);
117 #endif /* __MACH_OMAP2_MMU_H */