arch/arm/mach-omap2/mmu.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mmu.c
   3  *
   4  * Support for non-MPU OMAP2 MMUs.
   5  *
   6  * Copyright (C) 2002-2005 Nokia Corporation
   7  *
   8  * Written by Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
   9  *        and Paul Mundt <paul.mundt@nokia.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24  */
  25 #include <linux/types.h>
  26 #include <linux/init.h>
  27 #include <linux/rwsem.h>
  28 #include <linux/device.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include "mmu.h"
  32 #include <asm/arch/mmu.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/io.h>
  35 #include <asm/sizes.h>
  36
  37 static void *dspvect_page;
  38 #define DSP_INIT_PAGE   0xfff000
  39
  40 static inline void
  41 omap2_mmu_read_tlb(struct omap_mmu *mmu, struct cam_ram_regset *cr)
  42 {
  43         cr->cam = omap_mmu_read_reg(mmu, MMU_READ_CAM);
  44         cr->ram = omap_mmu_read_reg(mmu, MMU_READ_RAM);
  45 }
  46
  47 static inline void
  48 omap2_mmu_load_tlb(struct omap_mmu *mmu, struct cam_ram_regset *cr)
  49 {
  50         /* Set the CAM and RAM entries */
  51         omap_mmu_write_reg(mmu, cr->cam | OMAP_MMU_CAM_V, MMU_CAM);
  52         omap_mmu_write_reg(mmu, cr->ram, MMU_RAM);
  53 }
  54
  55 static void exmap_setup_iomap_page(struct omap_mmu *mmu, unsigned long phys,
  56                                    unsigned long dsp_io_adr, int index)
  57 {
  58         unsigned long dspadr;
  59         void *virt;
  60         struct omap_mmu_tlb_entry tlb_ent;
  61
  62         dspadr = (IOMAP_VAL << 18) + (dsp_io_adr << 1);
  63         virt = omap_mmu_to_virt(mmu, dspadr);
  64         exmap_set_armmmu((unsigned long)virt, phys, PAGE_SIZE);
  65         INIT_EXMAP_TBL_ENTRY_4KB_PRESERVED(mmu->exmap_tbl + index, NULL, virt);
  66         INIT_TLB_ENTRY_4KB_ES32_PRESERVED(&tlb_ent, dspadr, phys);
  67         omap_mmu_load_tlb_entry(mmu, &tlb_ent);
  68 }
  69
  70 static void exmap_clear_iomap_page(struct omap_mmu *mmu,
  71                                    unsigned long dsp_io_adr)
  72 {
  73         unsigned long dspadr;
  74         void *virt;
  75
  76         dspadr = (IOMAP_VAL << 18) + (dsp_io_adr << 1);
  77         virt = omap_mmu_to_virt(mmu, dspadr);
  78         exmap_clear_armmmu((unsigned long)virt, PAGE_SIZE);
  79         /* DSP MMU is shutting down. not handled here. */
  80 }
  81
  82 #define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
  83 #define OMAP2420_GPT5_BASE      (L4_24XX_BASE + 0x7c000)
  84 #define OMAP2420_GPT6_BASE      (L4_24XX_BASE + 0x7e000)
  85 #define OMAP2420_GPT7_BASE      (L4_24XX_BASE + 0x80000)
  86 #define OMAP2420_GPT8_BASE      (L4_24XX_BASE + 0x82000)
  87 #define OMAP24XX_EAC_BASE       (L4_24XX_BASE + 0x90000)
  88 #define OMAP24XX_STI_BASE       (L4_24XX_BASE + 0x68000)
  89 #define OMAP24XX_STI_CH_BASE    (L4_24XX_BASE + 0x0c000000)
  90
  91 static int exmap_setup_preserved_entries(struct omap_mmu *mmu)
  92 {
  93         int i, n = 0;
  94
  95         exmap_setup_preserved_mem_page(mmu, dspvect_page, DSP_INIT_PAGE, n++);
  96
  97         exmap_setup_iomap_page(mmu, OMAP24XX_PRCM_BASE, 0x7000, n++);
  98         exmap_setup_iomap_page(mmu, OMAP24XX_MAILBOX_BASE, 0x11000, n++);
  99
 100         if (cpu_is_omap2420()) {
 101                 exmap_setup_iomap_page(mmu, OMAP2420_GPT5_BASE, 0xe000, n++);
 102                 exmap_setup_iomap_page(mmu, OMAP2420_GPT6_BASE, 0xe800, n++);
 103                 exmap_setup_iomap_page(mmu, OMAP2420_GPT7_BASE, 0xf000, n++);
 104                 exmap_setup_iomap_page(mmu, OMAP2420_GPT8_BASE, 0xf800, n++);
 105                 exmap_setup_iomap_page(mmu, OMAP24XX_EAC_BASE,  0x10000, n++);
 106                 exmap_setup_iomap_page(mmu, OMAP24XX_STI_BASE, 0xc800, n++);
 107                 for (i = 0; i < 5; i++)
 108                         exmap_setup_preserved_mem_page(mmu,
 109                                 __va(OMAP24XX_STI_CH_BASE + i*SZ_4K),
 110                                 0xfb0000 + i*SZ_4K, n++);
 111         }
 112
 113         return n;
 114 }
 115
 116 static void exmap_clear_preserved_entries(struct omap_mmu *mmu)
 117 {
 118         int i;
 119
 120         exmap_clear_iomap_page(mmu, 0x7000);    /* PRCM registers */
 121         exmap_clear_iomap_page(mmu, 0x11000);   /* MAILBOX registers */
 122
 123         if (cpu_is_omap2420()) {
 124                 exmap_clear_iomap_page(mmu, 0xe000);    /* GPT5 */
 125                 exmap_clear_iomap_page(mmu, 0xe800);    /* GPT6 */
 126                 exmap_clear_iomap_page(mmu, 0xf000);    /* GPT7 */
 127                 exmap_clear_iomap_page(mmu, 0xf800);    /* GPT8 */
 128                 exmap_clear_iomap_page(mmu, 0x10000);   /* EAC */
 129                 exmap_clear_iomap_page(mmu, 0xc800);    /* STI */
 130                 for (i = 0; i < 5; i++)                 /* STI CH */
 131                         exmap_clear_mem_page(mmu, 0xfb0000 + i*SZ_4K);
 132         }
 133
 134         exmap_clear_mem_page(mmu, DSP_INIT_PAGE);
 135 }
 136
 137 #define MMU_IRQ_MASK \
 138         (OMAP_MMU_IRQ_MULTIHITFAULT | \
 139          OMAP_MMU_IRQ_TABLEWALKFAULT | \
 140          OMAP_MMU_IRQ_EMUMISS | \
 141          OMAP_MMU_IRQ_TRANSLATIONFAULT | \
 142          OMAP_MMU_IRQ_TLBMISS)
 143
 144 static int omap2_mmu_startup(struct omap_mmu *mmu)
 145 {
 146         dspvect_page = (void *)__get_dma_pages(GFP_KERNEL, 0);
 147         if (dspvect_page == NULL) {
 148                 printk(KERN_ERR "MMU: failed to allocate memory "
 149                                 "for dsp vector table\n");
 150                 return -ENOMEM;
 151         }
 152
 153         mmu->nr_exmap_preserved = exmap_setup_preserved_entries(mmu);
 154
 155         omap_mmu_write_reg(mmu, MMU_IRQ_MASK, MMU_IRQENABLE);
 156
 157         return 0;
 158 }
 159
 160 static void omap2_mmu_shutdown(struct omap_mmu *mmu)
 161 {
 162         exmap_clear_preserved_entries(mmu);
 163
 164         if (dspvect_page != NULL) {
 165                 unsigned long virt;
 166
 167                 down_read(&mmu->exmap_sem);
 168
 169                 virt = (unsigned long)omap_mmu_to_virt(mmu, DSP_INIT_PAGE);
 170                 flush_tlb_kernel_range(virt, virt + PAGE_SIZE);
 171                 free_page((unsigned long)dspvect_page);
 172                 dspvect_page = NULL;
 173
 174                 up_read(&mmu->exmap_sem);
 175         }
 176 }
 177
 178 static ssize_t omap2_mmu_show(struct omap_mmu *mmu, char *buf,
 179                               struct omap_mmu_tlb_lock *tlb_lock)
 180 {
 181         int i, len;
 182
 183         len = sprintf(buf, "P: preserved, V: valid\n"
 184                            "B: big endian, L:little endian, "
 185                            "M: mixed page attribute\n"
 186                            "ety P V size   cam_va     ram_pa E ES M\n");
 187                          /* 00: P V  4KB 0x300000 0x10171800 B 16 M */
 188
 189         for (i = 0; i < mmu->nr_tlb_entries; i++) {
 190                 struct omap_mmu_tlb_entry ent;
 191                 struct cam_ram_regset cr;
 192                 struct omap_mmu_tlb_lock entry_lock;
 193                 char *pgsz_str, *elsz_str;
 194
 195                 /* read a TLB entry */
 196                 entry_lock.base   = tlb_lock->base;
 197                 entry_lock.victim = i;
 198                 omap_mmu_read_tlb(mmu, &entry_lock, &cr);
 199
 200                 ent.pgsz   = cr.cam & OMAP_MMU_CAM_PAGESIZE_MASK;
 201                 ent.prsvd  = cr.cam & OMAP_MMU_CAM_P;
 202                 ent.valid  = cr.cam & OMAP_MMU_CAM_V;
 203                 ent.va     = cr.cam & OMAP_MMU_CAM_VATAG_MASK;
 204                 ent.endian = cr.ram & OMAP_MMU_RAM_ENDIANNESS;
 205                 ent.elsz   = cr.ram & OMAP_MMU_RAM_ELEMENTSIZE_MASK;
 206                 ent.pa     = cr.ram & OMAP_MMU_RAM_PADDR_MASK;
 207                 ent.mixed  = cr.ram & OMAP_MMU_RAM_MIXED;
 208
 209                 pgsz_str = (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_16MB) ? "64MB":
 210                            (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_1MB)  ? " 1MB":
 211                            (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_64KB) ? "64KB":
 212                            (ent.pgsz == OMAP_MMU_CAM_PAGESIZE_4KB)  ? " 4KB":
 213                                                                      " ???";
 214                 elsz_str = (ent.elsz == OMAP_MMU_RAM_ELEMENTSIZE_8)  ? " 8":
 215                            (ent.elsz == OMAP_MMU_RAM_ELEMENTSIZE_16) ? "16":
 216                            (ent.elsz == OMAP_MMU_RAM_ELEMENTSIZE_32) ? "32":
 217                                                                       "??";
 218
 219                 if (i == tlb_lock->base)
 220                         len += sprintf(buf + len, "lock base = %d\n",
 221                                        tlb_lock->base);
 222                 if (i == tlb_lock->victim)
 223                         len += sprintf(buf + len, "victim    = %d\n",
 224                                        tlb_lock->victim);
 225
 226                 len += sprintf(buf + len,
 227                                /* 00: P V  4KB 0x300000 0x10171800 B 16 M */
 228                                "%02d: %c %c %s 0x%06lx 0x%08lx %c %s %c\n",
 229                                i,
 230                                ent.prsvd ? 'P' : ' ',
 231                                ent.valid ? 'V' : ' ',
 232                                pgsz_str, ent.va, ent.pa,
 233                                ent.endian ? 'B' : 'L',
 234                                elsz_str,
 235                                ent.mixed ? 'M' : ' ');
 236         }
 237
 238         return len;
 239 }
 240
 241 #define get_cam_va_mask(pgsz) \
 242         (((pgsz) == OMAP_MMU_CAM_PAGESIZE_16MB) ? 0xff000000 : \
 243          ((pgsz) == OMAP_MMU_CAM_PAGESIZE_1MB)  ? 0xfff00000 : \
 244          ((pgsz) == OMAP_MMU_CAM_PAGESIZE_64KB) ? 0xffff0000 : \
 245          ((pgsz) == OMAP_MMU_CAM_PAGESIZE_4KB)  ? 0xfffff000 : 0)
 246
 247 static inline unsigned long omap2_mmu_cam_va(struct cam_ram_regset *cr)
 248 {
 249         unsigned int page_size = cr->cam & OMAP_MMU_CAM_PAGESIZE_MASK;
 250         unsigned int mask = get_cam_va_mask(cr->cam & page_size);
 251
 252         return cr->cam & mask;
 253 }
 254
 255 static struct cam_ram_regset *
 256 omap2_mmu_cam_ram_alloc(struct omap_mmu_tlb_entry *entry)
 257 {
 258         struct cam_ram_regset *cr;
 259
 260         if (entry->va & ~(get_cam_va_mask(entry->pgsz))) {
 261                 printk(KERN_ERR "MMU: mapping vadr (0x%06lx) is not on an "
 262                        "aligned boundary\n", entry->va);
 263                 return ERR_PTR(-EINVAL);
 264         }
 265
 266         cr = kmalloc(sizeof(struct cam_ram_regset), GFP_KERNEL);
 267
 268         cr->cam = (entry->va & OMAP_MMU_CAM_VATAG_MASK) |
 269                   entry->prsvd | entry->pgsz;
 270         cr->ram = entry->pa | entry->endian | entry->elsz;
 271
 272         return cr;
 273 }
 274
 275 static inline int omap2_mmu_cam_ram_valid(struct cam_ram_regset *cr)
 276 {
 277         return cr->cam & OMAP_MMU_CAM_V;
 278 }
 279
 280 static void omap2_mmu_interrupt(struct omap_mmu *mmu)
 281 {
 282         unsigned long status, va;
 283
 284         status = MMU_IRQ_MASK & omap_mmu_read_reg(mmu, MMU_IRQSTATUS);
 285         va = omap_mmu_read_reg(mmu, MMU_FAULT_AD);
 286
 287         pr_info("%s\n", (status & OMAP_MMU_IRQ_MULTIHITFAULT)           ? "multi hit":"");
 288         pr_info("%s\n", (status & OMAP_MMU_IRQ_TABLEWALKFAULT)          ? "table walk fault":"");
 289         pr_info("%s\n", (status & OMAP_MMU_IRQ_EMUMISS)                 ? "EMU miss":"");
 290         pr_info("%s\n", (status & OMAP_MMU_IRQ_TRANSLATIONFAULT)        ? "translation fault":"");
 291         pr_info("%s\n", (status & OMAP_MMU_IRQ_TLBMISS)                 ? "TLB miss":"");
 292         pr_info("fault address = %#08lx\n", va);
 293
 294         omap_mmu_disable(mmu);
 295         omap_mmu_write_reg(mmu, status, MMU_IRQSTATUS);
 296
 297         mmu->fault_address = va;
 298         schedule_work(&mmu->irq_work);
 299 }
 300 struct omap_mmu_ops omap2_mmu_ops = {
 301         .startup        = omap2_mmu_startup,
 302         .shutdown       = omap2_mmu_shutdown,
 303         .read_tlb       = omap2_mmu_read_tlb,
 304         .load_tlb       = omap2_mmu_load_tlb,
 305         .show           = omap2_mmu_show,
 306         .cam_va         = omap2_mmu_cam_va,
 307         .cam_ram_alloc  = omap2_mmu_cam_ram_alloc,
 308         .cam_ram_valid  = omap2_mmu_cam_ram_valid,
 309         .interrupt      = omap2_mmu_interrupt,
 310 };
 311 EXPORT_SYMBOL_GPL(omap2_mmu_ops);
 312
 313 MODULE_LICENSE("GPL");