arch/arm/mach-omap2/mmc-twl4030.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mmc-twl4030.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/i2c/twl4030.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/control.h>
  23 #include <mach/mmc.h>
  24 #include <mach/board.h>
  25
  26 #include "mmc-twl4030.h"
  27
  28 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  29
  30 #define TWL_GPIO_IMR1A          0x1C
  31 #define TWL_GPIO_ISR1A          0x19
  32 #define LDO_CLR                 0x00
  33 #define VSEL_S2_CLR             0x40
  34 #define GPIO_0_BIT_POS          (1 << 0)
  35
  36 #define VMMC1_DEV_GRP           0x27
  37 #define VMMC1_CLR               0x00
  38 #define VMMC1_315V              0x03
  39 #define VMMC1_300V              0x02
  40 #define VMMC1_285V              0x01
  41 #define VMMC1_185V              0x00
  42 #define VMMC1_DEDICATED         0x2A
  43
  44 #define VMMC2_DEV_GRP           0x2B
  45 #define VMMC2_CLR               0x40
  46 #define VMMC2_315V              0x0c
  47 #define VMMC2_300V              0x0b
  48 #define VMMC2_285V              0x0a
  49 #define VMMC2_260V              0x08
  50 #define VMMC2_185V              0x06
  51 #define VMMC2_DEDICATED         0x2E
  52
  53 #define VMMC_DEV_GRP_P1         0x20
  54
  55 static u16 control_pbias_offset;
  56
  57 static struct twl_mmc_controller {
  58         u16             control_devconf_offset;
  59         u32             devconf_loopback_clock;
  60         int             card_detect_gpio;
  61         u8              twl_vmmc_dev_grp;
  62         u8              twl_mmc_dedicated;
  63 } hsmmc[] = {
  64         {
  65                 .control_devconf_offset         = OMAP2_CONTROL_DEVCONF0,
  66                 .devconf_loopback_clock         = OMAP2_MMCSDIO1ADPCLKISEL,
  67                 .card_detect_gpio               = OMAP_MAX_GPIO_LINES,
  68                 .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
  69                 .twl_mmc_dedicated              = VMMC1_DEDICATED,
  70         },
  71         {
  72                 /* control_devconf_offset set dynamically */
  73                 .devconf_loopback_clock         = OMAP2_MMCSDIO2ADPCLKISEL,
  74                 .twl_vmmc_dev_grp               = VMMC2_DEV_GRP,
  75                 .twl_mmc_dedicated              = VMMC2_DEDICATED,
  76         },
  77  };
  78
  79 static int twl_mmc1_card_detect(int irq)
  80 {
  81         return gpio_get_value_cansleep(hsmmc[0].card_detect_gpio);
  82 }
  83
  84 /*
  85  * MMC Slot Initialization.
  86  */
  87 static int twl_mmc1_late_init(struct device *dev)
  88 {
  89         int ret = 0;
  90
  91         /*
  92          * Configure TWL4030 GPIO parameters for MMC hotplug irq
  93          */
  94         ret = gpio_request(hsmmc[0].card_detect_gpio, "mmc0_cd");
  95         if (ret)
  96                 goto err;
  97
  98         ret = twl4030_set_gpio_debounce(0, true);
  99         if (ret)
 100                 goto err;
 101
 102         return ret;
 103
 104 err:
 105         dev_err(dev, "Failed to configure TWL4030 GPIO IRQ\n");
 106
 107         return ret;
 108 }
 109
 110 static void twl_mmc1_cleanup(struct device *dev)
 111 {
 112         gpio_free(hsmmc[0].card_detect_gpio);
 113 }
 114
 115 #ifdef CONFIG_PM
 116
 117 /*
 118  * Mask and unmask MMC Card Detect Interrupt
 119  * mask : 1
 120  * unmask : 0
 121  */
 122 static int twl_mmc_mask_cd_interrupt(int mask)
 123 {
 124         u8 reg = 0, ret = 0;
 125
 126         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_IMR1A);
 127         if (ret)
 128                 goto err;
 129
 130         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 131
 132         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_IMR1A);
 133         if (ret)
 134                 goto err;
 135
 136         ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &reg, TWL_GPIO_ISR1A);
 137         if (ret)
 138                 goto err;
 139
 140         reg = (mask == 1) ? (reg | GPIO_0_BIT_POS) : (reg & ~GPIO_0_BIT_POS);
 141
 142         ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, reg, TWL_GPIO_ISR1A);
 143         if (ret)
 144                 goto err;
 145
 146 err:
 147         return ret;
 148 }
 149
 150 static int twl_mmc1_suspend(struct device *dev, int slot)
 151 {
 152         int ret = 0;
 153
 154         disable_irq(hsmmc[0].card_detect_gpio);
 155         ret = twl_mmc_mask_cd_interrupt(1);
 156
 157         return ret;
 158 }
 159
 160 static int twl_mmc1_resume(struct device *dev, int slot)
 161 {
 162         int ret = 0;
 163
 164         enable_irq(hsmmc[0].card_detect_gpio);
 165         ret = twl_mmc_mask_cd_interrupt(0);
 166
 167         return ret;
 168 }
 169
 170 #else
 171 #define twl_mmc1_suspend        NULL
 172 #define twl_mmc1_resume         NULL
 173 #endif
 174
 175 /*
 176  * Sets the MMC voltage in twl4030
 177  */
 178 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
 179 {
 180         int ret;
 181         u8 vmmc, dev_grp_val;
 182
 183         switch (1 << vdd) {
 184         case MMC_VDD_35_36:
 185         case MMC_VDD_34_35:
 186         case MMC_VDD_33_34:
 187         case MMC_VDD_32_33:
 188         case MMC_VDD_31_32:
 189         case MMC_VDD_30_31:
 190                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 191                         vmmc = VMMC1_315V;
 192                 else
 193                         vmmc = VMMC2_315V;
 194                 break;
 195         case MMC_VDD_29_30:
 196                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 197                         vmmc = VMMC1_315V;
 198                 else
 199                         vmmc = VMMC2_300V;
 200                 break;
 201         case MMC_VDD_27_28:
 202         case MMC_VDD_26_27:
 203                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 204                         vmmc = VMMC1_285V;
 205                 else
 206                         vmmc = VMMC2_285V;
 207                 break;
 208         case MMC_VDD_25_26:
 209         case MMC_VDD_24_25:
 210         case MMC_VDD_23_24:
 211         case MMC_VDD_22_23:
 212         case MMC_VDD_21_22:
 213         case MMC_VDD_20_21:
 214                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 215                         vmmc = VMMC1_285V;
 216                 else
 217                         vmmc = VMMC2_260V;
 218                 break;
 219         case MMC_VDD_165_195:
 220                 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
 221                         vmmc = VMMC1_185V;
 222                 else
 223                         vmmc = VMMC2_185V;
 224                 break;
 225         default:
 226                 vmmc = 0;
 227                 break;
 228         }
 229
 230         if (vmmc)
 231                 dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
 232         else
 233                 dev_grp_val = LDO_CLR;          /* Power down */
 234
 235         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 236                                         dev_grp_val, c->twl_vmmc_dev_grp);
 237         if (ret)
 238                 return ret;
 239
 240         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 241                                         vmmc, c->twl_mmc_dedicated);
 242
 243         return ret;
 244 }
 245
 246 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 247                                 int vdd)
 248 {
 249         u32 reg;
 250         int ret = 0;
 251         struct twl_mmc_controller *c = &hsmmc[0];
 252
 253         if (power_on) {
 254                 if (cpu_is_omap2430()) {
 255                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
 256                         if ((1 << vdd) >= MMC_VDD_30_31)
 257                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
 258                         else
 259                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
 260                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 261                 }
 262
 263                 /* REVISIT: Loop back clock not needed for 2430? */
 264                 if (!cpu_is_omap2430()) {
 265                         reg = omap_ctrl_readl(c->control_devconf_offset);
 266                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
 267                         omap_ctrl_writel(reg, c->control_devconf_offset);
 268                 }
 269
 270                 reg = omap_ctrl_readl(control_pbias_offset);
 271                 reg |= OMAP2_PBIASSPEEDCTRL0;
 272                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 273                 omap_ctrl_writel(reg, control_pbias_offset);
 274
 275                 ret = twl_mmc_set_voltage(c, vdd);
 276
 277                 /* 100ms delay required for PBIAS configuration */
 278                 msleep(100);
 279                 reg = omap_ctrl_readl(control_pbias_offset);
 280                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 281                 if ((1 << vdd) <= MMC_VDD_165_195)
 282                         reg &= ~OMAP2_PBIASLITEVMODE0;
 283                 else
 284                         reg |= OMAP2_PBIASLITEVMODE0;
 285                 omap_ctrl_writel(reg, control_pbias_offset);
 286         } else {
 287                 reg = omap_ctrl_readl(control_pbias_offset);
 288                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 289                 omap_ctrl_writel(reg, control_pbias_offset);
 290
 291                 ret = twl_mmc_set_voltage(c, 0);
 292
 293                 /* 100ms delay required for PBIAS configuration */
 294                 msleep(100);
 295                 reg = omap_ctrl_readl(control_pbias_offset);
 296                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 297                         OMAP2_PBIASLITEVMODE0);
 298                 omap_ctrl_writel(reg, control_pbias_offset);
 299         }
 300
 301         return ret;
 302 }
 303
 304 static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
 305 {
 306         int ret;
 307
 308         struct twl_mmc_controller *c = &hsmmc[1];
 309
 310         if (power_on) {
 311                 u32 reg;
 312
 313                 reg = omap_ctrl_readl(c->control_devconf_offset);
 314                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 315                 omap_ctrl_writel(reg, c->control_devconf_offset);
 316                 ret = twl_mmc_set_voltage(c, vdd);
 317         } else {
 318                 ret = twl_mmc_set_voltage(c, 0);
 319         }
 320
 321         return ret;
 322 }
 323
 324 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC];
 325
 326 #define HSMMC_NAME_LEN  9
 327
 328 void __init hsmmc_init(struct twl4030_hsmmc_info *controllers)
 329 {
 330         struct twl4030_hsmmc_info *c;
 331
 332         if (cpu_is_omap2430()) {
 333                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 334                 hsmmc[1].control_devconf_offset = OMAP243X_CONTROL_DEVCONF1;
 335         } else {
 336                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 337                 hsmmc[1].control_devconf_offset = OMAP343X_CONTROL_DEVCONF1;
 338         }
 339
 340         for (c = controllers; c->mmc; c++) {
 341                 struct omap_mmc_platform_data *mmc;
 342                 char *name;
 343
 344                 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 345                 if (!mmc) {
 346                         pr_err("Cannot allocate memory for mmc device!\n");
 347                         return;
 348                 }
 349
 350                 name = kzalloc(HSMMC_NAME_LEN, GFP_KERNEL);
 351                 if (!name) {
 352                         kfree(mmc);
 353                         pr_err("Cannot allocate memory for mmc name!\n");
 354                         return;
 355                 }
 356
 357                 sprintf(name, "mmc%islot%i", c->mmc, 1);
 358                 mmc->slots[0].name = name;
 359                 mmc->nr_slots = 1;
 360                 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
 361                                         MMC_VDD_26_27 | MMC_VDD_27_28 |
 362                                         MMC_VDD_29_30 |
 363                                         MMC_VDD_30_31 | MMC_VDD_31_32;
 364                 mmc->slots[0].wires = c->wires;
 365                 if (c->gpio_cd != -EINVAL)
 366                         mmc->slots[0].card_detect_irq = c->gpio_cd;
 367                 mmc->dma_mask = 0xffffffff;
 368
 369                 switch (c->mmc) {
 370                 case 1:
 371                         mmc->init = twl_mmc1_late_init;
 372                         mmc->cleanup = twl_mmc1_cleanup;
 373                         mmc->suspend = twl_mmc1_suspend;
 374                         mmc->resume = twl_mmc1_resume;
 375                         mmc->slots[0].set_power = twl_mmc1_set_power;
 376                         mmc->slots[0].card_detect = twl_mmc1_card_detect;
 377                         hsmmc_data[0] = mmc;
 378                         break;
 379                 case 2:
 380                         mmc->slots[0].set_power = twl_mmc2_set_power;
 381                         hsmmc_data[1] = mmc;
 382                         break;
 383                 default:
 384                         pr_err("Unknown MMC configuration!\n");
 385                         return;
 386                 }
 387         }
 388
 389         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 390 }
 391
 392 #endif