2 * linux/arch/arm/mach-omap2/mmc-twl4030.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c/twl4030.h>
20 #include <linux/regulator/machine.h>
22 #include <mach/hardware.h>
23 #include <mach/control.h>
25 #include <mach/board.h>
27 #include "mmc-twl4030.h"
29 #if defined(CONFIG_TWL4030_CORE) && \
30 (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
33 #define VSEL_S2_CLR 0x40
35 #define VMMC1_DEV_GRP 0x27
36 #define VMMC1_CLR 0x00
37 #define VMMC1_315V 0x03
38 #define VMMC1_300V 0x02
39 #define VMMC1_285V 0x01
40 #define VMMC1_185V 0x00
41 #define VMMC1_DEDICATED 0x2A
43 #define VMMC2_DEV_GRP 0x2B
44 #define VMMC2_CLR 0x40
45 #define VMMC2_315V 0x0c
46 #define VMMC2_300V 0x0b
47 #define VMMC2_285V 0x0a
48 #define VMMC2_280V 0x09
49 #define VMMC2_260V 0x08
50 #define VMMC2_185V 0x06
51 #define VMMC2_DEDICATED 0x2E
53 #define VMMC_DEV_GRP_P1 0x20
55 static u16 control_pbias_offset;
56 static u16 control_devconf1_offset;
58 #define HSMMC_NAME_LEN 9
60 static struct twl_mmc_controller {
61 struct omap_mmc_platform_data *mmc;
64 char name[HSMMC_NAME_LEN + 1];
65 } hsmmc[OMAP34XX_NR_MMC] = {
67 .twl_vmmc_dev_grp = VMMC1_DEV_GRP,
68 .twl_mmc_dedicated = VMMC1_DEDICATED,
71 .twl_vmmc_dev_grp = VMMC2_DEV_GRP,
72 .twl_mmc_dedicated = VMMC2_DEDICATED,
76 static int twl_mmc_card_detect(int irq)
80 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
81 struct omap_mmc_platform_data *mmc;
86 if (irq != mmc->slots[0].card_detect_irq)
89 /* NOTE: assumes card detect signal is active-low */
90 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
95 static int twl_mmc_get_ro(struct device *dev, int slot)
97 struct omap_mmc_platform_data *mmc = dev->platform_data;
99 /* NOTE: assumes write protect signal is active-high */
100 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
104 * MMC Slot Initialization.
106 static int twl_mmc_late_init(struct device *dev)
108 struct omap_mmc_platform_data *mmc = dev->platform_data;
112 ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
115 ret = gpio_direction_input(mmc->slots[0].switch_pin);
119 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
120 if (hsmmc[i].name == mmc->slots[0].name) {
129 gpio_free(mmc->slots[0].switch_pin);
131 mmc->slots[0].card_detect_irq = 0;
132 mmc->slots[0].card_detect = NULL;
134 dev_err(dev, "err %d configuring card detect\n", ret);
138 static void twl_mmc_cleanup(struct device *dev)
140 struct omap_mmc_platform_data *mmc = dev->platform_data;
142 gpio_free(mmc->slots[0].switch_pin);
147 static int twl_mmc_suspend(struct device *dev, int slot)
149 struct omap_mmc_platform_data *mmc = dev->platform_data;
151 disable_irq(mmc->slots[0].card_detect_irq);
155 static int twl_mmc_resume(struct device *dev, int slot)
157 struct omap_mmc_platform_data *mmc = dev->platform_data;
159 enable_irq(mmc->slots[0].card_detect_irq);
164 #define twl_mmc_suspend NULL
165 #define twl_mmc_resume NULL
169 * Sets the MMC voltage in twl4030
172 #define MMC1_OCR (MMC_VDD_165_195 \
173 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
174 #define MMC2_OCR (MMC_VDD_165_195 \
175 |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
176 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
178 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
181 u8 vmmc = 0, dev_grp_val;
186 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
187 /* VMMC1: max 220 mA. And for 8-bit mode,
191 case MMC_VDD_165_195:
206 /* error if VSIM needed */
211 } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
212 /* VMMC2: max 100 mA */
214 case MMC_VDD_165_195:
243 dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */
245 dev_grp_val = LDO_CLR; /* Power down */
247 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
248 dev_grp_val, c->twl_vmmc_dev_grp);
252 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
253 vmmc, c->twl_mmc_dedicated);
258 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
263 struct twl_mmc_controller *c = &hsmmc[0];
264 struct omap_mmc_platform_data *mmc = dev->platform_data;
267 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
268 * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
269 * 1.8V and 3.0V modes, controlled by the PBIAS register.
271 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
272 * is most naturally TWL VSIM; those pins also use PBIAS.
275 if (cpu_is_omap2430()) {
276 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
277 if ((1 << vdd) >= MMC_VDD_30_31)
278 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
280 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
281 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
284 if (mmc->slots[0].internal_clock) {
285 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
286 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
287 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
290 reg = omap_ctrl_readl(control_pbias_offset);
291 reg |= OMAP2_PBIASSPEEDCTRL0;
292 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
293 omap_ctrl_writel(reg, control_pbias_offset);
295 ret = twl_mmc_set_voltage(c, vdd);
297 /* 100ms delay required for PBIAS configuration */
299 reg = omap_ctrl_readl(control_pbias_offset);
300 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
301 if ((1 << vdd) <= MMC_VDD_165_195)
302 reg &= ~OMAP2_PBIASLITEVMODE0;
304 reg |= OMAP2_PBIASLITEVMODE0;
305 omap_ctrl_writel(reg, control_pbias_offset);
307 reg = omap_ctrl_readl(control_pbias_offset);
308 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
309 omap_ctrl_writel(reg, control_pbias_offset);
311 ret = twl_mmc_set_voltage(c, 0);
313 /* 100ms delay required for PBIAS configuration */
315 reg = omap_ctrl_readl(control_pbias_offset);
316 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
317 OMAP2_PBIASLITEVMODE0);
318 omap_ctrl_writel(reg, control_pbias_offset);
324 static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
327 struct twl_mmc_controller *c = &hsmmc[1];
328 struct omap_mmc_platform_data *mmc = dev->platform_data;
331 * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
332 * VDDS is used to power the pins, optionally with a transceiver to
333 * support cards using voltages other than VDDS (1.8V nominal). When a
334 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
337 if (mmc->slots[0].internal_clock) {
340 reg = omap_ctrl_readl(control_devconf1_offset);
341 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
342 omap_ctrl_writel(reg, control_devconf1_offset);
344 ret = twl_mmc_set_voltage(c, vdd);
346 ret = twl_mmc_set_voltage(c, 0);
352 static int twl_mmc3_set_power(struct device *dev, int slot, int power_on,
356 * Assume MMC3 has self-powered device connected, for example on-board
357 * chip with external power source.
362 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
364 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
366 struct twl4030_hsmmc_info *c;
367 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
369 if (cpu_is_omap2430()) {
370 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
371 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
374 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
375 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
378 for (c = controllers; c->mmc; c++) {
379 struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
380 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
382 if (!c->mmc || c->mmc > nr_hsmmc) {
383 pr_debug("MMC%d: no such controller\n", c->mmc);
387 pr_debug("MMC%d: already configured\n", c->mmc);
391 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
393 pr_err("Cannot allocate memory for mmc device!\n");
397 snprintf(twl->name, ARRAY_SIZE(twl->name), "mmc%islot%i",
399 mmc->slots[0].name = twl->name;
401 mmc->slots[0].wires = c->wires;
402 mmc->slots[0].internal_clock = !c->ext_clock;
403 mmc->dma_mask = 0xffffffff;
405 /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
406 if (gpio_is_valid(c->gpio_cd)) {
407 mmc->init = twl_mmc_late_init;
408 mmc->cleanup = twl_mmc_cleanup;
409 mmc->suspend = twl_mmc_suspend;
410 mmc->resume = twl_mmc_resume;
412 mmc->slots[0].switch_pin = c->gpio_cd;
413 mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
414 mmc->slots[0].card_detect = twl_mmc_card_detect;
416 mmc->slots[0].switch_pin = -EINVAL;
418 /* write protect normally uses an OMAP gpio */
419 if (gpio_is_valid(c->gpio_wp)) {
420 gpio_request(c->gpio_wp, "mmc_wp");
421 gpio_direction_input(c->gpio_wp);
423 mmc->slots[0].gpio_wp = c->gpio_wp;
424 mmc->slots[0].get_ro = twl_mmc_get_ro;
426 mmc->slots[0].gpio_wp = -EINVAL;
428 /* NOTE: we assume OMAP's MMC1 and MMC2 use
429 * the TWL4030's VMMC1 and VMMC2, respectively;
430 * and that MMC3 device has it's own power source.
435 mmc->slots[0].set_power = twl_mmc1_set_power;
436 mmc->slots[0].ocr_mask = MMC1_OCR;
439 mmc->slots[0].set_power = twl_mmc2_set_power;
441 mmc->slots[0].ocr_mask = MMC2_OCR;
443 mmc->slots[0].ocr_mask = MMC_VDD_165_195;
446 mmc->slots[0].set_power = twl_mmc3_set_power;
447 mmc->slots[0].ocr_mask = MMC_VDD_165_195;
450 pr_err("MMC%d configuration not supported!\n", c->mmc);
454 hsmmc_data[c->mmc - 1] = mmc;
457 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
459 /* pass the device nodes back to board setup code */
460 for (c = controllers; c->mmc; c++) {
461 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
463 if (!c->mmc || c->mmc > nr_hsmmc)