arch/arm/mach-omap2/mmc-twl4030.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mmc-twl4030.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/gpio.h>
  19 #include <linux/i2c/twl4030.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/control.h>
  23 #include <mach/mmc.h>
  24 #include <mach/board.h>
  25
  26 #include "mmc-twl4030.h"
  27
  28 #if defined(CONFIG_TWL4030_CORE) && \
  29         (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
  30
  31 #define LDO_CLR                 0x00
  32 #define VSEL_S2_CLR             0x40
  33
  34 #define VMMC1_DEV_GRP           0x27
  35 #define VMMC1_CLR               0x00
  36 #define VMMC1_315V              0x03
  37 #define VMMC1_300V              0x02
  38 #define VMMC1_285V              0x01
  39 #define VMMC1_185V              0x00
  40 #define VMMC1_DEDICATED         0x2A
  41
  42 #define VMMC2_DEV_GRP           0x2B
  43 #define VMMC2_CLR               0x40
  44 #define VMMC2_315V              0x0c
  45 #define VMMC2_300V              0x0b
  46 #define VMMC2_285V              0x0a
  47 #define VMMC2_280V              0x09
  48 #define VMMC2_260V              0x08
  49 #define VMMC2_185V              0x06
  50 #define VMMC2_DEDICATED         0x2E
  51
  52 #define VMMC_DEV_GRP_P1         0x20
  53
  54 static u16 control_pbias_offset;
  55 static u16 control_devconf1_offset;
  56
  57 #define HSMMC_NAME_LEN  9
  58
  59 static struct twl_mmc_controller {
  60         struct omap_mmc_platform_data   *mmc;
  61         u8              twl_vmmc_dev_grp;
  62         u8              twl_mmc_dedicated;
  63         char            name[HSMMC_NAME_LEN];
  64 } hsmmc[] = {
  65         {
  66                 .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
  67                 .twl_mmc_dedicated              = VMMC1_DEDICATED,
  68         },
  69         {
  70                 .twl_vmmc_dev_grp               = VMMC2_DEV_GRP,
  71                 .twl_mmc_dedicated              = VMMC2_DEDICATED,
  72         },
  73 };
  74
  75 static int twl_mmc_card_detect(int irq)
  76 {
  77         unsigned i;
  78
  79         for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
  80                 struct omap_mmc_platform_data *mmc;
  81
  82                 mmc = hsmmc[i].mmc;
  83                 if (!mmc)
  84                         continue;
  85                 if (irq != mmc->slots[0].card_detect_irq)
  86                         continue;
  87
  88                 /* NOTE: assumes card detect signal is active-low */
  89                 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  90         }
  91         return -ENOSYS;
  92 }
  93
  94 static int twl_mmc_get_ro(struct device *dev, int slot)
  95 {
  96         struct omap_mmc_platform_data *mmc = dev->platform_data;
  97
  98         /* NOTE: assumes write protect signal is active-high */
  99         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 100 }
 101
 102 /*
 103  * MMC Slot Initialization.
 104  */
 105 static int twl_mmc_late_init(struct device *dev)
 106 {
 107         struct omap_mmc_platform_data *mmc = dev->platform_data;
 108         int ret = 0;
 109         int i;
 110
 111         ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
 112         if (ret)
 113                 goto done;
 114         ret = gpio_direction_input(mmc->slots[0].switch_pin);
 115         if (ret)
 116                 goto err;
 117
 118         for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
 119                 if (hsmmc[i].name == mmc->slots[0].name) {
 120                         hsmmc[i].mmc = mmc;
 121                         break;
 122                 }
 123         }
 124
 125         return 0;
 126
 127 err:
 128         gpio_free(mmc->slots[0].switch_pin);
 129 done:
 130         mmc->slots[0].card_detect_irq = 0;
 131         mmc->slots[0].card_detect = NULL;
 132
 133         dev_err(dev, "err %d configuring card detect\n", ret);
 134         return ret;
 135 }
 136
 137 static void twl_mmc_cleanup(struct device *dev)
 138 {
 139         struct omap_mmc_platform_data *mmc = dev->platform_data;
 140
 141         gpio_free(mmc->slots[0].switch_pin);
 142 }
 143
 144 #ifdef CONFIG_PM
 145
 146 static int twl_mmc_suspend(struct device *dev, int slot)
 147 {
 148         struct omap_mmc_platform_data *mmc = dev->platform_data;
 149
 150         disable_irq(mmc->slots[0].card_detect_irq);
 151         return 0;
 152 }
 153
 154 static int twl_mmc_resume(struct device *dev, int slot)
 155 {
 156         struct omap_mmc_platform_data *mmc = dev->platform_data;
 157
 158         enable_irq(mmc->slots[0].card_detect_irq);
 159         return 0;
 160 }
 161
 162 #else
 163 #define twl_mmc_suspend NULL
 164 #define twl_mmc_resume  NULL
 165 #endif
 166
 167 /*
 168  * Sets the MMC voltage in twl4030
 169  */
 170
 171 #define MMC1_OCR        (MMC_VDD_165_195 \
 172                 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
 173 #define MMC2_OCR        (MMC_VDD_165_195 \
 174                 |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
 175                 |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
 176
 177 static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
 178 {
 179         int ret;
 180         u8 vmmc, dev_grp_val;
 181
 182         if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
 183                 /* VMMC1:  max 220 mA.  And for 8-bit mode,
 184                  * VSIM:  max 50 mA
 185                  */
 186                 switch (1 << vdd) {
 187                 case MMC_VDD_165_195:
 188                         vmmc = VMMC1_185V;
 189                         /* and VSIM_180V */
 190                         break;
 191                 case MMC_VDD_28_29:
 192                         vmmc = VMMC1_285V;
 193                         /* and VSIM_280V */
 194                         break;
 195                 case MMC_VDD_29_30:
 196                 case MMC_VDD_30_31:
 197                         vmmc = VMMC1_300V;
 198                         /* and VSIM_300V */
 199                         break;
 200                 case MMC_VDD_31_32:
 201                         vmmc = VMMC1_315V;
 202                         /* error if VSIM needed */
 203                         break;
 204                 default:
 205                         vmmc = 0;
 206                         break;
 207                 }
 208         } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
 209                 /* VMMC2:  max 100 mA */
 210                 switch (1 << vdd) {
 211                 case MMC_VDD_165_195:
 212                         vmmc = VMMC2_185V;
 213                         break;
 214                 case MMC_VDD_25_26:
 215                 case MMC_VDD_26_27:
 216                         vmmc = VMMC2_260V;
 217                         break;
 218                 case MMC_VDD_27_28:
 219                         vmmc = VMMC2_280V;
 220                         break;
 221                 case MMC_VDD_28_29:
 222                         vmmc = VMMC2_285V;
 223                         break;
 224                 case MMC_VDD_29_30:
 225                 case MMC_VDD_30_31:
 226                         vmmc = VMMC2_300V;
 227                         break;
 228                 case MMC_VDD_31_32:
 229                         vmmc = VMMC2_315V;
 230                         break;
 231                 default:
 232                         vmmc = 0;
 233                         break;
 234                 }
 235         } else {
 236                 return 0;
 237         }
 238
 239         if (vmmc)
 240                 dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
 241         else
 242                 dev_grp_val = LDO_CLR;          /* Power down */
 243
 244         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 245                                         dev_grp_val, c->twl_vmmc_dev_grp);
 246         if (ret)
 247                 return ret;
 248
 249         ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
 250                                         vmmc, c->twl_mmc_dedicated);
 251
 252         return ret;
 253 }
 254
 255 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 256                                 int vdd)
 257 {
 258         u32 reg;
 259         int ret = 0;
 260         struct twl_mmc_controller *c = &hsmmc[0];
 261         struct omap_mmc_platform_data *mmc = dev->platform_data;
 262
 263         /*
 264          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 265          * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
 266          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 267          *
 268          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 269          * is most naturally TWL VSIM; those pins also use PBIAS.
 270          */
 271         if (power_on) {
 272                 if (cpu_is_omap2430()) {
 273                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
 274                         if ((1 << vdd) >= MMC_VDD_30_31)
 275                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
 276                         else
 277                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
 278                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 279                 }
 280
 281                 if (mmc->slots[0].internal_clock) {
 282                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 283                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
 284                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
 285                 }
 286
 287                 reg = omap_ctrl_readl(control_pbias_offset);
 288                 reg |= OMAP2_PBIASSPEEDCTRL0;
 289                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 290                 omap_ctrl_writel(reg, control_pbias_offset);
 291
 292                 ret = twl_mmc_set_voltage(c, vdd);
 293
 294                 /* 100ms delay required for PBIAS configuration */
 295                 msleep(100);
 296                 reg = omap_ctrl_readl(control_pbias_offset);
 297                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 298                 if ((1 << vdd) <= MMC_VDD_165_195)
 299                         reg &= ~OMAP2_PBIASLITEVMODE0;
 300                 else
 301                         reg |= OMAP2_PBIASLITEVMODE0;
 302                 omap_ctrl_writel(reg, control_pbias_offset);
 303         } else {
 304                 reg = omap_ctrl_readl(control_pbias_offset);
 305                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
 306                 omap_ctrl_writel(reg, control_pbias_offset);
 307
 308                 ret = twl_mmc_set_voltage(c, 0);
 309
 310                 /* 100ms delay required for PBIAS configuration */
 311                 msleep(100);
 312                 reg = omap_ctrl_readl(control_pbias_offset);
 313                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 314                         OMAP2_PBIASLITEVMODE0);
 315                 omap_ctrl_writel(reg, control_pbias_offset);
 316         }
 317
 318         return ret;
 319 }
 320
 321 static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
 322 {
 323         int ret;
 324         struct twl_mmc_controller *c = &hsmmc[1];
 325         struct omap_mmc_platform_data *mmc = dev->platform_data;
 326
 327         /*
 328          * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
 329          * VDDS is used to power the pins, optionally with a transceiver to
 330          * support cards using voltages other than VDDS (1.8V nominal).  When a
 331          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 332          */
 333         if (power_on) {
 334                 if (mmc->slots[0].internal_clock) {
 335                         u32 reg;
 336
 337                         reg = omap_ctrl_readl(control_devconf1_offset);
 338                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 339                         omap_ctrl_writel(reg, control_devconf1_offset);
 340                 }
 341                 ret = twl_mmc_set_voltage(c, vdd);
 342         } else {
 343                 ret = twl_mmc_set_voltage(c, 0);
 344         }
 345
 346         return ret;
 347 }
 348
 349 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
 350
 351 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 352 {
 353         struct twl4030_hsmmc_info *c;
 354         int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
 355
 356         if (cpu_is_omap2430()) {
 357                 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 358                 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 359                 nr_hsmmc = 2;
 360         } else {
 361                 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 362                 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 363         }
 364
 365         for (c = controllers; c->mmc; c++) {
 366                 struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
 367                 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
 368
 369                 if (!c->mmc || c->mmc > nr_hsmmc) {
 370                         pr_debug("MMC%d: no such controller\n", c->mmc);
 371                         continue;
 372                 }
 373                 if (mmc) {
 374                         pr_debug("MMC%d: already configured\n", c->mmc);
 375                         continue;
 376                 }
 377
 378                 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 379                 if (!mmc) {
 380                         pr_err("Cannot allocate memory for mmc device!\n");
 381                         return;
 382                 }
 383
 384                 sprintf(twl->name, "mmc%islot%i", c->mmc, 1);
 385                 mmc->slots[0].name = twl->name;
 386                 mmc->nr_slots = 1;
 387                 mmc->slots[0].wires = c->wires;
 388                 mmc->slots[0].internal_clock = !c->ext_clock;
 389                 mmc->dma_mask = 0xffffffff;
 390
 391                 /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
 392                 if (gpio_is_valid(c->gpio_cd)) {
 393                         mmc->init = twl_mmc_late_init;
 394                         mmc->cleanup = twl_mmc_cleanup;
 395                         mmc->suspend = twl_mmc_suspend;
 396                         mmc->resume = twl_mmc_resume;
 397
 398                         mmc->slots[0].switch_pin = c->gpio_cd;
 399                         mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
 400                         mmc->slots[0].card_detect = twl_mmc_card_detect;
 401                 } else
 402                         mmc->slots[0].switch_pin = -EINVAL;
 403
 404                 /* write protect normally uses an OMAP gpio */
 405                 if (gpio_is_valid(c->gpio_wp)) {
 406                         gpio_request(c->gpio_wp, "mmc_wp");
 407                         gpio_direction_input(c->gpio_wp);
 408
 409                         mmc->slots[0].gpio_wp = c->gpio_wp;
 410                         mmc->slots[0].get_ro = twl_mmc_get_ro;
 411                 } else
 412                         mmc->slots[0].gpio_wp = -EINVAL;
 413
 414                 /* NOTE:  we assume OMAP's MMC1 and MMC2 use
 415                  * the TWL4030's VMMC1 and VMMC2, respectively;
 416                  * and that OMAP's MMC3 isn't used.
 417                  */
 418
 419                 switch (c->mmc) {
 420                 case 1:
 421                         mmc->slots[0].set_power = twl_mmc1_set_power;
 422                         mmc->slots[0].ocr_mask = MMC1_OCR;
 423                         break;
 424                 case 2:
 425                         mmc->slots[0].set_power = twl_mmc2_set_power;
 426                         if (c->transceiver)
 427                                 mmc->slots[0].ocr_mask = MMC2_OCR;
 428                         else
 429                                 mmc->slots[0].ocr_mask = MMC_VDD_165_195;
 430                         break;
 431                 default:
 432                         pr_err("MMC%d configuration not supported!\n", c->mmc);
 433                         continue;
 434                 }
 435                 hsmmc_data[c->mmc - 1] = mmc;
 436         }
 437
 438         omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
 439 }
 440
 441 #endif