2 * Mailbox reservation modules for OMAP2
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt <paul.mundt@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <asm/arch/mailbox.h>
18 #include <asm/arch/irqs.h>
21 #define MAILBOX_REVISION 0x00
22 #define MAILBOX_SYSCONFIG 0x10
23 #define MAILBOX_SYSSTATUS 0x14
24 #define MAILBOX_MESSAGE_0 0x40
25 #define MAILBOX_MESSAGE_1 0x44
26 #define MAILBOX_MESSAGE_2 0x48
27 #define MAILBOX_MESSAGE_3 0x4c
28 #define MAILBOX_MESSAGE_4 0x50
29 #define MAILBOX_MESSAGE_5 0x54
30 #define MAILBOX_FIFOSTATUS_0 0x80
31 #define MAILBOX_FIFOSTATUS_1 0x84
32 #define MAILBOX_FIFOSTATUS_2 0x88
33 #define MAILBOX_FIFOSTATUS_3 0x8c
34 #define MAILBOX_FIFOSTATUS_4 0x90
35 #define MAILBOX_FIFOSTATUS_5 0x94
36 #define MAILBOX_MSGSTATUS_0 0xc0
37 #define MAILBOX_MSGSTATUS_1 0xc4
38 #define MAILBOX_MSGSTATUS_2 0xc8
39 #define MAILBOX_MSGSTATUS_3 0xcc
40 #define MAILBOX_MSGSTATUS_4 0xd0
41 #define MAILBOX_MSGSTATUS_5 0xd4
42 #define MAILBOX_IRQSTATUS_0 0x100
43 #define MAILBOX_IRQENABLE_0 0x104
44 #define MAILBOX_IRQSTATUS_1 0x108
45 #define MAILBOX_IRQENABLE_1 0x10c
46 #define MAILBOX_IRQSTATUS_2 0x110
47 #define MAILBOX_IRQENABLE_2 0x114
48 #define MAILBOX_IRQSTATUS_3 0x118
49 #define MAILBOX_IRQENABLE_3 0x11c
51 unsigned long mbox_base;
53 #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
54 #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
56 struct omap_mbox2_fifo {
58 unsigned long fifo_stat;
59 unsigned long msg_stat;
62 struct omap_mbox2_priv {
63 struct omap_mbox2_fifo tx_fifo;
64 struct omap_mbox2_fifo rx_fifo;
65 unsigned long irqenable;
66 unsigned long irqstatus;
71 struct clk *mbox_ick_handle;
73 static inline unsigned int mbox_read_reg(unsigned int reg)
75 return __raw_readl(mbox_base + reg);
78 static inline void mbox_write_reg(unsigned int val, unsigned int reg)
80 __raw_writel(val, mbox_base + reg);
83 /* Mailbox H/W preparations */
84 static inline int omap2_mbox_startup(struct omap_mbox *mbox)
88 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
89 if (IS_ERR(mbox_ick_handle)) {
90 printk("Could not get mailboxes_ick\n");
93 clk_enable(mbox_ick_handle);
95 /* set smart-idle & autoidle */
96 l = mbox_read_reg(MAILBOX_SYSCONFIG);
98 mbox_write_reg(l, MAILBOX_SYSCONFIG);
103 static inline void omap2_mbox_shutdown(struct omap_mbox *mbox)
105 clk_disable(mbox_ick_handle);
106 clk_put(mbox_ick_handle);
109 /* Mailbox FIFO handle functions */
110 static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
112 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
113 return (mbox_msg_t) mbox_read_reg(fifo->msg);
116 static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
118 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
119 mbox_write_reg(msg, fifo->msg);
122 static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
124 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
125 return (mbox_read_reg(fifo->msg_stat) == 0);
128 static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
130 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
131 return (mbox_read_reg(fifo->fifo_stat));
134 /* Mailbox IRQ handle functions */
135 static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
137 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
138 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
140 l = mbox_read_reg(p->irqenable);
142 mbox_write_reg(l, p->irqenable);
145 static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
147 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
148 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
150 l = mbox_read_reg(p->irqenable);
152 mbox_write_reg(l, p->irqenable);
155 static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
157 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
158 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
160 mbox_write_reg(bit, p->irqstatus);
163 static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
165 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
166 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
167 u32 enable = mbox_read_reg(p->irqenable);
168 u32 status = mbox_read_reg(p->irqstatus);
170 return (enable & status & bit);
173 struct omap_mbox_ops omap2_mbox_ops = {
174 .type = OMAP_MBOX_TYPE2,
175 .startup = omap2_mbox_startup,
176 .shutdown = omap2_mbox_shutdown,
177 .fifo_read = omap2_mbox_fifo_read,
178 .fifo_write = omap2_mbox_fifo_write,
179 .fifo_empty = omap2_mbox_fifo_empty,
180 .fifo_full = omap2_mbox_fifo_full,
181 .enable_irq = omap2_mbox_enable_irq,
182 .disable_irq = omap2_mbox_disable_irq,
183 .ack_irq = omap2_mbox_ack_irq,
184 .is_irq = omap2_mbox_is_irq,
188 * MAILBOX 0: ARM -> DSP,
189 * MAILBOX 1: ARM <- DSP.
190 * MAILBOX 2: ARM -> IVA,
191 * MAILBOX 3: ARM <- IVA.
194 /* FIXME: the following structs should be filled automatically by the user id */
197 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
199 .msg = MAILBOX_MESSAGE_0,
200 .fifo_stat = MAILBOX_FIFOSTATUS_0,
203 .msg = MAILBOX_MESSAGE_1,
204 .msg_stat = MAILBOX_MSGSTATUS_1,
206 .irqenable = MAILBOX_IRQENABLE_0,
207 .irqstatus = MAILBOX_IRQSTATUS_0,
208 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
209 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
212 struct omap_mbox mbox_dsp_info = {
214 .ops = &omap2_mbox_ops,
215 .priv = &omap2_mbox_dsp_priv,
217 EXPORT_SYMBOL(mbox_dsp_info);
220 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
222 .msg = MAILBOX_MESSAGE_2,
223 .fifo_stat = MAILBOX_FIFOSTATUS_2,
226 .msg = MAILBOX_MESSAGE_3,
227 .msg_stat = MAILBOX_MSGSTATUS_3,
229 .irqenable = MAILBOX_IRQENABLE_3,
230 .irqstatus = MAILBOX_IRQSTATUS_3,
231 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
232 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
235 static struct omap_mbox mbox_iva_info = {
237 .ops = &omap2_mbox_ops,
238 .priv = &omap2_mbox_iva_priv,
241 static int __init omap2_mbox_probe(struct platform_device *pdev)
243 struct resource *res;
246 if (pdev->num_resources != 3) {
247 dev_err(&pdev->dev, "invalid number of resources: %d\n",
248 pdev->num_resources);
253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254 if (unlikely(!res)) {
255 dev_err(&pdev->dev, "invalid mem resource\n");
258 mbox_base = res->start;
261 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
262 if (unlikely(!res)) {
263 dev_err(&pdev->dev, "invalid irq resource\n");
266 mbox_dsp_info.irq = res->start;
268 ret = omap_mbox_register(&mbox_dsp_info);
271 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
272 if (unlikely(!res)) {
273 dev_err(&pdev->dev, "invalid irq resource\n");
276 mbox_iva_info.irq = res->start;
278 ret = omap_mbox_register(&mbox_iva_info);
283 static int omap2_mbox_remove(struct platform_device *pdev)
285 omap_mbox_unregister(&mbox_dsp_info);
289 static struct platform_driver omap2_mbox_driver = {
290 .probe = omap2_mbox_probe,
291 .remove = omap2_mbox_remove,
297 int __init omap2_mbox_init(void)
299 return platform_driver_register(&omap2_mbox_driver);
302 static void __exit omap2_mbox_exit(void)
304 platform_driver_unregister(&omap2_mbox_driver);
307 module_init(omap2_mbox_init);
308 module_exit(omap2_mbox_exit);
310 MODULE_LICENSE("GPL");