2 * Mailbox reservation modules for OMAP2
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt <paul.mundt@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/config.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <asm/arch/mailbox.h>
19 #include <asm/arch/irqs.h>
22 #define MAILBOX_REVISION 0x00
23 #define MAILBOX_SYSCONFIG 0x10
24 #define MAILBOX_SYSSTATUS 0x14
25 #define MAILBOX_MESSAGE_0 0x40
26 #define MAILBOX_MESSAGE_1 0x44
27 #define MAILBOX_MESSAGE_2 0x48
28 #define MAILBOX_MESSAGE_3 0x4c
29 #define MAILBOX_MESSAGE_4 0x50
30 #define MAILBOX_MESSAGE_5 0x54
31 #define MAILBOX_FIFOSTATUS_0 0x80
32 #define MAILBOX_FIFOSTATUS_1 0x84
33 #define MAILBOX_FIFOSTATUS_2 0x88
34 #define MAILBOX_FIFOSTATUS_3 0x8c
35 #define MAILBOX_FIFOSTATUS_4 0x90
36 #define MAILBOX_FIFOSTATUS_5 0x94
37 #define MAILBOX_MSGSTATUS_0 0xc0
38 #define MAILBOX_MSGSTATUS_1 0xc4
39 #define MAILBOX_MSGSTATUS_2 0xc8
40 #define MAILBOX_MSGSTATUS_3 0xcc
41 #define MAILBOX_MSGSTATUS_4 0xd0
42 #define MAILBOX_MSGSTATUS_5 0xd4
43 #define MAILBOX_IRQSTATUS_0 0x100
44 #define MAILBOX_IRQENABLE_0 0x104
45 #define MAILBOX_IRQSTATUS_1 0x108
46 #define MAILBOX_IRQENABLE_1 0x10c
47 #define MAILBOX_IRQSTATUS_2 0x110
48 #define MAILBOX_IRQENABLE_2 0x114
49 #define MAILBOX_IRQSTATUS_3 0x118
50 #define MAILBOX_IRQENABLE_3 0x11c
52 unsigned long mbox_base;
54 #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
55 #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
57 struct omap_mbox2_fifo {
59 unsigned long fifo_stat;
60 unsigned long msg_stat;
63 struct omap_mbox2_priv {
64 struct omap_mbox2_fifo tx_fifo;
65 struct omap_mbox2_fifo rx_fifo;
66 unsigned long irqenable;
67 unsigned long irqstatus;
72 struct clk *mbox_ick_handle;
74 static inline unsigned int mbox_read_reg(unsigned int reg)
76 return __raw_readl(mbox_base + reg);
79 static inline void mbox_write_reg(unsigned int val, unsigned int reg)
81 __raw_writel(val, mbox_base + reg);
84 /* Mailbox H/W preparations */
85 static inline int omap2_mbox_startup(struct omap_mbox *mbox)
89 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
90 if (IS_ERR(mbox_ick_handle)) {
91 printk("Could not get mailboxes_ick\n");
94 clk_enable(mbox_ick_handle);
96 /* set smart-idle & autoidle */
97 l = mbox_read_reg(MAILBOX_SYSCONFIG);
99 mbox_write_reg(l, MAILBOX_SYSCONFIG);
104 static inline void omap2_mbox_shutdown(struct omap_mbox *mbox)
106 clk_disable(mbox_ick_handle);
107 clk_put(mbox_ick_handle);
110 /* Mailbox FIFO handle functions */
111 static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
113 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
114 return (mbox_msg_t) mbox_read_reg(fifo->msg);
117 static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
119 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
120 mbox_write_reg(msg, fifo->msg);
123 static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
125 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
126 return (mbox_read_reg(fifo->msg_stat) == 0);
129 static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
131 struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
132 return (mbox_read_reg(fifo->fifo_stat));
135 /* Mailbox IRQ handle functions */
136 static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
138 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
139 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
141 l = mbox_read_reg(p->irqenable);
143 mbox_write_reg(l, p->irqenable);
146 static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
148 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
149 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
151 l = mbox_read_reg(p->irqenable);
153 mbox_write_reg(l, p->irqenable);
156 static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
158 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
159 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
161 mbox_write_reg(bit, p->irqstatus);
164 static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
166 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
167 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
168 u32 enable = mbox_read_reg(p->irqenable);
169 u32 status = mbox_read_reg(p->irqstatus);
171 return (enable & status & bit);
174 struct omap_mbox_ops omap2_mbox_ops = {
175 .type = OMAP_MBOX_TYPE2,
176 .startup = omap2_mbox_startup,
177 .shutdown = omap2_mbox_shutdown,
178 .fifo_read = omap2_mbox_fifo_read,
179 .fifo_write = omap2_mbox_fifo_write,
180 .fifo_empty = omap2_mbox_fifo_empty,
181 .fifo_full = omap2_mbox_fifo_full,
182 .enable_irq = omap2_mbox_enable_irq,
183 .disable_irq = omap2_mbox_disable_irq,
184 .ack_irq = omap2_mbox_ack_irq,
185 .is_irq = omap2_mbox_is_irq,
189 * MAILBOX 0: ARM -> DSP,
190 * MAILBOX 1: ARM <- DSP.
191 * MAILBOX 2: ARM -> IVA,
192 * MAILBOX 3: ARM <- IVA.
195 /* FIXME: the following structs should be filled automatically by the user id */
198 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
200 .msg = MAILBOX_MESSAGE_0,
201 .fifo_stat = MAILBOX_FIFOSTATUS_0,
204 .msg = MAILBOX_MESSAGE_1,
205 .msg_stat = MAILBOX_MSGSTATUS_1,
207 .irqenable = MAILBOX_IRQENABLE_0,
208 .irqstatus = MAILBOX_IRQSTATUS_0,
209 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
210 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
213 static struct omap_mbox mbox_dsp_info = {
215 .ops = &omap2_mbox_ops,
216 .priv = &omap2_mbox_dsp_priv,
220 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
222 .msg = MAILBOX_MESSAGE_2,
223 .fifo_stat = MAILBOX_FIFOSTATUS_2,
226 .msg = MAILBOX_MESSAGE_3,
227 .msg_stat = MAILBOX_MSGSTATUS_3,
229 .irqenable = MAILBOX_IRQENABLE_3,
230 .irqstatus = MAILBOX_IRQSTATUS_3,
231 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
232 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
235 static struct omap_mbox mbox_iva_info = {
237 .ops = &omap2_mbox_ops,
238 .priv = &omap2_mbox_iva_priv,
241 static int __init omap2_mbox_probe(struct platform_device *pdev)
243 struct resource *res;
246 if (pdev->num_resources != 3) {
247 dev_err(&pdev->dev, "invalid number of resources: %d\n",
248 pdev->num_resources);
253 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
254 if (unlikely(!res)) {
255 dev_err(&pdev->dev, "invalid mem resource\n");
258 mbox_base = res->start;
261 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
262 if (unlikely(!res)) {
263 dev_err(&pdev->dev, "invalid irq resource\n");
266 mbox_dsp_info.irq = res->start;
268 ret = omap_mbox_register(&mbox_dsp_info);
271 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
272 if (unlikely(!res)) {
273 dev_err(&pdev->dev, "invalid irq resource\n");
276 mbox_iva_info.irq = res->start;
278 ret = omap_mbox_register(&mbox_iva_info);
283 static int omap2_mbox_remove(struct platform_device *pdev)
285 omap_mbox_unregister(&mbox_dsp_info);
289 static struct platform_driver omap2_mbox_driver = {
290 .probe = omap2_mbox_probe,
291 .remove = omap2_mbox_remove,
297 int __init omap2_mbox_init(void)
299 return platform_driver_register(&omap2_mbox_driver);
302 static void __exit omap2_mbox_exit(void)
304 platform_driver_unregister(&omap2_mbox_driver);
307 module_init(omap2_mbox_init);
308 module_exit(omap2_mbox_exit);
310 MODULE_LICENSE("GPL");