2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <mach/mailbox.h>
18 #include <mach/irqs.h>
21 #define MAILBOX_REVISION 0x000
22 #define MAILBOX_SYSCONFIG 0x010
23 #define MAILBOX_SYSSTATUS 0x014
24 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
25 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
26 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
27 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
28 #define MAILBOX_IRQENABLE(u) (0x108 + 8 * (u))
30 #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
31 #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
33 static void __iomem *mbox_base;
35 struct omap_mbox2_fifo {
37 unsigned long fifo_stat;
38 unsigned long msg_stat;
41 struct omap_mbox2_priv {
42 struct omap_mbox2_fifo tx_fifo;
43 struct omap_mbox2_fifo rx_fifo;
44 unsigned long irqenable;
45 unsigned long irqstatus;
50 static struct clk *mbox_ick_handle;
52 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
53 omap_mbox_type_t irq);
55 static inline unsigned int mbox_read_reg(size_t ofs)
57 return __raw_readl(mbox_base + ofs);
60 static inline void mbox_write_reg(u32 val, size_t ofs)
62 __raw_writel(val, mbox_base + ofs);
65 /* Mailbox H/W preparations */
66 static int omap2_mbox_startup(struct omap_mbox *mbox)
70 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
71 if (IS_ERR(mbox_ick_handle)) {
72 printk("Could not get mailboxes_ick\n");
75 clk_enable(mbox_ick_handle);
77 /* set smart-idle & autoidle */
78 l = mbox_read_reg(MAILBOX_SYSCONFIG);
80 mbox_write_reg(l, MAILBOX_SYSCONFIG);
82 omap2_mbox_enable_irq(mbox, IRQ_RX);
87 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
89 clk_disable(mbox_ick_handle);
90 clk_put(mbox_ick_handle);
93 /* Mailbox FIFO handle functions */
94 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
96 struct omap_mbox2_fifo *fifo =
97 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
98 return (mbox_msg_t) mbox_read_reg(fifo->msg);
101 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
103 struct omap_mbox2_fifo *fifo =
104 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
105 mbox_write_reg(msg, fifo->msg);
108 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
110 struct omap_mbox2_fifo *fifo =
111 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
112 return (mbox_read_reg(fifo->msg_stat) == 0);
115 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
117 struct omap_mbox2_fifo *fifo =
118 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
119 return (mbox_read_reg(fifo->fifo_stat));
122 /* Mailbox IRQ handle functions */
123 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
124 omap_mbox_type_t irq)
126 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
127 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
129 l = mbox_read_reg(p->irqenable);
131 mbox_write_reg(l, p->irqenable);
134 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
135 omap_mbox_type_t irq)
137 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
138 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
140 l = mbox_read_reg(p->irqenable);
142 mbox_write_reg(l, p->irqenable);
145 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
146 omap_mbox_type_t irq)
148 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
149 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
151 mbox_write_reg(bit, p->irqstatus);
154 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
155 omap_mbox_type_t irq)
157 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
158 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
159 u32 enable = mbox_read_reg(p->irqenable);
160 u32 status = mbox_read_reg(p->irqstatus);
162 return (enable & status & bit);
165 static struct omap_mbox_ops omap2_mbox_ops = {
166 .type = OMAP_MBOX_TYPE2,
167 .startup = omap2_mbox_startup,
168 .shutdown = omap2_mbox_shutdown,
169 .fifo_read = omap2_mbox_fifo_read,
170 .fifo_write = omap2_mbox_fifo_write,
171 .fifo_empty = omap2_mbox_fifo_empty,
172 .fifo_full = omap2_mbox_fifo_full,
173 .enable_irq = omap2_mbox_enable_irq,
174 .disable_irq = omap2_mbox_disable_irq,
175 .ack_irq = omap2_mbox_ack_irq,
176 .is_irq = omap2_mbox_is_irq,
180 * MAILBOX 0: ARM -> DSP,
181 * MAILBOX 1: ARM <- DSP.
182 * MAILBOX 2: ARM -> IVA,
183 * MAILBOX 3: ARM <- IVA.
186 /* FIXME: the following structs should be filled automatically by the user id */
189 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
191 .msg = MAILBOX_MESSAGE(0),
192 .fifo_stat = MAILBOX_FIFOSTATUS(0),
195 .msg = MAILBOX_MESSAGE(1),
196 .msg_stat = MAILBOX_MSGSTATUS(1),
198 .irqenable = MAILBOX_IRQENABLE(0),
199 .irqstatus = MAILBOX_IRQSTATUS(0),
200 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
201 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
204 struct omap_mbox mbox_dsp_info = {
206 .ops = &omap2_mbox_ops,
207 .priv = &omap2_mbox_dsp_priv,
209 EXPORT_SYMBOL(mbox_dsp_info);
211 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
212 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
214 .msg = MAILBOX_MESSAGE(2),
215 .fifo_stat = MAILBOX_FIFOSTATUS(2),
218 .msg = MAILBOX_MESSAGE(3),
219 .msg_stat = MAILBOX_MSGSTATUS(3),
221 .irqenable = MAILBOX_IRQENABLE(3),
222 .irqstatus = MAILBOX_IRQSTATUS(3),
223 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
224 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
227 static struct omap_mbox mbox_iva_info = {
229 .ops = &omap2_mbox_ops,
230 .priv = &omap2_mbox_iva_priv,
234 static int __init omap2_mbox_probe(struct platform_device *pdev)
236 struct resource *res;
240 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
241 if (unlikely(!res)) {
242 dev_err(&pdev->dev, "invalid mem resource\n");
245 mbox_base = ioremap(res->start, res->end - res->start);
249 /* DSP or IVA2 IRQ */
250 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
251 if (unlikely(!res)) {
252 dev_err(&pdev->dev, "invalid irq resource\n");
256 mbox_dsp_info.irq = res->start;
258 ret = omap_mbox_register(&mbox_dsp_info);
262 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
263 if (cpu_is_omap2420()) {
265 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
266 if (unlikely(!res)) {
267 dev_err(&pdev->dev, "invalid irq resource\n");
271 mbox_iva_info.irq = res->start;
272 ret = omap_mbox_register(&mbox_iva_info);
280 omap_mbox_unregister(&mbox_dsp_info);
286 static int omap2_mbox_remove(struct platform_device *pdev)
288 #if defined(CONFIG_ARCH_OMAP2420)
289 omap_mbox_unregister(&mbox_iva_info);
291 omap_mbox_unregister(&mbox_dsp_info);
296 static struct platform_driver omap2_mbox_driver = {
297 .probe = omap2_mbox_probe,
298 .remove = omap2_mbox_remove,
304 static int __init omap2_mbox_init(void)
306 return platform_driver_register(&omap2_mbox_driver);
309 static void __exit omap2_mbox_exit(void)
311 platform_driver_unregister(&omap2_mbox_driver);
314 module_init(omap2_mbox_init);
315 module_exit(omap2_mbox_exit);
317 MODULE_LICENSE("GPL v2");
318 MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
319 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");