2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <asm/hardware.h>
17 #include <asm/mach/irq.h>
18 #include <linux/irq.h>
21 /* selected INTC register offsets */
23 #define INTC_REVISION 0x0000
24 #define INTC_SYSCONFIG 0x0010
25 #define INTC_SYSSTATUS 0x0014
26 #define INTC_CONTROL 0x0048
27 #define INTC_MIR_CLEAR0 0x0088
28 #define INTC_MIR_SET0 0x008c
29 #define INTC_PENDING_IRQ0 0x0098
31 /* Number of IRQ state bits in each MIR register */
32 #define IRQ_BITS_PER_REG 32
35 * OMAP2 has a number of different interrupt controllers, each interrupt
36 * controller is identified as its own "bank". Register definitions are
37 * fairly consistent for each bank, but not all registers are implemented
38 * for each bank.. when in doubt, consult the TRM.
40 static struct omap_irq_bank {
41 unsigned long base_reg;
43 } __attribute__ ((aligned(4))) irq_banks[] = {
51 /* INTC bank register get/set */
53 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
55 pr_debug("intc_write_reg: writing 0x%0x to 0x%0x\n", val,
56 (__force u32)(bank->base_reg + reg));
58 omap_writel(val, bank->base_reg + reg);
61 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
63 return omap_readl(bank->base_reg + reg);
66 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
67 static void omap_ack_irq(unsigned int irq)
69 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
72 static void omap_mask_irq(unsigned int irq)
74 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
76 irq &= (IRQ_BITS_PER_REG - 1);
78 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
81 static void omap_unmask_irq(unsigned int irq)
83 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
85 irq &= (IRQ_BITS_PER_REG - 1);
87 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
90 static void omap_mask_ack_irq(unsigned int irq)
96 static struct irq_chip omap_irq_chip = {
98 .ack = omap_mask_ack_irq,
99 .mask = omap_mask_irq,
100 .unmask = omap_unmask_irq,
103 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
107 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
108 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
109 "(revision %ld.%ld) with %d interrupts\n",
110 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
112 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
113 tmp |= 1 << 1; /* soft reset */
114 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
116 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
117 /* Wait for reset to complete */;
119 /* Enable autoidle */
120 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
123 int omap_irq_pending(void)
127 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
128 struct omap_irq_bank *bank = irq_banks + i;
131 for (irq = 0; irq < bank->nr_irqs; irq += IRQ_BITS_PER_REG) {
132 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
134 if (intc_bank_read_reg(bank, (INTC_PENDING_IRQ0 +
143 void __init omap_init_irq(void)
145 unsigned long nr_irqs = 0;
146 unsigned int nr_banks = 0;
149 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
150 struct omap_irq_bank *bank = irq_banks + i;
152 if (cpu_is_omap24xx())
153 bank->base_reg = OMAP24XX_IC_BASE;
154 else if (cpu_is_omap34xx())
155 bank->base_reg = OMAP34XX_IC_BASE;
157 omap_irq_bank_init_one(bank);
159 nr_irqs += bank->nr_irqs;
163 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
164 nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
166 for (i = 0; i < nr_irqs; i++) {
167 set_irq_chip(i, &omap_irq_chip);
168 set_irq_handler(i, handle_level_irq);
169 set_irq_flags(i, IRQF_VALID);