2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
19 #include <mach/common.h>
20 #include <mach/control.h>
23 static void __iomem *tap_base;
24 static u16 tap_prod_id;
26 #define OMAP_TAP_IDCODE 0x0204
27 #define OMAP_TAP_DIE_ID_0 0x0218
28 #define OMAP_TAP_DIE_ID_1 0x021C
29 #define OMAP_TAP_DIE_ID_2 0x0220
30 #define OMAP_TAP_DIE_ID_3 0x0224
32 /* system_rev fields for OMAP2 processors:
33 * CPU id bits [31:16],
34 * CPU device type [15:12], (unprg,normal,POP)
35 * CPU revision [11:08]
36 * CPU class bits [07:00]
40 u16 hawkeye; /* Silicon type (Hawkeye id) */
41 u8 dev; /* Device type from production_id reg */
42 u32 type; /* combined type id copied to system_rev */
45 /* Register values to detect the OMAP version */
46 static struct omap_id omap_ids[] __initdata = {
47 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
48 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
49 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
50 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
51 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
52 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
55 static struct omap_chip_id omap_chip;
58 * omap_chip_is - test whether currently running OMAP matches a chip type
59 * @oc: omap_chip_t to test against
61 * Test whether the currently-running OMAP chip matches the supplied
62 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
64 int omap_chip_is(struct omap_chip_id oci)
66 return (oci.oc & omap_chip.oc) ? 1 : 0;
68 EXPORT_SYMBOL(omap_chip_is);
74 if (cpu_is_omap24xx()) {
75 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
76 } else if (cpu_is_omap34xx()) {
77 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
79 pr_err("Cannot detect omap type!\n");
83 val &= OMAP2_DEVICETYPE_MASK;
89 EXPORT_SYMBOL(omap_type);
91 static u32 __init read_tap_reg(int reg)
93 unsigned int regval = 0;
96 /* Reading the IDCODE register on 3430 ES1 results in a
97 * data abort as the register is not exposed on the OCP
98 * Hence reading the Cortex Rev
100 cpuid = read_cpuid(CPUID_ID);
102 /* If the processor type is Cortex-A8 and the revision is 0x0
103 * it means its Cortex r0p0 which is 3430 ES1
105 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
107 if (reg == tap_prod_id) {
113 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
114 /* Making DevType as 0xF in ES1 to differ from ES2 */
115 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
116 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
117 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
118 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
121 regval = __raw_readl(tap_base + reg);
129 * _set_system_rev - set the system_rev global based on current OMAP chip type
131 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
134 static void __init _set_system_rev(u32 type, u8 rev)
139 * system_rev encoding is as follows
140 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
141 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
142 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
143 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
144 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
145 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
146 * system_rev & 0x0000003f -> sys_boot[0:5]
148 /* Embedding the ES revision info in type field */
150 /* Also add IDCODE revision info only two lower bits */
151 system_rev |= ((rev & 0x3) << 6);
153 /* Add in the device type and sys_boot fields (see above) */
154 if (cpu_is_omap24xx()) {
155 i = OMAP24XX_CONTROL_STATUS;
156 } else if (cpu_is_omap343x()) {
157 i = OMAP343X_CONTROL_STATUS;
159 printk(KERN_ERR "id: unknown CPU type\n");
162 ctrl_status = omap_ctrl_readl(i);
163 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
164 OMAP2_SYSBOOT_4_MASK |
165 OMAP2_SYSBOOT_3_MASK |
166 OMAP2_SYSBOOT_2_MASK |
167 OMAP2_SYSBOOT_1_MASK |
168 OMAP2_SYSBOOT_0_MASK));
169 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
174 * _set_omap_chip - set the omap_chip global based on OMAP chip type
176 * Build the omap_chip bits. This variable is used by powerdomain and
177 * clockdomain code to indicate whether structures are applicable for
178 * the current OMAP chip type by ANDing it against a 'platform' bitfield
181 static void __init _set_omap_chip(void)
183 if (cpu_is_omap343x()) {
185 omap_chip.oc = CHIP_IS_OMAP3430;
186 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
187 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
188 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
189 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
191 } else if (cpu_is_omap243x()) {
193 /* Currently only supports 2430ES2.1 and 2430-all */
194 omap_chip.oc |= CHIP_IS_OMAP2430;
196 } else if (cpu_is_omap242x()) {
198 /* Currently only supports 2420ES2.1.1 and 2420-all */
199 omap_chip.oc |= CHIP_IS_OMAP2420;
203 /* Current CPU not supported by this code. */
204 printk(KERN_WARNING "OMAP chip type code does not yet support "
212 void __init omap24xx_check_revision(void)
221 idcode = read_tap_reg(OMAP_TAP_IDCODE);
222 prod_id = read_tap_reg(tap_prod_id);
223 hawkeye = (idcode >> 12) & 0xffff;
224 rev = (idcode >> 28) & 0x0f;
225 dev_type = (prod_id >> 16) & 0x0f;
227 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
228 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
229 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
230 read_tap_reg(OMAP_TAP_DIE_ID_0));
231 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
232 read_tap_reg(OMAP_TAP_DIE_ID_1),
233 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
234 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
235 read_tap_reg(OMAP_TAP_DIE_ID_2));
236 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
237 read_tap_reg(OMAP_TAP_DIE_ID_3));
238 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
241 /* Check hawkeye ids */
242 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
243 if (hawkeye == omap_ids[i].hawkeye)
247 if (i == ARRAY_SIZE(omap_ids)) {
248 printk(KERN_ERR "Unknown OMAP CPU id\n");
252 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
253 if (dev_type == omap_ids[j].dev)
257 if (j == ARRAY_SIZE(omap_ids)) {
258 printk(KERN_ERR "Unknown OMAP device type. "
259 "Handling it as OMAP%04x\n",
260 omap_ids[i].type >> 16);
264 _set_system_rev(omap_ids[j].type, rev);
268 pr_info("OMAP%04x", system_rev >> 16);
269 if ((system_rev >> 8) & 0x0f)
270 pr_info("ES%x", (system_rev >> 12) & 0xf);
275 void __init omap34xx_check_revision(void)
282 idcode = read_tap_reg(OMAP_TAP_IDCODE);
283 prod_id = read_tap_reg(tap_prod_id);
284 hawkeye = (idcode >> 12) & 0xffff;
285 rev = (idcode >> 28) & 0x0f;
288 * Detection for 34xx ES2.0 and above can be done with just
289 * hawkeye and rev. See TRM 1.5.2 Device Identification.
290 * Note that rev cannot be used directly as ES1.0 uses value 0.
292 if (hawkeye == 0xb7ae) {
293 system_rev = 0x34300000 | ((1 + rev) << 12);
294 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
300 void __init omap2_check_revision(void)
303 * At this point we have an idea about the processor revision set
304 * earlier with omap2_set_globals_tap().
306 if (cpu_is_omap24xx())
307 omap24xx_check_revision();
308 else if (cpu_is_omap34xx())
309 omap34xx_check_revision();
311 pr_err("OMAP revision unknown, please fix!\n");
315 * Set up things for map_io and processor detection later on. Gets called
316 * pretty much first thing from board init. For multi-omap, this gets
317 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
318 * detect the exact revision later on in omap2_detect_revision() once map_io
321 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
323 system_rev = omap2_globals->class;
324 tap_base = omap2_globals->tap;
326 if (cpu_is_omap34xx())
327 tap_prod_id = 0x0210;
329 tap_prod_id = 0x0208;