2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
22 #if defined(CONFIG_ARCH_OMAP2420)
23 #define TAP_BASE io_p2v(0x48014000)
24 #elif defined(CONFIG_ARCH_OMAP2430)
25 #define TAP_BASE io_p2v(0x4900A000)
26 #elif defined(CONFIG_ARCH_OMAP34XX)
27 #define TAP_BASE io_p2v(0x4830A000)
30 #define OMAP_TAP_IDCODE 0x0204
31 #if defined(CONFIG_ARCH_OMAP34XX)
32 #define OMAP_TAP_PROD_ID 0x0210
34 #define OMAP_TAP_PROD_ID 0x0208
37 #define OMAP_TAP_DIE_ID_0 0x0218
38 #define OMAP_TAP_DIE_ID_1 0x021C
39 #define OMAP_TAP_DIE_ID_2 0x0220
40 #define OMAP_TAP_DIE_ID_3 0x0224
42 /* system_rev fields for OMAP2 processors:
43 * CPU id bits [31:16],
44 * CPU device type [15:12], (unprg,normal,POP)
45 * CPU revision [11:08]
46 * CPU class bits [07:00]
50 u16 hawkeye; /* Silicon type (Hawkeye id) */
51 u8 dev; /* Device type from production_id reg */
52 u32 type; /* combined type id copied to system_rev */
55 /* Register values to detect the OMAP version */
56 static struct omap_id omap_ids[] __initdata = {
57 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
58 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
59 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
60 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
61 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
62 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
63 { .hawkeye = 0xb7ae, .dev = 0xf, .type = 0x34300000 },
64 { .hawkeye = 0xb7ae, .dev = 0x0, .type = 0x34301000 },
67 static u32 __init read_tap_reg(int reg)
69 unsigned int regval = 0;
72 /* Reading the IDCODE register on 3430 ES1 results in a
73 * data abort as the register is not exposed on the OCP
74 * Hence reading the Cortex Rev
76 cpuid = read_cpuid(CPUID_ID);
78 /* If the processor type is Cortex-A8 and the revision is 0x0
79 * it means its Cortex r0p0 which is 3430 ES1
81 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
83 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
84 /* Making DevType as 0xF in ES1 to differ from ES2 */
85 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
86 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
87 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
88 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
89 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
92 regval = __raw_readl(TAP_BASE + reg);
98 void __init omap2_check_revision(void)
108 idcode = read_tap_reg(OMAP_TAP_IDCODE);
109 prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
110 hawkeye = (idcode >> 12) & 0xffff;
111 rev = (idcode >> 28) & 0x0f;
112 dev_type = (prod_id >> 16) & 0x0f;
115 printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
116 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
117 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
118 read_tap_reg(OMAP_TAP_DIE_ID_0));
119 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
120 read_tap_reg(OMAP_TAP_DIE_ID_1),
121 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
122 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
123 read_tap_reg(OMAP_TAP_DIE_ID_2));
124 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
125 read_tap_reg(OMAP_TAP_DIE_ID_3));
126 printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
130 /* Check hawkeye ids */
131 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
132 if (hawkeye == omap_ids[i].hawkeye)
136 if (i == ARRAY_SIZE(omap_ids)) {
137 printk(KERN_ERR "Unknown OMAP CPU id\n");
141 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
142 if (dev_type == omap_ids[j].dev)
146 if (j == ARRAY_SIZE(omap_ids)) {
147 printk(KERN_ERR "Unknown OMAP device type. "
148 "Handling it as OMAP%04x\n",
149 omap_ids[i].type >> 16);
154 * system_rev encoding is as follows
155 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
156 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
157 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
158 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
159 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
160 * system_rev & 0x0000003f -> sys_boot[0:5]
162 /* Embedding the ES revision info in type field */
163 system_rev = omap_ids[j].type;
165 /* Add in the device type and sys_boot fields (see above) */
166 if (cpu_is_omap24xx()) {
167 i = OMAP24XX_CONTROL_STATUS;
168 } else if (cpu_is_omap343x()) {
169 i = OMAP343X_CONTROL_STATUS;
171 printk(KERN_ERR "id: unknown CPU type\n");
174 ctrl_status = ctrl_read_reg(i);
175 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
176 OMAP2_SYSBOOT_4_MASK |
177 OMAP2_SYSBOOT_3_MASK |
178 OMAP2_SYSBOOT_2_MASK |
179 OMAP2_SYSBOOT_1_MASK |
180 OMAP2_SYSBOOT_0_MASK));
181 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
183 pr_info("OMAP%04x", system_rev >> 16);
184 if ((system_rev >> 8) & 0x0f)
185 printk("ES%x", (system_rev >> 12) & 0xf);